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2025-07-31aarch64: Prevent streaming-compatible code from assembler rejection [PR121028]Spencer Abson4-6/+61
Streaming-compatible functions can be compiled without SME enabled, but need to use "SMSTART SM" and "SMSTOP SM" to temporarily switch into the streaming state of a callee. These switches are conditional on the current mode being opposite to the target mode, so no SME instructions are executed if SME is not available. However, in GAS, "SMSTART SM" and "SMSTOP SM" always require +sme. A call from a streaming-compatible function, compiled without SME enabled, to a non -streaming function will be rejected as: Error: selected processor does not support `smstop sm'.. To work around this, we make use of the .inst directive to insert the literal encodings of "SMSTART SM" and "SMSTOP SM". gcc/ChangeLog: PR target/121028 * config/aarch64/aarch64-sme.md (aarch64_smstart_sm): Use the .inst directive if !TARGET_SME. (aarch64_smstop_sm): Likewise. gcc/testsuite/ChangeLog: PR target/121028 * gcc.target/aarch64/sme/call_sm_switch_1.c: Tell check-function -bodies not to ignore .inst directives, and replace the test for "smstart sm" with one for it's encoding. * gcc.target/aarch64/sme/call_sm_switch_11.c: Likewise. * gcc.target/aarch64/sme/pr121028.c: New test.
2025-07-31Remove STMT_VINFO_MEMORY_ACCESS_TYPERichard Biener5-38/+19
This should be present only on SLP nodes now. The RISC-V changes are mechanical along the line of the SLP_TREE_TYPE changes. * tree-vectorizer.h (_stmt_vec_info::memory_access_type): Remove. (STMT_VINFO_MEMORY_ACCESS_TYPE): Likewise. (vect_mem_access_type): Likewise. * tree-vect-stmts.cc (vectorizable_store): Do not set STMT_VINFO_MEMORY_ACCESS_TYPE. Fix SLP_TREE_MEMORY_ACCESS_TYPE usage. * tree-vect-loop.cc (update_epilogue_loop_vinfo): Remove checking of memory access type. * config/riscv/riscv-vector-costs.cc (costs::compute_local_live_ranges): Use SLP_TREE_MEMORY_ACCESS_TYPE. (costs::need_additional_vector_vars_p): Likewise. (segment_loadstore_group_size): Get SLP node as argument, use SLP_TREE_MEMORY_ACCESS_TYPE. (costs::adjust_stmt_cost): Pass down SLP node. * config/aarch64/aarch64.cc (aarch64_ld234_st234_vectors): Use SLP_TREE_MEMORY_ACCESS_TYPE instead of vect_mem_access_type. (aarch64_detect_vector_stmt_subtype): Likewise. (aarch64_vector_costs::count_ops): Likewise. (aarch64_vector_costs::add_stmt_cost): Likewise.
2025-07-31Do not bother with fake verifying of shared DRsRichard Biener1-4/+2
The following avoids comparing the shared DRs against their unmodified copy for epilogues during loop transform since they are actually modified by update_epilogue_loop_vinfo. Avoid the pointless faking of the original DRs there. * tree-vect-loop.cc (vect_transform_loop): Do not verify DRs have not been modified for epilogue loops. (update_epilogue_loop_vinfo): Do not copy modified DRs to the originals.
2025-07-31change get_best_mode args int -> HOST_WIDE_INT [PR121264]Jakub Jelinek3-2/+15
The following testcase is miscompiled, because byte 0x20000000 is bit 0x100000000 and ifcombine incorrectly combines the two loads into a BIT_FIELD_REF even when they are very far away. The problem is that gimple-fold.cc ifcombine uses get_best_mode heavily, and that function has just int bitsize and int bitpos arguments, so when called e.g. with if (get_best_mode (end_bit - first_bit, first_bit, 0, ll_end_region, ll_align, BITS_PER_WORD, volatilep, &lnmode)) where end_bit - first_bit doesn't fit into int, it is silently truncated. If there was just a single problematic get_best_mode call, I would probably just check for overflows in the caller, but there are many. And the two arguments are used solely as arguments to bit_field_mode_iterator constructor which has HOST_WIDE_INT arguments, so I think the easiest fix is just make the get_best_mode arguments also HOST_WIDE_INT. 2025-07-31 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/121264 * machmode.h (get_best_mode): Change type of first 2 arguments from int to HOST_WIDE_INT. * stor-layout.cc (get_best_mode): Likewise. * gcc.dg/tree-ssa/pr121264.c: New test.
2025-07-31aarch64: testsuite: Fix do-assemble tests for SMESpencer Abson13-4/+48
GCC doesn't support SME without SVE2, so the -march=armv8-a+<ext> argument to check_no_compiler_messages causes aarch64_asm_<ext>_ok to return zero for SME and any <ext> that implies it. This patch changes the baseline architecure to armv9-a for these extensions. The tests for ACLE SME2 intrinsics that require FEAT_FAMINMAX were configured to do-assemble if aarch64_asm_sme2_ok returned 1 (by default), but they really need to check if +faminmax is supported too. The fix above exposed this, so we also fix the do-assemble/do-compile choice for those tests here. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sme2/acle-asm/amax_f16_x2.c: Gate do-assemble on assembler support for +faminmax and +sme2. * gcc.target/aarch64/sme2/acle-asm/amax_f16_x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amax_f32_x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amax_f32_x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amax_f64_x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amax_f64_x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amin_f16_x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amin_f16_x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amin_f32_x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amin_f32_x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amin_f64_x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/amin_f64_x4.c: Likewise. * lib/target-supports.exp: Split the extensions that require SME into a separate set, and use armv9-a as their baseline.
2025-07-31Fix comment typos - hanlde -> handleJakub Jelinek6-8/+8
2025-07-31 Jakub Jelinek <jakub@redhat.com> * gimple-ssa-store-merging.cc (find_bswap_or_nop): Fix comment typos, hanlde -> handle. * config/i386/i386.cc (ix86_gimple_fold_builtin, ix86_rtx_costs): Likewise. * config/i386/i386-features.cc (remove_partial_avx_dependency): Likewise. * gcc.target/i386/apx-1.c (apx_hanlder): Rename to ... (apx_handler): ... this. * gcc.target/i386/uintr-2.c (UINTR_hanlder): Rename to ... (UINTR_handler): ... this. * gcc.target/i386/uintr-5.c (UINTR_hanlder): Rename to ... (UINTR_handler): ... this.
2025-07-31Disallow scan-store vectorization in epiloguesRichard Biener1-1/+2
The following disallows vectorizing epilogues containing scan-stores. Since code generation works by walking gimple stmts it is not ready for this when cleaning up epilogue vectorization. I believe scan-store vectorization needs most of the work done during SLP discovery to reflect the data flow. * tree-vect-stmts.cc (check_scan_store): Remove redundant slp_node check. Disallow epilogue vectorization.
2025-07-31Avoid passing vectype != NULL when costing scalar ILRichard Biener1-0/+8
The following makes sure to not leak a set vectype on a stmt when doing scalar IL costing as this can confuse vector cost models which do not look at m_costing_for_scalar most of the time. * tree-vectorizer.h (vector_costs::costing_for_scalar): New accessor. (add_stmt_cost): For scalar costing force vectype to NULL. Verify we do not pass in a SLP node.
2025-07-31RISC-V: Adding H to the canonical order [PR121312]Kito Cheng1-1/+1
We added H into canonical order before, but forgot to add it to arch-canonicalize as well... gcc/ChangeLog: PR target/121312 * config/riscv/arch-canonicalize: Add H extension to the canonical order.
2025-07-31Daily bump.GCC Administrator9-1/+421
2025-07-30[sanitizer_common] Remove reference to obsolete termio ioctls (#138822)Sam James2-8/+0
Cherry picked from LLVM commit c99b1bcd505064f2e086e6b1034ce0b0c91ea5b9. The termio ioctls are no longer used after commit 59978b21ad9c ("[sanitizer_common] Remove interceptors for deprecated struct termio (#137403)"), remove them. Fixes this build error: ../../../../libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp:765:27: error: invalid application of ‘sizeof’ to incomplete type ‘__sanitizer::termio’ 765 | unsigned IOCTL_TCGETA = TCGETA; | ^~~~~~ ../../../../libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp:769:27: error: invalid application of ‘sizeof’ to incomplete type ‘__sanitizer::termio’ 769 | unsigned IOCTL_TCSETA = TCSETA; | ^~~~~~ ../../../../libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp:770:28: error: invalid application of ‘sizeof’ to incomplete type ‘__sanitizer::termio’ 770 | unsigned IOCTL_TCSETAF = TCSETAF; | ^~~~~~~ ../../../../libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp:771:28: error: invalid application of ‘sizeof’ to incomplete type ‘__sanitizer::termio’ 771 | unsigned IOCTL_TCSETAW = TCSETAW; | ^~~~~~~
2025-07-30Update cpplib sr.poJoseph Myers1-528/+357
* sr.po: Update.
2025-07-31c++: Don't assume trait funcs return error_mark_node when tf_error is passed ↵Nathaniel Shead5-30/+52
[PR121291] For the sake of determining if there are other errors in user code to report early, many trait functions don't always return error_mark_node if not called in a SFINAE context (i.e., tf_error is set). This patch removes some assumptions on this behaviour I'd made when improving diagnostics of builtin traits. PR c++/121291 gcc/cp/ChangeLog: * constraint.cc (diagnose_trait_expr): Remove assumption about failures returning error_mark_node. * except.cc (explain_not_noexcept): Allow expr not being noexcept. * method.cc (build_invoke): Adjust comment. (is_trivially_xible): Always note non-trivial components if expr is not null or error_mark_node. (is_nothrow_xible): Likewise for non-noexcept components. (is_nothrow_convertible): Likewise. gcc/testsuite/ChangeLog: * g++.dg/ext/is_invocable7.C: New test. * g++.dg/ext/is_nothrow_convertible5.C: New test. Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com> Reviewed-by: Patrick Palka <ppalka@redhat.com>
2025-07-30libstdc++: Fix test when dual abi disabledFrançois Dumont1-2/+2
When !_GLIBCXX_USE_DUAL_ABI the old COW std::string implementation is being used which do not generate the expected error diagnostics. libstdc++-v3/ChangeLog: * testsuite/std/time/format/data_not_present_neg.cc: Remove _GLIBCXX_USE_DUAL_ABI check. Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
2025-07-30c++: improve non-constant template arg diagnosticJason Merrill4-26/+45
A conversation today pointed out that the current diagnostic for this case doesn't mention the constant evaluation failure, it just says e.g. "'p' is not a valid template argument for 'int*' because it is not the address of a variable" This patch improves the diagnostic in C++17 and above (post-N4268) to diagnose failed constant-evaluation. gcc/cp/ChangeLog: * pt.cc (convert_nontype_argument_function): Check cxx_constant_value on failure. (invalid_tparm_referent_p): Likewise. gcc/testsuite/ChangeLog: * g++.dg/tc1/dr49.C: Adjust diagnostic. * g++.dg/template/func2.C: Likewise. * g++.dg/cpp1z/nontype8.C: New test.
2025-07-30simplify-rtx: Add `(subreg (not a))` simplification for word_mode [PR121308]Andrew Pinski1-0/+9
Right now in simplify_subreg, there is code to try to simplify for word_mode with the binary bitwise operators. The unary bitwise operator is not handle, this causes an odd mix match and the new self testing code that was added with r16-2614-g965564eafb721f was not expecting. The self testing code was for testing the newly added code but since there was already code that handles word_mode, we hit the mismatch but only for targets where word_mode is SImode (or smaller). This adds the code to handle `not` in a similar fashion as the other bitwise operators for word_mode. Changes since v1: * v2: add `&& SCALAR_INT_MODE_P (innermode)` to the conditional. Bootstrapped and tested on x86_64-linux-gnu. PR rtl-optimization/121308 gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_subreg): Handle subreg of `not` with word_mode to make it symmetric with the other bitwise operators. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2025-07-30IFCVT: Fix factor_out_operators correctly for more than 1 phi [PR121295]Andrew Pinski3-0/+40
r16-2590-ga51bf9e10182cf was not the correct fix for this in the end. Instead a much simplier and localized fix is needed, just change the phi that is being worked on with the new result and arguments that is from the factored out operator. This solves the issue of not having result in the IR and causing issues that way. Bootstrapped and tested on x86_64-linux-gnu. Note this depends on reverting r16-2590-ga51bf9e10182cf. PR tree-optimization/121236 PR tree-optimization/121295 gcc/ChangeLog: * tree-if-conv.cc (factor_out_operators): Change the phi node to the new result and args. gcc/testsuite/ChangeLog: * gcc.dg/torture/pr121236-1.c: New test. * gcc.dg/torture/pr121295-1.c: New test. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2025-07-30Revert "ifcvt: Fix ifcvt for multiple phi nodes after factoring operator ↵Andrew Pinski2-55/+25
[PR121236]" This reverts commit a51bf9e10182cf7ac858db0ea6c5cb11b4f12377.
2025-07-30Report read errors when reading auto-profileJan Hubicka3-2/+13
currently -fauto-profile will happily read truncated file without any warning and interpret it as a zero profile which will in turn result in slow code. This patch exports gcov_is_error and adds checks so truncated files are detected. gcc/ChangeLog: * auto-profile.cc (string_table::read): Check gcov_is_error. (read_profile): Likewise. * gcov-io.cc (gcov_is_error): Export for gcc linkage. * gcov-io.h (gcov_is_error): Declare.
2025-07-30[x86] factor out worker from ix86_builtin_vectorization_costRichard Biener1-18/+23
The following factors out a worker that gets a mode argument rather than a vectype argument. That makes a difference when we hit the fallback in add_stmt_cost for scalar stmts where vectype might be NULL and thus mode is derived from the scalar stmt there. But ix86_builtin_vectorization_cost does not have access to the stmt. So the patch instead dispatches to the new ix86_default_vector_cost there, passing down the mode we derived from the stmt. This is to avoid regressions with a patch that makes even more scalar stmt costings have a vectype passed. * config/i386/i386.cc (ix86_default_vector_cost): Split out from ... (ix86_builtin_vectorization_cost): ... this and use mode instead of vectype as argument. (ix86_vector_costs::add_stmt_cost): Call ix86_default_vector_cost instead of ix86_builtin_vectorization_cost.
2025-07-30s390: Implement spaceship optab [PR117015]Stefan Schulze Frielinghaus10-0/+381
gcc/ChangeLog: PR target/117015 * config/s390/s390-protos.h (s390_expand_int_spaceship): New function. (s390_expand_fp_spaceship): New function. * config/s390/s390.cc (s390_expand_int_spaceship): New function. (s390_expand_fp_spaceship): New function. * config/s390/s390.md (spaceship<mode>4): New expander. gcc/testsuite/ChangeLog: * gcc.target/s390/spaceship-fp-1.c: New test. * gcc.target/s390/spaceship-fp-2.c: New test. * gcc.target/s390/spaceship-fp-3.c: New test. * gcc.target/s390/spaceship-fp-4.c: New test. * gcc.target/s390/spaceship-int-1.c: New test. * gcc.target/s390/spaceship-int-2.c: New test. * gcc.target/s390/spaceship-int-3.c: New test.
2025-07-30cprop: Allow jump bypassing for single set insnsStefan Schulze Frielinghaus1-6/+18
During jump bypassing also consider insns of the form (insn 25 57 26 9 (parallel [ (set (reg:CCZ 33 %cc) (compare:CCZ (reg:SI 60 [ _9 ]) (const_int 0 [0]))) (clobber (scratch:SI)) ]) "spaceship-fp-4.c":27:1 1746 {*tstsi_cconly_extimm} (nil)) by testing for a single set insn during bypass_conditional_jumps(). This is a requirement for test gcc.target/s390/spaceship-fp-4.c of the subsequent commit. In order to silence cprop.cc:1621:40: error: 'setcc_dest' may be used uninitialized [-Werror=maybe-uninitialized] 1621 | src = simplify_replace_rtx (src, setcc_dest, setcc_src); | ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~ initialize setcc_{dest,src} in bypass_block() although this is not really required. gcc/ChangeLog: * cprop.cc (bypass_block): Extract single set. (bypass_conditional_jumps): Ditto.
2025-07-30x86: Transform to "pushq $-1; popq reg" for -OzH.J. Lu2-1/+12
commit 4c80062d7b8c272e2e193b8074a8440dbb4fe588 Author: H.J. Lu <hjl.tools@gmail.com> Date: Sun May 25 07:40:29 2025 +0800 x86: Enable *mov<mode>_(and|or) only for -Oz disabled transformation from "movq $-1,reg" to "pushq $-1; popq reg" for -Oz. But for legacy integer registers, the former is 4 bytes and the latter is 3 bytes. Enable such transformation for -Oz. gcc/ PR target/120427 * config/i386/i386.md (peephole2): Transform "movq $-1,reg" to "pushq $-1; popq reg" for -Oz if reg is a legacy integer register. gcc/testsuite/ PR target/120427 * gcc.target/i386/pr120427-5.c: New test. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-07-30auto-profile fixesJan Hubicka1-3/+9
This patch silences warning about bad location in function_instance::match warning about profile containing record for line numbers that are not matched by the function body. While this is a bogus profile (and we will end up losing the profile data), create_gcov does not have enough information to output them correctly in all contexts since in dwarf5 we output multiple locations per single instructions (possibly comming from different inlines) while it can only represent one inline stack. The patch also fixes issue with profile scaling. By making force_nonzero to take into account cutoffs, I made the test for counter being non-zero before scaling too agressive. gcc/ChangeLog: * auto-profile.cc (function_instance::match): Disable warning about bogus locations since dwarf does not represent enough info to output them correctly in all cases. (add_scale): Use nonzero_p instead of orig.force_nonzero () == orig. (afdo_adjust_guessed_profile): Add missing newline in dump file.
2025-07-30Fix symbol_table::change_decl_assembler_name when DECL_RTL is already computedJan Hubicka1-0/+5
while working on patch assigning unique names to static symbols I noticed that fortran symbols are not renamed since the frontend calls make_decl_rtl. This gets DECL_ASSEMBBLER_NAME and DECL_RTL out of sync. I think we can drop that call, but it is also good idea to avoid this inconsistence, so this patch makes symbol_table::change_decl_assembler_name to recompute DECL_RTL in this case. gcc/ChangeLog: * symtab.cc (symbol_table::change_decl_assembler_name): Recompute DECL_RTL in case it is already computed.
2025-07-30Fix fasle profile insonsistency errorJan Hubicka2-2/+60
This patch fixes false incosistent profile error message seen when building SPEC with -fprofile-use -fdump-ipa-profile. The problem is that with dumping tree_esitmate_probability is run in dry run mode to report success rates of heuristics. It however runs determine_unlikely_bbs which ovewrites some counts to profile_count::zero and later value profiling sees the mismatch. In sane profile determine_unlikely_bbs should be almost always no-op since it should only drop to 0 things that are known to be unlikely executed. What happens here is that there is a comdat where profile is lost and we see a call with non-zero count calling function with zero count and "fix" the profile by making the call to have zero count, too. I also extended unlikely prediates to avoid tampering with predictions when prediciton is believed to be reliable. This also avoids us from dropping all EH regions to 0 count as tested by the testcase. gcc/ChangeLog: * predict.cc (unlikely_executed_edge_p): Ignore EDGE_EH if profile is reliable. (unlikely_executed_stmt_p): special case builtin_trap/unreachable and ignore other heuristics for reliable profiles. (tree_estimate_probability): Disable unlikely bb detection when doing dry run gcc/testsuite/ChangeLog: * g++.dg/tree-prof/eh1.C: New test.
2025-07-30vect: Add target hook to prefer gather/scatter instructionsAndrew Stubbs7-10/+68
For AMD GCN, the instructions available for loading/storing vectors are always scatter/gather operations (i.e. there are separate addresses for each vector lane), so the current heuristic to avoid gather/scatter operations with too many elements in get_group_load_store_type is counterproductive. Avoiding such operations in that function can subsequently lead to a missed vectorization opportunity whereby later analyses in the vectorizer try to use a very wide array type which is not available on this target, and thus it bails out. This patch adds a target hook to override the "single_element_p" heuristic in the function as a target hook, and activates it for GCN. This allows much better code to be generated for affected loops. Co-authored-by: Julian Brown <julian@codesourcery.com> gcc/ * doc/tm.texi.in (TARGET_VECTORIZE_PREFER_GATHER_SCATTER): Add documentation hook. * doc/tm.texi: Regenerate. * target.def (prefer_gather_scatter): Add target hook under vectorizer. * hooks.cc (hook_bool_mode_int_unsigned_false): New function. * hooks.h (hook_bool_mode_int_unsigned_false): New prototype. * tree-vect-stmts.cc (vect_use_strided_gather_scatters_p): Add parameters group_size and single_element_p, and rework to use targetm.vectorize.prefer_gather_scatter. (get_group_load_store_type): Move some of the condition into vect_use_strided_gather_scatters_p. * config/gcn/gcn.cc (gcn_prefer_gather_scatter): New function. (TARGET_VECTORIZE_PREFER_GATHER_SCATTER): Define hook.
2025-07-30Don't pass vector params through to offload targetsAndrew Stubbs3-5/+26
The optimization options are deliberately passed through to the LTO compiler, but when the same mechanism is reused for offloading it ends up forcing the host compiler settings onto the device compiler. Maybe this should be removed completely, but this patch just fixes a few of them. In particular, param_vect_partial_vector_usage is disabled by x86 and this really hurts amdgcn. I also fixed an ambiguous else warning in the generated file by adding braces. gcc/ChangeLog: * config/gcn/gcn.cc (gcn_option_override): Add note to set default for param_vect_partial_vector_usage to "1". * optc-save-gen.awk: Don't pass through options marked "NoOffload". * params.opt (-param=vect-epilogues-nomask): Add NoOffload. (-param=vect-partial-vector-usage): Likewise. (-param=vect-inner-loop-cost-factor): Likewise.
2025-07-30tree-optimization/121130 - vectorizable_call cannot handle .MASK_CALLRichard Biener2-1/+18
The following makes it correctly reject them, vectorizable_simd_clone_call is solely responsible for them. PR tree-optimization/121130 * tree-vect-stmts.cc (vectorizable_call): Bail out for .MASK_CALL. * gcc.dg/vect/vect-simd-pr121130.c: New testcase.
2025-07-30c++: Make __extension__ silence -Wlong-long pedwarns/warnings [PR121133]Jakub Jelinek5-11/+52
The PR13358 r0-92909 change changed the diagnostics on long long in C++ (either with -std=c++98 or -Wlong-long), but unlike the C FE we unfortunately warn even in the __extension__ long long a; etc. cases. The C FE in that case in disable_extension_diagnostics saves and clears not just pedantic flag but also warn_long_long (and several others), while C++ FE only temporarily disables pedantic. The following patch makes it behave like the C FE in this regard, though (__extension__ 1LL) still doesn't work because of the separate lexing (and I must say I have no idea how to fix that). Or do you prefer a solution closer to the C FE, cp_parser_extension_opt saving the values into a bitfield and have another function to restore the state (or use RAII)? 2025-07-30 Jakub Jelinek <jakub@redhat.com> PR c++/121133 * parser.cc (cp_parser_unary_expression): Adjust cp_parser_extension_opt caller and restore warn_long_long. (cp_parser_declaration): Likewise. (cp_parser_block_declaration): Likewise. (cp_parser_member_declaration): Likewise. (cp_parser_extension_opt): Add SAVED_LONG_LONG argument, save previous warn_long_long state into it and clear it for __extension__. * g++.dg/warn/pr121133-1.C: New test. * g++.dg/warn/pr121133-2.C: New test. * g++.dg/warn/pr121133-3.C: New test. * g++.dg/warn/pr121133-4.C: New test.
2025-07-30libcpp: Fix up comma diagnostics in preprocessor for C++ [PR120778]Jakub Jelinek3-3/+60
The P2843R3 Preprocessing is never undefined paper contains comments that various compilers handle comma operators in preprocessor expressions incorrectly and I think they are right. In both C and C++ the grammar uses constant-expression non-terminal for #if/#elif and in both C and C++ that NT is conditional-expression, so #if 1, 2 is IMHO clearly wrong in both languages. C89 then says for constant-expression "Constant expressions shall not contain assignment, increment, decrement, function-call, or comma operators, except when they are contained within the operand of a sizeof operator." Because all the remaining identifiers in the #if/#elif expression are replaced with 0 I think assignments, increment, decrement and function-call aren't that big deal because (0 = 1) or ++4 etc. are all invalid, but for comma expressions I think it matters. In r0-56429 PR456 Joseph has added !CPP_OPTION (pfile, c99) to handle that correctly. Then C99 changed that to: "Constant expressions shall not contain assignment, increment, decrement, function-call, or comma operators, except when they are contained within a subexpression that is not evaluated." That made for C99+ #if 1 || (1, 2) etc. valid but #if (1, 2) is still invalid, ditto #if 1 ? 1, 2 : 3 In C++ I can't find anything like that though, and as can be seen on say int a[(1, 2)]; int b[1 ? 1, 2 : 3]; being accepted by C++ and rejected by C while int c[1, 2]; int d[1 ? 2 : 3, 4]; being rejected in both C and C++, so I think for C++ it is indeed just the grammar that prevents #if 1, 2. When it is the second operand of ?: or inside of () the grammar just uses expression and that allows comma operator. So, the following patch uses different decisions for C++ when to diagnose comma operator in preprocessor expressions, for C++ tracks if it is inside of () (obviously () around #embed clauses don't count unless one uses limit ((1, 2)) etc.) or inside of the second ?: operand and allows comma operator there and disallows elsewhere. BTW, I wonder if anything in the standard disallows <=> in the preprocessor expressions. Say #if (0 <=> 1) < 0 etc. #include <compare> constexpr int a = (0 <=> 1) < 0; is valid (but not valid without #include <compare>) and the expressions don't use any identifiers. 2025-07-30 Jakub Jelinek <jakub@redhat.com> PR c++/120778 * internal.h (struct lexer_state): Add comma_ok member. * expr.cc (_cpp_parse_expr): Initialize it to 0, increment on CPP_OPEN_PAREN and CPP_QUERY, decrement on CPP_CLOSE_PAREN and CPP_COLON. (num_binary_op): For C++ pedwarn on comma operator if pfile->state.comma_ok is 0 instead of !c99 or skip_eval. * g++.dg/cpp/if-comma-1.C: New test.
2025-07-30vect: Add missing skip-vector check for peeling with versioning [PR121020]Pengfei Li3-1/+59
This fixes a miscompilation issue introduced by the enablement of combined loop peeling and versioning. A test case that reproduces the issue is included in the patch. When performing loop peeling, GCC usually inserts a skip-vector check. This ensures that after peeling, there are enough remaining iterations to enter the main vectorized loop. Previously, the check was omitted if loop versioning for alignment was applied. It was safe before because versioning and peeling for alignment were mutually exclusive. However, with combined peeling and versioning enabled, this is not safe any more. A loop may be peeled and versioned at the same time. Without the skip-vector check, the main vectorized loop can be entered even if its iteration count is zero. This can cause the loop running many more iterations than needed, resulting in incorrect results. To fix this, the patch updates the condition of omitting the skip-vector check to when versioning is performed alone without peeling. gcc/ChangeLog: PR tree-optimization/121020 * tree-vect-loop-manip.cc (vect_do_peeling): Update the condition of omitting the skip-vector check. * tree-vectorizer.h (LOOP_VINFO_USE_VERSIONING_WITHOUT_PEELING): Add a helper macro. gcc/testsuite/ChangeLog: PR tree-optimization/121020 * gcc.dg/vect/vect-early-break_138-pr121020.c: New test.
2025-07-30vect: Fix insufficient alignment requirement for speculative loads [PR121190]Pengfei Li3-15/+69
This patch fixes a segmentation fault issue that can occur in vectorized loops with an early break. When GCC vectorizes such loops, it may insert a versioning check to ensure that data references (DRs) with speculative loads are aligned. The check normally requires DRs to be aligned to the vector mode size, which prevents generated vector load instructions from crossing page boundaries. However, this is not sufficient when a single scalar load is vectorized into multiple loads within the same iteration. In such cases, even if none of the vector loads crosses page boundaries, subsequent loads after the first one may still access memory beyond current valid page. Consider the following loop as an example: while (i < MAX_COMPARE) { if (*(p + i) != *(q + i)) return i; i++; } When compiled with "-O3 -march=znver2" on x86, the vectorized loop may include instructions like: vmovdqa (%rcx,%rax), %ymm0 vmovdqa 32(%rcx,%rax), %ymm1 vpcmpeqq (%rdx,%rax), %ymm0, %ymm0 vpcmpeqq 32(%rdx,%rax), %ymm1, %ymm1 Note two speculative vector loads are generated for each DR (p and q). The first vmovdqa and vpcmpeqq are safe due to the vector size (32-byte) alignment, but the following ones (at offset 32) may not be safe because they could read from the beginning of the next memory page, potentially leading to segmentation faults. To avoid the issue, this patch increases the alignment requirement for speculative loads to DR_TARGET_ALIGNMENT. It ensures all vector loads in the same vector iteration access memory within the same page. gcc/ChangeLog: PR tree-optimization/121190 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment): Increase alignment requirement for speculative loads. gcc/testsuite/ChangeLog: PR tree-optimization/121190 * gcc.dg/vect/vect-early-break_52.c: Update an unsafe test. * gcc.dg/vect/vect-early-break_137-pr121190.c: New test.
2025-07-30aarch64: Fix sme2+faminmax intrisic gating (PR 121300)Alfie Richards2-1/+11
Fixes the feature gating for the SME2+FAMINMAX intrinsics. PR target/121300 gcc/ChangeLog: * config/aarch64/aarch64-sve-builtins-sme.def (svamin/svamax): Fix arch gating. gcc/testsuite/ChangeLog: * gcc.target/aarch64/pr121300.c: New test.
2025-07-30tree-optimization/121304 - set memory_access_type before reading itRichard Biener1-43/+43
The following re-orders gather/scatter handling back to be before we check for fallback situations, specifically make sure to set memory_access_type before reading it. * tree-vect-stmts.cc (get_group_load_store_type): Process STMT_VINFO_GATHER_SCATTER before reading memory_access_type.
2025-07-30aarch64: Add support for unpacked SVE FP conditional ternary arithmeticSpencer Abson11-41/+196
This patch extends the expander for fma, fnma, fms, and fnms to support partial SVE FP modes. We add the missing BF16 tests, which we can now trigger for having implemented the conditional expander. We also add tests for the 'merging with multiplicand' case, which this expander canonicalizes (albeit under SVE_STRICT_GP). gcc/ChangeLog: * config/aarch64/aarch64-sve.md (@cond_<optab><mode>): Extend to support partial FP modes. (*cond_<optab><mode>_2_strict): Extend from SVE_FULL_F to SVE_F, use aarch64_predicate_operand. (*cond_<optab><mode>_4_strict): Extend from SVE_FULL_F_B16B16 to SVE_F_B16B16, use aarch64_predicate_operand. (*cond_<optab><mode>_any_strict): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/unpacked_cond_fmla_1.c: Add test cases for merging with multiplcand. * gcc.target/aarch64/sve/unpacked_cond_fmls_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fnmla_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fnmls_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fmla_2.c: New test. * gcc.target/aarch64/sve/unpacked_cond_fmls_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fnmla_2.c: Likewise.. * gcc.target/aarch64/sve/unpacked_cond_fnmls_2.c: Likewise. * g++.target/aarch64/sve/unpacked_cond_ternary_bf16_1.C: Likewise. * g++.target/aarch64/sve/unpacked_cond_ternary_bf16_2.C: Likewise.
2025-07-30aarch64: Relaxed SEL combiner patterns for unpacked SVE FP ternary arithmeticSpencer Abson5-19/+207
Extend the ternary op/UNSPEC_SEL combiner patterns from SVE_FULL_F/ SVE_FULL_F_BF to SVE_F/SVE_F_BF, where the strictness value is SVE_RELAXED_GP. We can only reliably test the 'merging with the third input' (addend) and 'independent value' patterns at this stage as the canocalisation that reorders the multiplicands based on the second SEL input would be performed by the conditional expander. Another difficulty is that we can't test these fused multiply/SEL combines without using __builtin_fma and friends. The reason for this is as follows: We support COND_ADD, COND_SUB, and COND_MUL optabs, so match.pd will canonicalize patterns like ADD/SUB/MUL combined with a VEC_COND_EXPR into these conditional forms. Later, when widening_mul tries to fold these into conditional fused multiply operations, the transformation fails - simply because we haven’t implemented those conditional fused multiply optabs yet. Hence why this patch lacks tests for BFloat16... gcc/ChangeLog: * config/aarch64/aarch64-sve.md (*cond_<optab><mode>_2_relaxed): Extend from SVE_FULL_F to SVE_F. (*cond_<optab><mode>_4_relaxed): Extend from SVE_FULL_F_B16B16 to SVE_F_B16B16. (*cond_<optab><mode>_any_relaxed): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/unpacked_cond_fmla_1.c: New test. * gcc.target/aarch64/sve/unpacked_cond_fmls_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fnmla_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fnmls_1.c: Likewise.
2025-07-30fortran: Remove useless elements count variableMikael Morin3-15/+9
The function gfc_array_init_size evaluates the number of array elements to a variable from a caller, but the single caller providing the variable actually doesn't use it. This change removes the variable and the function arguments passing its address down the call chain. gcc/fortran/ChangeLog: * trans-array.cc (gfc_array_init_size): Remove the nelems argument. (gfc_array_allocate): Update caller. Remove the nelems argument. * trans-stmt.cc (gfc_trans_allocate): Update caller. Remove the nelems variable. * trans-array.h (gfc_array_allocate): Update prototype.
2025-07-30fortran: implement split for fortran 2023Yuao Ma15-0/+328
This patch includes the implementation, documentation, and test case for SPLIT. gcc/fortran/ChangeLog: * check.cc (gfc_check_split): Argument check for SPLIT. * gfortran.h (enum gfc_isym_id): Define GFC_ISYM_SPLIT. * intrinsic.cc (add_subroutines): Register SPLIT intrinsic. * intrinsic.h (gfc_check_split): New decl. (gfc_resolve_split): Ditto. * intrinsic.texi: SPLIT documentation. * iresolve.cc (gfc_resolve_split): Add resolved_sym for SPLIT. * trans-decl.cc (gfc_build_intrinsic_function_decls): Add decl for SPLIT in libgfortran. * trans-intrinsic.cc (conv_intrinsic_split): SPLIT codegen. (gfc_conv_intrinsic_subroutine): Handle SPLIT case. * trans.h (GTY): Declare gfor_fndecl_string_split{, _char4}. libgfortran/ChangeLog: * gfortran.map: Add split symbol. * intrinsics/string_intrinsics_inc.c (string_split): Runtime support for SPLIT. gcc/testsuite/ChangeLog: * gfortran.dg/split_1.f90: New test. * gfortran.dg/split_2.f90: New test. * gfortran.dg/split_3.f90: New test. * gfortran.dg/split_4.f90: New test. Signed-off-by: Yuao Ma <c8ef@outlook.com>
2025-07-30aarch64: Add support for unpacked SVE FP ternary arithmeticSpencer Abson11-13/+263
This patch extends the expander for unconditional fma, fnma, fms, and fnms, so that it supports partial SVE FP modes. gcc/ChangeLog: * config/aarch64/aarch64-sve.md (<optab><mode>4): Extend from SVE_FULL_F_B16B16 to SVE_F_B16B16. Use aarch64_sve_fp_pred instead of aarch64_ptrue_reg. (@aarch64_pred_<optab><mode>): Extend from SVE_FULL_F_B16B16 to SVE_F_B16B16. Use aarch64_predicate_operand. gcc/testsuite/ChangeLog: * g++.target/aarch64/sve/unpacked_ternary_bf16_1.C: New test. * g++.target/aarch64/sve/unpacked_ternary_bf16_2.C: Likewise. * gcc.target/aarch64/sve/unpacked_fmla_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_fmla_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_fmls_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_fmls_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_fnmla_1.c: Likeiwse. * gcc.target/aarch64/sve/unpacked_fnmla_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_fnmls_1.c: Likewise. * gcc.target/aarch64/sve/unpacked_fnmls_2.c: Likewise.
2025-07-30Remove V64SFmode and V64SImode.liuhongt2-4/+1
It's needed by avx5124vnniw/avx5124fmaps which have been removed by r15-656-ge1a7e2c54d52d0. gcc/ChangeLog: * config/i386/i386-modes.def: Remove VECTOR_MODES(FLOAT, 256) and VECTOR_MODE (INT, SI, 64). * config/i386/i386.cc (ix86_hard_regno_nregs): Remove related code for V64SF/V64SImode.
2025-07-30Eliminate redundant vpextrq/vpinsrq when move TI to V4SI.liuhongt2-0/+37
r14-1902-g96c3539f2a3813 split TImode move with 2 DImode move, it's supposed to optimize TImode in parameter/return since accoring to psABI it's stored into 2 general registers. But when TImode is not in parameter/return, it could create redundancy in the PR. The patch add a splitter to handle that. .i.e. (insn 10 9 14 2 (set (subreg:V2DI (reg:V4SI 98 [ <retval> ]) 0) (vec_concat:V2DI (subreg:DI (reg:TI 101) 0) (subreg:DI (reg:TI 101) 8))) 8442 {vec_concatv2di} (expr_list:REG_DEAD (reg:TI 101) gcc/ChangeLog: PR target/121274 * config/i386/sse.md (*vec_concatv2di_0): Add a splitter before it. gcc/testsuite/ChangeLog: * gcc.target/i386/pr121274.c: New test.
2025-07-30RISC-V: Add testcases for unsigned avg ceil vx combine.Pan Li20-3/+303
The unsigned avg ceil share the vaaddux.vx for the vx combine, so add the test case to make sure it works well as expected. The below test suites are passed for this patch series. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Add asm check for unsigned avg ceil. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test data. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2025-07-30Daily bump.GCC Administrator5-1/+283
2025-07-29simplify-rtx: Fix Distribute subregs over logic ops [PR121302]Andrew Pinski1-4/+4
r16-2614-g965564eafb721f had a typo where it would assume byte==0 rather than use the byte (offset) that was passed. This fixes that typo and also fixes the comment since it is not just about lowerpart subregs but all non-paradoxical subregs. Pushed as obvious after bootstrap/test on x86_64-linux-gnu. PR rtl-optimization/121302 gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_subreg): Use byte instead of 0 when calling simplify_subreg. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2025-07-29testsuite: Cleanup after auto-profile testcases when auto-profile is not ↵Andrew Pinski1-0/+2
supported [PR121215] The problem here is that in tree-prof.exp does not cleanup if requiring auto-profile but it is not supported and the testcase uses dg-additional-sources. Currently additional_sources is not reset to "" and then another testcase comes along and thinks that is the additional source to be added. Committed as obvious after testing: make check-gcc RUNTESTFLAGS="tree-prof.exp=afdo-crossmodule-1.c tree-ssa.exp=pr67891.c" to make sure pr67891.c now no longer uses the additional source. PR testsuite/121215 gcc/testsuite/ChangeLog: * lib/profopt.exp (profopt-execute): Call cleanup-after-saved-dg-test if returning early for the -fauto-profile case failing case. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2025-07-29aarch64: Add support for unpacked SVE FP conditional binary arithmeticSpencer Abson12-73/+319
This patch extends the expander for conditional smax, smin, add, sub, mul, min, max, and div to support partial SVE FP modes. If exceptions from undefined vector elements must be suppressed, this expansion converts the container-level predicate to an element-level one, and ensures that these elements are inactive for the operation. In practice, this is a predicate AND with the existing mask and a container-size PTRUE. gcc/ChangeLog: * config/aarch64/aarch64-protos.h (aarch64_sve_emit_masked_fp_pred): Declare. * config/aarch64/aarch64-sve.md (and<mode>3): Change this to... (@and<mode>3): ...this, so that we can use gen_and3. (@cond_<optab><mode>): Extend from SVE_FULL_F_B16B16 to SVE_F_B16B16, use aarch64_predicate_operand. (*cond_<optab><mode>_2_strict): Likewise. (*cond_<optab><mode>_3_strict): Likewise. (*cond_<optab><mode>_any_strict): Likwise. (*cond_<optab><mode>_2_const_strict): Extend from SVE_FULL_F to SVE_F, use aarch64_predicate_operand. (*cond_<optab><mode>_any_const_strict): Likewise. (*cond_sub<mode>_3_const_strict): Likwise. (*cond_sub<mode>_const_strict): Likewise. (*vcond_mask_<mode><vpred>): Use aarch64_predicate_operand, and update the comment here. * config/aarch64/aarch64.cc (aarch64_sve_emit_masked_fp_pred): New function. Helper to mask the predicate in conditional expanders. gcc/testsuite/ChangeLog: * g++.target/aarch64/sve/unpacked_cond_binary_bf16_2.C: New test. * gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fadd_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fdiv_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fmaxnm_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fminnm_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fmul_2.c: Likewise. * gcc.target/aarch64/sve/unpacked_cond_fsubr_2.c: Likewise.
2025-07-29x86: Pass -mno-80387 to compile pr121208-1(a|b).cH.J. Lu2-2/+2
Pass -mno-80387 to compile pr121208-1(a|b).c to silence .../pr121208-1a.c:11:1: sorry, unimplemented: 80387 instructions aren’t allowed in a function with the ‘no_caller_saved_registers’ attribute PR target/121208 * gcc.target/i386/pr121208-1a.c (dg-options): Add -mno-80387. * gcc.target/i386/pr121208-1b.c (dg-options): Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-07-29testsuite: Adjust s390x params for vector tests.Juergen Christ2-0/+2
Loop peeling and minimal loop vectorization threshold prevented loop vectorization in these examples. Adjust parameters in the test to make the test pass. Signed-off-by: Juergen Christ <jchrist@linux.ibm.com> PR testsuite/121286 PR testsuite/121288 gcc/testsuite/ChangeLog: * gcc.dg/vect/pr112325.c: Adjust parameters for s390. * gcc.dg/vect/pr117888-1.c: Ditto.
2025-07-29RISC-V: Generate -mcpu and -mtune options from riscv-cores.def.Dongyan Chen7-23/+251
Automatically generate -mcpu and -mtune options in invoke.texi from the unified riscv-cores.def metadata, ensuring documentation stays in sync with definitions and reducing manual maintenance. gcc/ChangeLog: * Makefile.in: Add riscv-mcpu.texi and riscv-mtune.texi to the list of files to be processed by the Texinfo generator. * config/riscv/t-riscv: Add rule for generating riscv-mcpu.texi and riscv-mtune.texi. * doc/invoke.texi: Replace hand‑written extension table with `@include riscv-mcpu.texi` and `@include riscv-mtune.texi` to pull in auto‑generated entries. * config/riscv/gen-riscv-mcpu-texi.cc: New file. * config/riscv/gen-riscv-mtune-texi.cc: New file. * doc/riscv-mcpu.texi: New file. * doc/riscv-mtune.texi: New file.
generated by cgit v1.1 at 2025-09-24 02:09:27 +0000