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Provide a GORI API which can produce a range vector for all outgoing
ranges on an edge without any of the other infratructure.
* gimple-range-gori.cc (gori_stmt_info::gori_stmt_info): New.
(gori_calc_operands): New.
(gori_on_edge): New.
(gori_name_helper): New.
(gori_name_on_edge): New.
* gimple-range-gori.h (gori_on_edge): New prototype.
(gori_name_on_edge): New prototype.
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r14-3459-g0c78240fd7d519 "Check that passes do not forget to define profile"
exposed check failures in cases when gcc produces uninitialized profile
probabilities. In case of PR/111559 uninitialized profile is generated
by edges executed 0 times reported by IPA profile:
$ gcc -O2 -fprofile-generate pr111559.c -o b -fopt-info
$ ./b
$ gcc -O2 -fprofile-use -fprofile-correction pr111559.c -o b -fopt-info
pr111559.c: In function 'rule1':
pr111559.c:6:13: error: probability of edge 3->4 not initialized
6 | static void rule1(void) { if (p) edge(); }
| ^~~~~
during GIMPLE pass: fixup_cfg
pr111559.c:6:13: internal compiler error: verify_flow_info failed
The change conservatively ignores updates with zero execution counts and
uses initially assigned probabilities (`always` probability in case of
the example).
PR ipa/111283
PR gcov-profile/111559
gcc/
* ipa-utils.cc (ipa_merge_profiles): Avoid producing
uninitialized probabilities when merging counters with zero
denominators.
gcc/testsuite/
* gcc.dg/tree-prof/pr111559.c: New test.
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86% of the document have 4 spaces; adjust the remaining 14%.
Signed-off-by: Jan Engelhardt <jengelh@inai.de>
ChangeLog:
* SECURITY.txt: Fix up indentation.
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Signed-off-by: Jan Engelhardt <jengelh@inai.de>
ChangeLog:
* SECURITY.txt: Fix up commas.
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The stringop strategy selection algorithm falls back to a libcall strategy
when it exhausts its pool of available strategies. The memory area copy
function (memcpy) is not availabe from the system library for non-default
address spaces, so the compiler emits the most trivial byte-at-a-time
copy loop instead.
The compiler should instead emit an optimized copy loop as a fallback for
non-default address spaces.
PR target/111657
gcc/ChangeLog:
* config/i386/i386-expand.cc (alg_usable_p): Reject libcall
strategy for non-default address spaces.
(decide_alg): Use loop strategy as a fallback strategy for
non-default address spaces.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr111657.c: New test.
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Hello all,
this patch checks in mdcompact, the tool written in elisp that I used
to mass convert all the multi choice pattern in the aarch64 back-end to
the new compact syntax.
I tested it on Emacs 29 (might run on older versions as well not
sure), also I verified it runs cleanly on a few other back-ends (arm,
loongarch).
The tool can be used to convert a single pattern, an open buffer or
all md files in a directory.
The tool might need further adjustment to run on some specific
back-end, in case very happy to help.
This patch was pre-approved here [1].
Best Regards
Andrea Corallo
[1] <https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631830.html>
contrib/ChangeLog
* mdcompact/mdcompact-testsuite.el: New file.
* mdcompact/mdcompact.el: Likewise.
* mdcompact/tests/1.md: Likewise.
* mdcompact/tests/1.md.out: Likewise.
* mdcompact/tests/2.md: Likewise.
* mdcompact/tests/2.md.out: Likewise.
* mdcompact/tests/3.md: Likewise.
* mdcompact/tests/3.md.out: Likewise.
* mdcompact/tests/4.md: Likewise.
* mdcompact/tests/4.md.out: Likewise.
* mdcompact/tests/5.md: Likewise.
* mdcompact/tests/5.md.out: Likewise.
* mdcompact/tests/6.md: Likewise.
* mdcompact/tests/6.md.out: Likewise.
* mdcompact/tests/7.md: Likewise.
* mdcompact/tests/7.md.out: Likewise.
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libgcc/config/avr/libf7/
* libf7.h (F7_PURE): Remove all occurrences.
* libf7.c: Same.
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libgcc/config/avr/libf7/
* libf7.h (F7_FLAGNO_plusx, F7_FLAG_plusx): New macros.
* libf7.c (f7_horner): Handle F7_FLAG_plusx in highest coefficient.
* libf7-const.def [F7MOD_atan_]: Denominator: Set F7_FLAG_plusx
and omit highest term.
[F7MOD_asinacos_]: Use rational function with normalized denominator.
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My earlier version of the ipa_bits removal patch resulted in self-test
failures in sreal. When debugging it, I was really confused that I couldn't
find verify_arithmetics function in the source. Turns out it had bad
spelling...
2023-10-05 Jakub Jelinek <jakub@redhat.com>
* sreal.cc (verify_aritmetics): Rename to ...
(verify_arithmetics): ... this.
(sreal_verify_arithmetics): Adjust caller.
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This reverts commit 1be18ea110a2d69570dbc494588a7c73173883be.
As reported in PR bootstrap/111688, it broke ppc64le bootstrap because
of a debug-compare failure.
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gcc/ChangeLog:
* config/riscv/autovec.md (@vec_series<mode>): Remove @.
(vec_series<mode>): Ditto.
* config/riscv/riscv-v.cc (expand_const_vector): Ditto.
(shuffle_decompress_patterns): Ditto.
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gcc/testsuite:
* gcc.target/arc/enter-dw2-1.c: Remove tests when using linux
build.
* gcc.target/arc/tls-ld.c: Update test.
* gcc.target/arc/tls-le.c: Likewise.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Remove old ccfsm responsible for conditional execution support in ARC.
This machinery is not needed as the current gcc conditional execution
support is mature.
gcc/
* config/arc/arc-passes.def: Remove arc_ifcvt pass.
* config/arc/arc-protos.h (arc_ccfsm_branch_deleted_p): Remove.
(arc_ccfsm_record_branch_deleted): Likewise.
(arc_ccfsm_cond_exec_p): Likewise.
(arc_ccfsm): Likewise.
(arc_ccfsm_record_condition): Likewise.
(make_pass_arc_ifcvt): Likewise.
* config/arc/arc.cc (arc_ccfsm): Remove.
(arc_ccfsm_current): Likewise.
(ARC_CCFSM_BRANCH_DELETED_P): Likewise.
(ARC_CCFSM_RECORD_BRANCH_DELETED): Likewise.
(ARC_CCFSM_COND_EXEC_P): Likewise.
(CCFSM_ISCOMPACT): Likewise.
(CCFSM_DBR_ISCOMPACT): Likewise.
(machine_function): Remove ccfsm related fields.
(arc_ifcvt): Remove pass.
(arc_print_operand): Remove `#` punct operand and other ccfsm
related code.
(arc_ccfsm_advance): Remove.
(arc_ccfsm_at_label): Likewise.
(arc_ccfsm_record_condition): Likewise.
(arc_ccfsm_post_advance): Likewise.
(arc_ccfsm_branch_deleted_p): Likewise.
(arc_ccfsm_record_branch_deleted): Likewise.
(arc_ccfsm_cond_exec_p): Likewise.
(arc_get_ccfsm_cond): Likewise.
(arc_final_prescan_insn): Remove ccfsm references.
(arc_internal_label): Likewise.
(arc_reorg): Likewise.
(arc_output_libcall): Likewise.
* config/arc/arc.md: Remove ccfsm references and update related
instruction patterns.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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The '^' was used to print '@' character in the ouput assembly. This is
not anylonger required by the ARC binutils. Remove it.
gcc/
* config/arc/arc.cc (arc_init): Remove '^' punct char.
(arc_print_operand): Remove related code.
* config/arc/arc.md: Update patterns which uses '%&'.
gcc/testsuite/
* gcc.target/arc/loop-3.c: Update test.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Update tests and remove old mtune-* tests.
gcc/testsuite
* gcc.target/arc/add_n-combine.c: Recognize add2 instruction.
* gcc.target/arc/firq-4.c: FP register is a temp reg. Update test.
* gcc.target/arc/firq-6.c: Likewise.
* gcc.target/arc/mtune-ARC600.c: Remove test.
* gcc.target/arc/mtune-ARC601.c: Likewise.
* gcc.target/arc/mtune-ARC700-xmac: Likewise.
* gcc.target/arc/mtune-ARC700.c: Likewise.
* gcc.target/arc/mtune-ARC725D.c: Likewise.
* gcc.target/arc/mtune-ARC750D.c: Likewise.
* gcc.target/arc/uncached-7.c: Set it to XFAIL.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Removes '&' print operant punct character, disable -mannotate-align
option and clean up the port.
gcc/
* config/arc/arc-protos.h (arc_clear_unalign): Remove.
(arc_toggle_unalign): Likewise.
* config/arc/arc.cc (machine_function) Remove unalign.
(arc_init): Remove `&` punct character.
(arc_print_operand): Remove `&` related functions.
(arc_verify_short): Update function's number of parameters.
(output_short_suffix): Update function.
(arc_short_long): Likewise.
(arc_clear_unalign): Remove.
(arc_toggle_unalign): Likewise.
* config/arc/arc.h (ASM_OUTPUT_CASE_END): Remove.
(ASM_OUTPUT_ALIGN): Update.
* config/arc/arc.md: Remove all `%&` references.
* config/arc/arc.opt (mannotate-align): Ignore option.
* doc/invoke.texi (mannotate-align): Update description.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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When we do SLP discovery of SIMD calls we run into the issue that
when the call is neither builtin nor internal function we have
cfn == CFN_LAST but internal_fn_p of that returns true. Since
IFN_LAST isn't vectorizable we fail spuriously.
Fixed by checking for cfn != CFN_LAST && internal_fn_p (cfn)
instead.
* tree-vect-slp.cc (vect_build_slp_tree_1): Do not
ask for internal_fn_p (CFN_LAST).
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The following makes sure to treat values whose definition we didn't
visit as available since those by definition must dominate the entry
of the region. That avoids unpropagated copies after if-conversion
and resulting SLP discovery fails (which doesn't handle plain copies).
* tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Not
visited value numbers are available itself.
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The following clarifies the flatten attribute documentation to mention
the inlining applies also to calls formed as part of inlining earlier
calls but not calls to the function itself.
PR ipa/111643
* doc/extend.texi (attribute flatten): Clarify.
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Define a security process and exclusions to security issues for GCC and
all components it ships.
Signed-off-by: Siddhesh Poyarekar <siddhesh@gotplt.org>
ChangeLog:
* SECURITY.txt: New file.
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flake8 points out that the new call to _string_types from
StdExpAnyPrinter.__init__ is not correct -- it needs to be qualified.
libstdc++-v3/ChangeLog:
* python/libstdcxx/v6/printers.py
(StdExpAnyPrinter.__init__): Qualify call to
_string_types.
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This patch splits SImode shifts, for !TARGET_BARREL_SHIFTER targets,
after combine and before reload, in the split1 pass, as suggested by
the FIXME comment above output_shift in arc.cc. To do this I've
copied the implementation of the x86_pre_reload_split function from
the i386 backend, and renamed it arc_pre_reload_split.
Although the actual implementations of shifts remain the same
(as in output_shift), having them as explicit instructions in
the RTL stream allows better scheduling and use of compact forms
when available. The benefits can be seen in two short examples
below.
For the function:
unsigned int foo(unsigned int x, unsigned int y) {
return y << 2;
}
GCC with -O2 -mcpu=em would previously generate:
foo: add r1,r1,r1
add r1,r1,r1
j_s.d [blink]
mov_s r0,r1 ;4
and with this patch now generates:
foo: asl_s r0,r1
j_s.d [blink]
asl_s r0,r0
Notice the original (from shift_si3's output_shift) requires the
shift sequence to be monolithic with the same destination register
as the source (requiring an extra mov_s). The new version can
eliminate this move, and schedule the second asl in the branch
delay slot of the return.
For the function:
int x,y,z;
void bar()
{
x <<= 3;
y <<= 3;
z <<= 3;
}
GCC -O2 -mcpu=em currently generates:
bar: push_s r13
ld.as r12,[gp,@x@sda] ;23
ld.as r3,[gp,@y@sda] ;23
mov r2,0
add3 r12,r2,r12
mov r2,0
add3 r3,r2,r3
ld.as r2,[gp,@z@sda] ;23
st.as r12,[gp,@x@sda] ;26
mov r13,0
add3 r2,r13,r2
st.as r3,[gp,@y@sda] ;26
st.as r2,[gp,@z@sda] ;26
j_s.d [blink]
pop_s r13
where each shift by 3, uses ARC's add3 instruction, which is similar
to x86's lea implementing x = (y<<3) + z, but requires the value zero
to be placed in a temporary register "z". Splitting this before reload
allows these pseudos to be shared/reused. With this patch, we get
bar: ld.as r2,[gp,@x@sda] ;23
mov_s r3,0 ;3
add3 r2,r3,r2
ld.as r3,[gp,@y@sda] ;23
st.as r2,[gp,@x@sda] ;26
ld.as r2,[gp,@z@sda] ;23
mov_s r12,0 ;3
add3 r3,r12,r3
add3 r2,r12,r2
st.as r3,[gp,@y@sda] ;26
st.as r2,[gp,@z@sda] ;26
j_s [blink]
Unfortunately, register allocation means that we only share two of the
three "mov_s z,0", but this is sufficient to reduce register pressure
enough to avoid spilling r13 in the prologue/epilogue.
2023-10-04 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/arc/arc-protos.h (emit_shift): Delete prototype.
(arc_pre_reload_split): New function prototype.
* config/arc/arc.cc (emit_shift): Delete function.
(arc_pre_reload_split): New predicate function, copied from i386,
to schedule define_insn_and_split splitters to the split1 pass.
* config/arc/arc.md (ashlsi3): Expand RTL template unconditionally.
(ashrsi3): Likewise.
(lshrsi3): Likewise.
(shift_si3): Move after other shift patterns, and disable when
operands[2] is one (which is handled by its own define_insn).
Use shiftr4_operator, instead of shift4_operator, as this is no
longer used for left shifts.
(shift_si3_loop): Likewise. Additionally remove match_scratch.
(*ashlsi3_nobs): New pre-reload define_insn_and_split.
(*ashrsi3_nobs): Likewise.
(*lshrsi3_nobs): Likewise.
(rotrsi3_cnt1): Rename define_insn from *rotrsi3_cnt1.
(add_shift): Rename define_insn from *add_shift.
* config/arc/predicates.md (shiftl4_operator): Delete.
(shift4_operator): Delete.
gcc/testsuite/ChangeLog
* gcc.target/arc/ashrsi-1.c: New TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/ashrsi-2.c: New !TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/ashrsi-3.c: Likewise.
* gcc.target/arc/ashrsi-4.c: Likewise.
* gcc.target/arc/ashrsi-5.c: Likewise.
* gcc.target/arc/lshrsi-1.c: New TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/lshrsi-2.c: New !TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/lshrsi-3.c: Likewise.
* gcc.target/arc/lshrsi-4.c: Likewise.
* gcc.target/arc/lshrsi-5.c: Likewise.
* gcc.target/arc/shlsi-1.c: New TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/shlsi-2.c: New !TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/shlsi-3.c: Likewise.
* gcc.target/arc/shlsi-4.c: Likewise.
* gcc.target/arc/shlsi-5.c: Likewise.
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This patch changes/corrects the "type" insn attribute on the SImode shift
by one bit instructions in arc.md: {ashl,lshr,ashr}si2_cnt1. These insns
can use a compact representation, but the default method to determine the
"length" attribute of ARC instruction assumes that instructions of type
"shift" have two input operands, and therefore accesses operands[2].
For the shift by constant templates, a type attribute of "unary" is more
appropriate (when an explicit length isn't specified) to avoid an ICE.
2023-10-04 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/arc/arc.md (ashlsi3_cnt1): Rename define_insn *ashlsi2_cnt1.
Change type attribute to "unary", as this doesn't have operands[2].
Change length attribute to "*,4" to allow compact representation.
(lshrsi3_cnt1): Rename define_insn from *lshrsi3_cnt1. Change
insn type attribute to "unary", as this doesn't have operands[2].
(ashrsi3_cnt1): Rename define_insn from *ashrsi3_cnt1. Change
insn type attribute to "unary", as this doesn't have operands[2].
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This patch is my proposed fix to PR rtl-optimization 110701, a latent bug
in combine's record_dead_and_set_regs_1 exposed by recent improvements to
simplify_subreg.
The issue involves the handling of (normal) SUBREG SET_DESTs as in the
instruction:
(set (subreg:HI (reg:SI x) 0) (expr:HI y))
The semantics of this are that the bits specified by the SUBREG are set
to the SET_SRC, y, and that the other bits of the SET_DEST are left/become
undefined. To simplify explanation, we'll only consider lowpart SUBREGs
(though in theory non-lowpart SUBREGS could be handled), and the fact that
bits outside of the lowpart WORD retain their original values (treating
these as undefined is a missed optimization rather than incorrect code
bug, that only affects targets with less than 64-bit words).
The bug is that combine simulates the behaviour of the above instruction,
for calculating nonzero_bits and set_sign_bit_copies, in the function
record_value_for_reg, by using the equivalent of:
(set (reg:SI x) (subreg:SI (expr:HI y))
by calling gen_lowpart on the SET_SRC. Alas, the semantics of this
revised instruction aren't always equivalent to the original.
In the test case for PR110701, the original instruction
(set (subreg:HI (reg:SI x), 0)
(and:HI (subreg:HI (reg:SI y) 0)
(const_int 340)))
which (by definition) leaves the top bits of x undefined, is mistakenly
considered to be equivalent to
(set (reg:SI x) (and:SI (reg:SI y) (const_int 340)))
where gen_lowpart's freedom to do anything with paradoxical SUBREG bits,
has now cleared the high bits. The same bug also triggers when the
SET_SRC is say (subreg:HI (reg:DI z)), where gen_lowpart transforms
this into (subreg:SI (reg:DI z)) which defines bits 16-31 to be the
same as bits 16-31 of z.
The fix is that after calling record_value_for_reg, we need to mark
the bits that should be undefined as undefined, in case gen_lowpart,
which performs transforms appropriate for r-values, has changed the
interpretation of the SUBREG when used as an l-value.
2023-10-04 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR rtl-optimization/110701
* combine.cc (record_dead_and_set_regs_1): Split comment into
pieces placed before the relevant clauses. When the SET_DEST
is a partial_subreg_p, mark the bits outside of the updated
portion of the destination as undefined.
gcc/testsuite/ChangeLog
PR rtl-optimization/110701
* gcc.target/i386/pr110701.c: New test case.
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Some code in the pretty-printers seems to assume that the
_versioned_namespace global might be None (or the empty string).
However, doesn't occur, as the variable is never reassigned.
libstdc++-v3/ChangeLog:
* python/libstdcxx/v6/printers.py: Assume that
_versioned_namespace is non-None.
* python/libstdcxx/v6/xmethods.py (is_specialization_of):
Assume that _versioned_namespace is non-None.
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flake8 pointed out that is_specialization_of in xmethods.py looks at a
global that wasn't added to the file. This patch correct the
oversight.
libstdc++-v3/ChangeLog:
* python/libstdcxx/v6/xmethods.py (_versioned_namespace):
Define.
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Multidimensional arrary is gawk extension, and we accidentally
introduced that in recent commit[1].
[1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=e4a4b8e983bac865eb435b11798e38d633b98942
gcc/ChangeLog:
PR bootstrap/111664
* opt-read.awk: Drop multidimensional arrays.
* opth-gen.awk: Ditto.
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libgomp/ChangeLog:
* libgomp.texi (OpenMP Context Selectors): Clarify 'kind' trait
and that other target archs have no 'arch'/'isa' traits implemented.
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When I added copysign support for LoongArch (r13-3702), we did not have
a copysign RTL insn, so I had to use UNSPEC to represent the copysign
instruction. Now the copysign RTX code has been added in r14-1586, so
this patch removes those UNSPECs, and it uses the native RTL copysign
insn.
Inspired by rs6000 patch "Cleanup: Replace UNSPEC_COPYSIGN with copysign
RTL" [1] from Michael Meissner.
[1]: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631701.html
gcc/ChangeLog:
* config/loongarch/loongarch.md (UNSPEC_FCOPYSIGN): Delete.
(copysign<mode>3): Use copysign RTL instead of UNSPEC.
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In the light of the PR111668 patch which shows that
build_nonstandard_integer_type is needed (at least for some signed prec > 1
BOOLEAN_TYPEs if we use e.g. negation), I've reworked this patch and handled
the last problematic build_nonstandard_integer_type call in there as well.
In the x == cstN ? cst4 : cst3 optimization it uses
build_nonstandard_integer_type solely for BOOLEAN_TYPEs (I really don't see
why ENUMERAL_TYPEs would be a problem, we treat them in GIMPLE as uselessly
convertible to same precision/sign INTEGER_TYPEs), for INTEGER_TYPEs it is
really a no-op (might return a different type, but always INTEGER_TYPE
with same TYPE_PRECISION same TYPE_UNSIGNED) and for BITINT_TYPE with larger
precisions really harmful (we shouldn't create large precision
INTEGER_TYPEs).
The a?~t:t optimization just omits the negation of a in type for 1-bit
precision types or any BOOLEAN_TYPEs. I think that is correct, because
for both signed and unsigned 1-bit precision type, cast to type of a bool
value yields already 0, -1 or 0, 1 values and for 1-bit precision negation
of that is still 0, -1 or 0, 1 (except for invoking sometimes UB).
And for signed larger precision BOOLEAN_TYPEs I think it is correct as well,
cast of [0, 1] to type yields 0, -1 and those can be xored with 0 or -1
to yield the proper result, any other values would be UB.
This fixes PR111369, where one of the bitint*.c tests FAILs with
GCC_TEST_RUN_EXPENSIVE=1.
2023-10-04 Jakub Jelinek <jakub@redhat.com>
PR middle-end/111369
* match.pd (x == cstN ? cst4 : cst3): Use
build_nonstandard_integer_type only if type1 is BOOLEAN_TYPE.
Fix comment typo. Formatting fix.
(a?~t:t -> (-(a))^t): Always convert to type rather
than using build_nonstandard_integer_type. Perform negation
only if type has precision > 1 and is not signed BOOLEAN_TYPE.
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My relatively recent changes to these simplifiers to avoid
doing build_nonstandard_integer_type (primarily for BITINT_TYPE)
broke PR111668, a recurrence of the PR110487 bug.
I thought the build_nonstandard_integer_type isn't ever needed there,
but there is one special case where it is.
For the a ? -1 : 0 and a ? 0 : -1 simplifications there are actually
3 different cases. One is for signed 1-bit precision types (signed
kind of implied from integer_all_onesp, because otherwise it would
match integer_onep earlier), where the simplifier wierdly was matching
them using the a ? powerof2cst : 0 -> a << (log2(powerof2cst))
simplification and then another simplifier optimizing away the left shift
when log2(powerof2cst) was 0. Another one is signed BOOLEAN_TYPE with
precision > 1, where indeed we shouldn't be doing the negation in type,
because it isn't well defined in that type, the type only has 2 valid
values, 0 and -1. As an alternative, we could also e.g. cast to
signed 1-bit precision BOOLEAN_TYPE and then extend to type.
And the last case is what we were doing for types which have both 1 and -1
(all all ones) as valid values (i.e. all signed/unsigned ENUMERAL_TYPEs,
INTEGRAL_TYPEs and BITINT_TYPEs with precision > 1).
The following patch avoids the hops through << 0 for 1-bit precision
and uses build_nonstandard_integer_type solely for the BOOLEAN_TYPE types
(where we have a guarantee the precision is reasonably small, nothing ought
to be created 129+ bit precision BOOLEAN_TYPEs).
2023-10-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/111668
* match.pd (a ? CST1 : CST2): Handle the a ? -1 : 0 and
a ? 0 : -1 cases before the powerof2cst cases and differentiate
between 1-bit precision types, larger precision boolean types
and other integral types. Fix comment pastos and formatting.
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2023-10-04 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/37336
PR fortran/111674
* trans-expr.cc (gfc_trans_scalar_assign): Finalize components
on deallocation if derived type is not finalizable.
gcc/testsuite/
PR fortran/37336
PR fortran/111674
* gfortran.dg/allocate_with_source_25.f90: Final count in tree
dump reverts from 4 to original 6.
* gfortran.dg/finalize_38.f90: Add test for fix of PR111674.
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As mentioned in my Cauldron talk, this patch adds a call to
diagnostic_show_locus to the "required from here" messages
in print_instantiation_partial_context_line, so that e.g., rather
than the rather mystifying:
In file included from ../x86_64-pc-linux-gnu/libstdc++-v3/include/memory:78,
from ../../src/demo-1.C:1:
../x86_64-pc-linux-gnu/libstdc++-v3/include/bits/unique_ptr.h: In instantiation of ‘std::__detail::__unique_ptr_t<_Tp> std::make_unique(_Args&& ...) [with _Tp = bar; _Args = {}; __detail::__unique_ptr_t<_Tp> = __detail::__unique_ptr_t<bar>]’:
../../src/demo-1.C:15:32: required from here
../x86_64-pc-linux-gnu/libstdc++-v3/include/bits/unique_ptr.h:1066:30: error: no matching function for call to ‘bar::bar()’
1066 | { return unique_ptr<_Tp>(new _Tp(std::forward<_Args>(__args)...)); }
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/demo-1.C:10:3: note: candidate: ‘bar::bar(int)’
10 | bar (int);
| ^~~
../../src/demo-1.C:10:3: note: candidate expects 1 argument, 0 provided
../../src/demo-1.C:7:7: note: candidate: ‘constexpr bar::bar(const bar&)’
7 | class bar : public foo
| ^~~
../../src/demo-1.C:7:7: note: candidate expects 1 argument, 0 provided
../../src/demo-1.C:7:7: note: candidate: ‘constexpr bar::bar(bar&&)’
../../src/demo-1.C:7:7: note: candidate expects 1 argument, 0 provided
we emit:
In file included from ../x86_64-pc-linux-gnu/libstdc++-v3/include/memory:78,
from ../../src/demo-1.C:1:
../x86_64-pc-linux-gnu/libstdc++-v3/include/bits/unique_ptr.h: In instantiation of ‘std::__detail::__unique_ptr_t<_Tp> std::make_unique(_Args&& ...) [with _Tp = bar; _Args = {}; __detail::__unique_ptr_t<_Tp> = __detail::__unique_ptr_t<bar>]’:
../../src/demo-1.C:15:32: required from here
15 | return std::make_unique<bar> ();
| ~~~~~~~~~~~~~~~~~~~~~~^~
../x86_64-pc-linux-gnu/libstdc++-v3/include/bits/unique_ptr.h:1066:30: error: no matching function for call to ‘bar::bar()’
1066 | { return unique_ptr<_Tp>(new _Tp(std::forward<_Args>(__args)...)); }
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/demo-1.C:10:3: note: candidate: ‘bar::bar(int)’
10 | bar (int);
| ^~~
../../src/demo-1.C:10:3: note: candidate expects 1 argument, 0 provided
../../src/demo-1.C:7:7: note: candidate: ‘constexpr bar::bar(const bar&)’
7 | class bar : public foo
| ^~~
../../src/demo-1.C:7:7: note: candidate expects 1 argument, 0 provided
../../src/demo-1.C:7:7: note: candidate: ‘constexpr bar::bar(bar&&)’
../../src/demo-1.C:7:7: note: candidate expects 1 argument, 0 provided
which shows the code that's leading to the error (the bad call to
std::make_unique).
gcc/cp/ChangeLog:
* error.cc (print_instantiation_partial_context_line): Call
diagnostic_show_locus.
gcc/testsuite/ChangeLog:
* g++.dg/diagnostic/static_assert3.C: Add directives for
additional source printing.
* g++.dg/template/error60.C: New test.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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Some characters are escaped which causes the testcase to fail. This
patch restores the original characters.
Tested for regressions using multilib rv32gcv-ilp32d, rv64gcv-lp64d.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/fortran/pr111566.f90: Restore escaped
characters.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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Pointers only track null and nonnull, so we need to handle them
specially.
* tree-ssanames.cc (set_range_info): Use get_ptr_info for
pointers rather than range_info_get_range.
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The testing infrastructure built by Martin Liška contains checking a
few python scripts in contrib witha tool flake8. That tool recently
complains that:
contrib/mklog.py:360:45: E711 comparison to None should be 'if cond is None:'
contrib/mklog.py:362:1: E305 expected 2 blank lines after class or function definition, found 1
I'd like to silence these with the following, hopefully trivial,
changes. However, I have only tested the changes by running flake8
again and running ./contrib/mklog.py --help.
Is this good for trunk? (Or should I stop using flake8 instead?)
Thanks,
Martin
contrib/ChangeLog:
2023-10-03 Martin Jambor <mjambor@suse.cz>
* mklog.py (skip_line_in_changelog): Compare to None using is instead
of ==, add an extra newline after the function.
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Function dump_lto_records ought to dump to its parameter OUT but was
dumping expressions to dump_file. This is corrected by this patch and
while at at, I also made the modref_summary::dump member function
const so that it is callable from more contexts.
gcc/ChangeLog:
2023-09-21 Martin Jambor <mjambor@suse.cz>
* ipa-modref.h (modref_summary::dump): Make const.
* ipa-modref.cc (modref_summary::dump): Likewise.
(dump_lto_records): Dump to out instead of dump_file.
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Testing on 32bit arm revealed that even the simplest case of PR 110378
was still not resolved there because destructors were rturning this
pointer. Needless to say, the return value of those destructors often
is just not used, which IPA-SRA can already detect in time. Since
such enhancement seems generally useful, here it is.
The patch simply adds two flag to respective summaries to mark down
situations when it encounters either a simple direct use of a defaut
definition SSA_NAME of a paramter, which means that the parameter may
still be split when rturn value is removed, and when any derived use
of it is returned, allowing for complete removal in that case, instead
of discarding it as a candidate for removal or splitting like we do
now. The IPA phase then simply checks that we indeed plan to remove
the return value before allowing any transformation to be considered
in such cases.
gcc/ChangeLog:
2023-08-18 Martin Jambor <mjambor@suse.cz>
PR ipa/110378
* ipa-param-manipulation.cc
(ipa_param_body_adjustments::mark_dead_statements): Verify that any
return uses of PARAM will be removed.
(ipa_param_body_adjustments::mark_clobbers_dead): Likewise.
* ipa-sra.cc (isra_param_desc): New fields
remove_only_when_retval_removed and split_only_when_retval_removed.
(struct gensum_param_desc): Likewise. Fix comment long line.
(ipa_sra_function_summaries::duplicate): Copy the new flags.
(dump_gensum_param_descriptor): Dump the new flags.
(dump_isra_param_descriptor): Likewise.
(isra_track_scalar_value_uses): New parameter desc. Set its flag
remove_only_when_retval_removed when encountering a simple return.
(isra_track_scalar_param_local_uses): Replace parameter call_uses_p
with desc. Pass it to isra_track_scalar_value_uses and set its
call_uses.
(ptr_parm_has_nonarg_uses): Accept parameter descriptor as a
parameter. If there is a direct return use, mark any..
(create_parameter_descriptors): Pass the whole parameter descriptor to
isra_track_scalar_param_local_uses and ptr_parm_has_nonarg_uses.
(process_scan_results): Copy the new flags.
(isra_write_node_summary): Stream the new flags.
(isra_read_node_info): Likewise.
(adjust_parameter_descriptions): Check that transformations
requring return removal only happen when return value is removed.
Restructure main loop. Adjust dump message.
gcc/testsuite/ChangeLog:
2023-08-18 Martin Jambor <mjambor@suse.cz>
PR ipa/110378
* gcc.dg/ipa/ipa-sra-32.c: New test.
* gcc.dg/ipa/pr110378-4.c: Likewise.
* gcc.dg/ipa/ipa-sra-4.c: Use a return value.
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PR 108007 is another manifestation where we rely on DCE to clean-up
after IPA-SRA and if the user explicitely switches DCE off, IPA-SRA
can leave behind statements which are fed uninitialized values and
trap, even though their results are themselves never used.
I have already fixed this for unused parameters in callees, this bug
shows that almost the same thing can happen for removed returns, on
the side of callers. This means that the issue has to be fixed
elsewhere, in call redirection. This patch adds a function which
looks for (and through, using a work-list) uses of operations fed
specific SSA names and removes them all.
That would have been easy if it wasn't for debug statements during
tree-inline (from which call redirection is also invoked). Debug
statements are decoupled from the rest at this point and iterating
over uses of SSAs does not bring them up. During tree-inline they are
handled especially at the end, I assume in order to make sure that
relative ordering of UIDs are the same with and without debug info.
This means that during tree-inline we need to make a hash of killed
SSAs, that we already have in copy_body_data, available to the
function making the purging. So the patch duly does also that, making
the interface slightly ugly.
gcc/ChangeLog:
2023-09-27 Martin Jambor <mjambor@suse.cz>
PR ipa/108007
* cgraph.h (cgraph_edge): Add a parameter to
redirect_call_stmt_to_callee.
* ipa-param-manipulation.h (ipa_param_adjustments): Add a
parameter to modify_call.
* cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
parameter killed_ssas, pass it to padjs->modify_call.
* ipa-param-manipulation.cc (purge_transitive_uses): New function.
(ipa_param_adjustments::modify_call): New parameter killed_ssas.
Instead of substituting uses, invoke purge_transitive_uses. If
hash of killed SSAs has not been provided, create a temporary one
and release SSAs that have been added to it.
* tree-inline.cc (redirect_all_calls): Create
id->killed_new_ssa_names earlier, pass it to edge redirection,
adjust a comment.
(copy_body): Release SSAs in id->killed_new_ssa_names.
gcc/testsuite/ChangeLog:
2023-05-11 Martin Jambor <mjambor@suse.cz>
PR ipa/108007
* gcc.dg/ipa/pr108007.c: New test.
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Rather than using a pass count to decide which parameters are passed to
VRP, makemit explicit.
* passes.def (pass_vrp): Pass "final pass" flag as parameter.
* tree-vrp.cc (vrp_pass_num): Remove.
(pass_vrp::my_pass): Remove.
(pass_vrp::pass_vrp): Add warn_p as a parameter.
(pass_vrp::final_p): New.
(pass_vrp::set_pass_param): Set final_p param.
(pass_vrp::execute): Call execute_range_vrp with no conditions.
(make_pass_vrp): Pass additional parameter.
(make_pass_early_vrp): Ditto.
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set_range_info should return TRUE only when it sets a new value. VRP no
longer overwrites global ranges DOM has set. Check for ranges in the
final listing.
gcc/
* tree-ssanames.cc (set_range_info): Return true only if the
current value changes.
gcc/testsuite/
* gcc.dg/pr93917.c: Check for ranges in final optimized listing.
* gcc.dg/tree-ssa/vrp-unreachable.c: Ditto.
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No functional change intended.
gcc/ada/ChangeLog:
* gcc-interface/misc.cc: Use text_info ctor.
gcc/analyzer/ChangeLog:
* analyzer-logging.cc (logger::log_va_partial): Use text_info
ctor.
* analyzer.cc (make_label_text): Likewise.
(make_label_text_n): Likewise.
* pending-diagnostic.cc (evdesc::event_desc::formatted_print):
Likewise.
gcc/c/ChangeLog:
* c-objc-common.cc (c_tree_printer): Update for "m_" prefixes to
text_info fields.
gcc/cp/ChangeLog:
* error.cc: Update for "m_" prefixes to text_info fields.
gcc/d/ChangeLog:
* d-diagnostic.cc (d_diagnostic_report_diagnostic): Use text_info
ctor.
gcc/ChangeLog:
* diagnostic.cc (diagnostic_set_info_translated): Update for "m_"
prefixes to text_info fields.
(diagnostic_report_diagnostic): Likewise.
(verbatim): Use text_info ctor.
(simple_diagnostic_path::add_event): Likewise.
(simple_diagnostic_path::add_thread_event): Likewise.
* dumpfile.cc (dump_pretty_printer::decode_format): Update for
"m_" prefixes to text_info fields.
(dump_context::dump_printf_va): Use text_info ctor.
* graphviz.cc (graphviz_out::graphviz_out): Use text_info ctor.
(graphviz_out::print): Likewise.
* opt-problem.cc (opt_problem::opt_problem): Likewise.
* pretty-print.cc (pp_format): Update for "m_" prefixes to
text_info fields.
(pp_printf): Use text_info ctor.
(pp_verbatim): Likewise.
(assert_pp_format_va): Likewise.
* pretty-print.h (struct text_info): Add ctors. Add "m_" prefix
to all fields.
* text-art/styled-string.cc (styled_string::from_fmt_va): Use
text_info ctor.
* tree-diagnostic.cc (default_tree_printer): Update for "m_"
prefixes to text_info fields.
* tree-pretty-print.h (pp_ti_abstract_origin): Likewise.
gcc/fortran/ChangeLog:
* error.cc (gfc_format_decoder): Update for "m_" prefixes to
text_info fields.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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This patch teaches the ARC backend that the contents of the carry flag
can be placed in an integer register conveniently using the "rlc rX,0"
instruction, which is a rotate-left-through-carry using zero as a source.
This is a convenient special case for the LTU form of the scc pattern.
unsigned int foo(unsigned int x, unsigned int y)
{
return (x+y) < x;
}
With -O2 -mcpu=em this is currently compiled to:
foo: add.f 0,r0,r1
mov_s r0,1 ;3
j_s.d [blink]
mov.hs r0,0
[which after an addition to set the carry flag, sets r0 to 1,
followed by a conditional assignment of r0 to zero if the
carry flag is clear]. With the new define_insn/optimization
in this patch, this becomes:
foo: add.f 0,r0,r1
j_s.d [blink]
rlc r0,0
This define_insn is also a useful building block for implementing
shifts and rotates.
2023-10-03 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/arc/arc.md (CC_ltu): New mode iterator for CC and CC_C.
(scc_ltu_<mode>): New define_insn to handle LTU form of scc_insn.
(*scc_insn): Don't split to a conditional move sequence for LTU.
gcc/testsuite/ChangeLog
* gcc.target/arc/scc-ltu.c: New test case.
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Hi all,
this patch converts a number of multi multi choice patterns within the
aarch64 backend to the new syntax.
The list of the converted patterns is in the Changelog.
For completeness here follows the list of multi choice patterns that
were rejected for conversion by my parser, they typically have some C
as asm output and require some manual intervention:
aarch64_simd_vec_set<mode>, aarch64_get_lane<mode>,
aarch64_cm<optab>di, aarch64_cm<optab>di, aarch64_cmtstdi,
*aarch64_movv8di, *aarch64_be_mov<mode>, *aarch64_be_movci,
*aarch64_be_mov<mode>, *aarch64_be_movxi, *aarch64_sve_mov<mode>_le,
*aarch64_sve_mov<mode>_be, @aarch64_pred_mov<mode>,
@aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx4SI_ONLY:mode>,
@aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx2DI_ONLY:mode>,
*aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx2DI_ONLY:mode>_sxtw,
*aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx2DI_ONLY:mode>_uxtw,
@aarch64_vec_duplicate_vq<mode>_le, *vec_extract<mode><Vel>_0,
*vec_extract<mode><Vel>_v128, *cmp<cmp_op><mode>_and,
*fcm<cmp_op><mode>_and_combine, @aarch64_sve_ext<mode>,
@aarch64_sve2_<su>aba<mode>, *sibcall_insn, *sibcall_value_insn,
*xor_one_cmpl<mode>3, *insv_reg<mode>_<SUBDI_BITS>,
*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>,
*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>, *aarch64_bfxil<mode>,
*aarch64_bfxilsi_uxtw,
*aarch64_<su_optab>cvtf<fcvt_target><GPF:mode>2_mult,
atomic_store<mode>.
Bootstraped and reg tested on aarch64-unknown-linux-gnu, also I
analysed tmp-mddump.md (from 'make mddump') and could not find
effective differences, okay for trunk?
Bests
Andrea
gcc/ChangeLog:
* config/aarch64/aarch64.md (@ccmp<CC_ONLY:mode><GPI:mode>)
(@ccmp<CC_ONLY:mode><GPI:mode>_rev, *call_insn, *call_value_insn)
(*mov<mode>_aarch64, load_pair_sw_<SX:mode><SX2:mode>)
(load_pair_dw_<DX:mode><DX2:mode>)
(store_pair_sw_<SX:mode><SX2:mode>)
(store_pair_dw_<DX:mode><DX2:mode>, *extendsidi2_aarch64)
(*zero_extendsidi2_aarch64, *load_pair_zero_extendsidi2_aarch64)
(*extend<SHORT:mode><GPI:mode>2_aarch64)
(*zero_extend<SHORT:mode><GPI:mode>2_aarch64)
(*extendqihi2_aarch64, *zero_extendqihi2_aarch64)
(*add<mode>3_aarch64, *addsi3_aarch64_uxtw, *add<mode>3_poly_1)
(add<mode>3_compare0, *addsi3_compare0_uxtw)
(*add<mode>3_compareC_cconly, add<mode>3_compareC)
(*add<mode>3_compareV_cconly_imm, add<mode>3_compareV_imm)
(*add<mode>3nr_compare0, subdi3, subv<GPI:mode>_imm)
(*cmpv<GPI:mode>_insn, sub<mode>3_compare1_imm, neg<mode>2)
(cmp<mode>, fcmp<mode>, fcmpe<mode>, *cmov<mode>_insn)
(*cmovsi_insn_uxtw, <optab><mode>3, *<optab>si3_uxtw)
(*and<mode>3_compare0, *andsi3_compare0_uxtw, one_cmpl<mode>2)
(*<NLOGICAL:optab>_one_cmpl<mode>3, *and<mode>3nr_compare0)
(*aarch64_ashl_sisd_or_int_<mode>3)
(*aarch64_lshr_sisd_or_int_<mode>3)
(*aarch64_ashr_sisd_or_int_<mode>3, *ror<mode>3_insn)
(*<optab>si3_insn_uxtw, <optab>_trunc<fcvt_target><GPI:mode>2)
(<optab><fcvt_target><GPF:mode>2)
(<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3)
(<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>3)
(*aarch64_<optab><mode>3_cssc, copysign<GPF:mode>3_insn): Update
to new syntax.
* config/aarch64/aarch64-sve2.md (@aarch64_scatter_stnt<mode>)
(@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
(*aarch64_mul_unpredicated_<mode>)
(@aarch64_pred_<sve_int_op><mode>, *cond_<sve_int_op><mode>_2)
(*cond_<sve_int_op><mode>_3, *cond_<sve_int_op><mode>_any)
(*cond_<sve_int_op><mode>_z, @aarch64_pred_<sve_int_op><mode>)
(*cond_<sve_int_op><mode>_2, *cond_<sve_int_op><mode>_3)
(*cond_<sve_int_op><mode>_any, @aarch64_sve_<sve_int_op><mode>)
(@aarch64_sve_<sve_int_op>_lane_<mode>)
(@aarch64_sve_add_mul_lane_<mode>)
(@aarch64_sve_sub_mul_lane_<mode>, @aarch64_sve2_xar<mode>)
(*aarch64_sve2_bcax<mode>, @aarch64_sve2_eor3<mode>)
(*aarch64_sve2_nor<mode>, *aarch64_sve2_nand<mode>)
(*aarch64_sve2_bsl<mode>, *aarch64_sve2_nbsl<mode>)
(*aarch64_sve2_bsl1n<mode>, *aarch64_sve2_bsl2n<mode>)
(*aarch64_sve2_sra<mode>, @aarch64_sve_add_<sve_int_op><mode>)
(*aarch64_sve2_<su>aba<mode>, @aarch64_sve_add_<sve_int_op><mode>)
(@aarch64_sve_add_<sve_int_op>_lane_<mode>)
(@aarch64_sve_qadd_<sve_int_op><mode>)
(@aarch64_sve_qadd_<sve_int_op>_lane_<mode>)
(@aarch64_sve_sub_<sve_int_op><mode>)
(@aarch64_sve_sub_<sve_int_op>_lane_<mode>)
(@aarch64_sve_qsub_<sve_int_op><mode>)
(@aarch64_sve_qsub_<sve_int_op>_lane_<mode>)
(@aarch64_sve_<sve_fp_op><mode>, @aarch64_<sve_fp_op>_lane_<mode>)
(@aarch64_pred_<sve_int_op><mode>)
(@aarch64_pred_<sve_fp_op><mode>, *cond_<sve_int_op><mode>_2)
(*cond_<sve_int_op><mode>_z, @aarch64_sve_<optab><mode>)
(@aarch64_<optab>_lane_<mode>, @aarch64_sve_<optab><mode>)
(@aarch64_<optab>_lane_<mode>, @aarch64_pred_<sve_fp_op><mode>)
(*cond_<sve_fp_op><mode>_any_relaxed)
(*cond_<sve_fp_op><mode>_any_strict)
(@aarch64_pred_<sve_int_op><mode>, *cond_<sve_int_op><mode>)
(@aarch64_pred_<sve_fp_op><mode>, *cond_<sve_fp_op><mode>)
(*cond_<sve_fp_op><mode>_strict): Update to new syntax.
* config/aarch64/aarch64-sve.md (*aarch64_sve_mov<mode>_ldr_str)
(*aarch64_sve_mov<mode>_no_ldr_str, @aarch64_pred_mov<mode>)
(*aarch64_sve_mov<mode>, aarch64_wrffr)
(mask_scatter_store<mode><v_int_container>)
(*mask_scatter_store<mode><v_int_container>_<su>xtw_unpacked)
(*mask_scatter_store<mode><v_int_container>_sxtw)
(*mask_scatter_store<mode><v_int_container>_uxtw)
(@aarch64_scatter_store_trunc<VNx4_NARROW:mode><VNx4_WIDE:mode>)
(@aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>)
(*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_sxtw)
(*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_uxtw)
(*vec_duplicate<mode>_reg, vec_shl_insert_<mode>)
(vec_series<mode>, @extract_<last_op>_<mode>)
(@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2)
(*cond_<optab><mode>_any, @aarch64_pred_<optab><mode>)
(@aarch64_sve_revbhw_<SVE_ALL:mode><PRED_HSD:mode>)
(@cond_<optab><mode>)
(*<optab><SVE_PARTIAL_I:mode><SVE_HSDI:mode>2)
(@aarch64_pred_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode>)
(@aarch64_cond_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode>)
(*cond_uxt<mode>_2, *cond_uxt<mode>_any, *cnot<mode>)
(*cond_cnot<mode>_2, *cond_cnot<mode>_any)
(@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2_relaxed)
(*cond_<optab><mode>_2_strict, *cond_<optab><mode>_any_relaxed)
(*cond_<optab><mode>_any_strict, @aarch64_pred_<optab><mode>)
(*cond_<optab><mode>_2, *cond_<optab><mode>_3)
(*cond_<optab><mode>_any, add<mode>3, sub<mode>3)
(@aarch64_pred_<su>abd<mode>, *aarch64_cond_<su>abd<mode>_2)
(*aarch64_cond_<su>abd<mode>_3, *aarch64_cond_<su>abd<mode>_any)
(@aarch64_sve_<optab><mode>, @aarch64_pred_<optab><mode>)
(*cond_<optab><mode>_2, *cond_<optab><mode>_z)
(@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2)
(*cond_<optab><mode>_3, *cond_<optab><mode>_any, <optab><mode>3)
(*cond_bic<mode>_2, *cond_bic<mode>_any)
(@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2_const)
(*cond_<optab><mode>_any_const, *cond_<sve_int_op><mode>_m)
(*cond_<sve_int_op><mode>_z, *sdiv_pow2<mode>3)
(*cond_<sve_int_op><mode>_2, *cond_<sve_int_op><mode>_any)
(@aarch64_pred_<optab><mode>, *cond_<optab><mode>_2_relaxed)
(*cond_<optab><mode>_2_strict, *cond_<optab><mode>_any_relaxed)
(*cond_<optab><mode>_any_strict, @aarch64_pred_<optab><mode>)
(*cond_<optab><mode>_2_relaxed, *cond_<optab><mode>_2_strict)
(*cond_<optab><mode>_2_const_relaxed)
(*cond_<optab><mode>_2_const_strict)
(*cond_<optab><mode>_3_relaxed, *cond_<optab><mode>_3_strict)
(*cond_<optab><mode>_any_relaxed, *cond_<optab><mode>_any_strict)
(*cond_<optab><mode>_any_const_relaxed)
(*cond_<optab><mode>_any_const_strict)
(@aarch64_pred_<optab><mode>, *cond_add<mode>_2_const_relaxed)
(*cond_add<mode>_2_const_strict)
(*cond_add<mode>_any_const_relaxed)
(*cond_add<mode>_any_const_strict, @aarch64_pred_<optab><mode>)
(*cond_<optab><mode>_2_relaxed, *cond_<optab><mode>_2_strict)
(*cond_<optab><mode>_any_relaxed, *cond_<optab><mode>_any_strict)
(@aarch64_pred_<optab><mode>, *cond_sub<mode>_3_const_relaxed)
(*cond_sub<mode>_3_const_strict, *cond_sub<mode>_const_relaxed)
(*cond_sub<mode>_const_strict, *aarch64_pred_abd<mode>_relaxed)
(*aarch64_pred_abd<mode>_strict)
(*aarch64_cond_abd<mode>_2_relaxed)
(*aarch64_cond_abd<mode>_2_strict)
(*aarch64_cond_abd<mode>_3_relaxed)
(*aarch64_cond_abd<mode>_3_strict)
(*aarch64_cond_abd<mode>_any_relaxed)
(*aarch64_cond_abd<mode>_any_strict, @aarch64_pred_<optab><mode>)
(@aarch64_pred_fma<mode>, *cond_fma<mode>_2, *cond_fma<mode>_4)
(*cond_fma<mode>_any, @aarch64_pred_fnma<mode>)
(*cond_fnma<mode>_2, *cond_fnma<mode>_4, *cond_fnma<mode>_any)
(<sur>dot_prod<vsi2qi>, @aarch64_<sur>dot_prod_lane<vsi2qi>)
(@<sur>dot_prod<vsi2qi>, @aarch64_<sur>dot_prod_lane<vsi2qi>)
(@aarch64_sve_add_<optab><vsi2qi>, @aarch64_pred_<optab><mode>)
(*cond_<optab><mode>_2_relaxed, *cond_<optab><mode>_2_strict)
(*cond_<optab><mode>_4_relaxed, *cond_<optab><mode>_4_strict)
(*cond_<optab><mode>_any_relaxed, *cond_<optab><mode>_any_strict)
(@aarch64_<optab>_lane_<mode>, @aarch64_pred_<optab><mode>)
(*cond_<optab><mode>_4_relaxed, *cond_<optab><mode>_4_strict)
(*cond_<optab><mode>_any_relaxed, *cond_<optab><mode>_any_strict)
(@aarch64_<optab>_lane_<mode>, @aarch64_sve_tmad<mode>)
(@aarch64_sve_<sve_fp_op>vnx4sf)
(@aarch64_sve_<sve_fp_op>_lanevnx4sf)
(@aarch64_sve_<sve_fp_op><mode>, *vcond_mask_<mode><vpred>)
(@aarch64_sel_dup<mode>, @aarch64_pred_cmp<cmp_op><mode>)
(*cmp<cmp_op><mode>_cc, *cmp<cmp_op><mode>_ptest)
(@aarch64_pred_fcm<cmp_op><mode>, @fold_extract_<last_op>_<mode>)
(@aarch64_fold_extract_vector_<last_op>_<mode>)
(@aarch64_sve_splice<mode>)
(@aarch64_sve_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>)
(@aarch64_sve_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>)
(*cond_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>_relaxed)
(*cond_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>_strict)
(*cond_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>)
(@aarch64_sve_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>)
(@aarch64_sve_<optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>)
(*cond_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>_relaxed)
(*cond_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>_strict)
(*cond_<optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>)
(@aarch64_sve_<optab>_trunc<SVE_FULL_SDF:mode><SVE_FULL_HSF:mode>)
(*cond_<optab>_trunc<SVE_FULL_SDF:mode><SVE_FULL_HSF:mode>)
(@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
(*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
(@aarch64_sve_<optab>_nontrunc<SVE_FULL_HSF:mode><SVE_FULL_SDF:mode>)
(*cond_<optab>_nontrunc<SVE_FULL_HSF:mode><SVE_FULL_SDF:mode>)
(@aarch64_brk<brk_op>, *aarch64_sve_<inc_dec><mode>_cntp): Update
to new syntax.
* config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>)
(load_pair<DREG:mode><DREG2:mode>)
(vec_store_pair<DREG:mode><DREG2:mode>, aarch64_simd_stp<mode>)
(aarch64_simd_mov_from_<mode>low)
(aarch64_simd_mov_from_<mode>high, and<mode>3<vczle><vczbe>)
(ior<mode>3<vczle><vczbe>, aarch64_simd_ashr<mode><vczle><vczbe>)
(aarch64_simd_bsl<mode>_internal<vczle><vczbe>)
(*aarch64_simd_bsl<mode>_alt<vczle><vczbe>)
(aarch64_simd_bsldi_internal, aarch64_simd_bsldi_alt)
(store_pair_lanes<mode>, *aarch64_combine_internal<mode>)
(*aarch64_combine_internal_be<mode>, *aarch64_combinez<mode>)
(*aarch64_combinez_be<mode>)
(aarch64_cm<optab><mode><vczle><vczbe>, *aarch64_cm<optab>di)
(aarch64_cm<optab><mode><vczle><vczbe>, *aarch64_mov<mode>)
(*aarch64_be_mov<mode>, *aarch64_be_movoi): Update to new syntax.
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Hi all,
this is to allow for spaces before "cons:" in the definitions of
patterns using the new compact syntax, ex:
(define_insn "aarch64_simd_dup<mode>"
[(set (match_operand:VDQ_I 0 "register_operand")
(vec_duplicate:VDQ_I
(match_operand:<VEL> 1 "register_operand")))]
"TARGET_SIMD"
{@ [ cons: =0 , 1 ; attrs: type ]
[ w , w ; neon_dup<q> ] dup\t%0.<Vtype>, %1.<Vetype>[0]
[ w , ?r ; neon_from_gp<q> ] dup\t%0.<Vtype>, %<vwcore>1
}
)
gcc/Changelog
2023-09-20 Andrea Corallo <andrea.corallo@arm.com>
* gensupport.cc (convert_syntax): Skip spaces before "cons:"
in new compact pattern syntax.
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Hi all,
this is to add support to the new compact pattern syntax for the case
where the constraints do appear unsorted like:
(define_insn "*<optab>si3_insn_uxtw"
[(set (match_operand:DI 0 "register_operand")
(zero_extend:DI (SHIFT_no_rotate:SI
(match_operand:SI 1 "register_operand")
(match_operand:QI 2 "aarch64_reg_or_shift_imm_si"))))]
""
{@ [cons: =0, 2, 1]
[ r, Uss, r] <shift>\\t%w0, %w1, %2
[ r, r, r] <shift>\\t%w0, %w1, %w2
}
[(set_attr "type" "bfx,shift_reg")]
)
Best Regards
Andrea
gcc/Changelog
2023-09-20 Richard Sandiford <richard.sandiford@arm.com>
* gensupport.cc (convert_syntax): Updated to support unordered
constraints in compact syntax.
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2023-10-02 John David Anglin <danglin@gcc.gnu.org>
gcc/testsuite/ChangeLog:
* gfortran.dg/pr95690.f90: Add hppa*-*-* to dg-error targets at line 5.
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