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2023-09-23d: Merge upstream dmd, druntime 4574d1728d, phobos d7e79f024.Iain Buclaw182-1665/+2002
D front-end changes: - Import dmd v2.105.0. - Catch clause must take only `const' or mutable exceptions. - Creating a `scope' class instance with a non-scope constructor is now `@system' only with `-fpreview=dip1000'. - Global `const' variables can no longer be initialized from a non-shared static constructor D runtime changes: - Import druntime v2.105.0. Phobos changes: - Import phobos v2.105.0. gcc/d/ChangeLog: * dmd/MERGE: Merge upstream dmd 4574d1728d. * dmd/VERSION: Bump version to v2.105.0. * d-diagnostic.cc (verror): Remove. (verrorSupplemental): Remove. (vwarning): Remove. (vwarningSupplemental): Remove. (vdeprecation): Remove. (vdeprecationSupplemental): Remove. (vmessage): Remove. (vtip): Remove. (verrorReport): New function. (verrorReportSupplemental): New function. * d-lang.cc (d_parse_file): Update for new front-end interface. * decl.cc (d_mangle_decl): Update for new front-end interface. * intrinsics.cc (maybe_set_intrinsic): Update for new front-end interface. libphobos/ChangeLog: * libdruntime/MERGE: Merge upstream druntime 4574d1728d. * src/MERGE: Merge upstream phobos d7e79f024.
2023-09-23testsuite: Add new test for already fixed PR111455Jakub Jelinek1-0/+37
The following testcase has been fixed by r14-4231. 2023-09-23 Jakub Jelinek <jakub@redhat.com> PR c++/111455 * g++.dg/ext/integer-pack8.C: New test.
2023-09-23RISC-V: Add VLS unary combine patternsJuzhe-Zhong3-17/+113
gcc/ChangeLog: * config/riscv/autovec-opt.md: Add VLS modes for conditional ABS/SQRT. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c: New test.
2023-09-23RISC-V: Suport FP floor auto-vectorizationPan Li10-2/+277
This patch would like to support auto-vectorization for the floor API in math.h. It depends on the -ffast-math option. When we would like to call floor/floorf like v2 = floor (v1), we will convert it into below insns (reference the implementation of llvm). * vfcvt.x.f v3, v1, RDN * vfcvt.f.x v2, v3 However, the floating point value may not need the cvt as above if its mantissa is zero. For example single precision floating point below. +-----------+---------------+-------------+ | raw float | binary layout | after floor | +-----------+---------------+-------------+ | 8388607.5 | 0x4affffff | 8388607.0 | | 8388608.0 | 0x4b000000 | 8388608.0 | | 8388609.0 | 0x4b000001 | 8388609.0 | +-----------+---------------+-------------+ All single floating point glte 8388608.0 will have all zero mantisaa. We leverage vmflt and mask to filter them out in vector and only do the cvt on mask. Befor this patch: math-floor-1.c:21:1: missed: couldn't vectorize loop ... .L3: flw fa0,0(s0) addi s0,s0,4 addi s1,s1,4 call ceilf fsw fa0,-4(s1) bne s0,s2,.L3 After this patch: ... fsrmi 2 // Rounding Down .L4: vfabs.v v1,v2 vmflt.vf v0,v1,fa5 vfcvt.x.f.v v3,v2,v0.t vfcvt.f.x.v v1,v3,v0.t vfsgnj.vv v1,v1,v2 bne .L4 .L14: fsrm a6 ret Please note VLS mode is also involved in this patch and covered by the test cases. gcc/ChangeLog: * config/riscv/autovec.md (floor<mode>2): New pattern. * config/riscv/riscv-protos.h (enum insn_flags): New enum type. (enum insn_type): Ditto. (expand_vec_floor): New function decl. * config/riscv/riscv-v.cc (gen_floor_const_fp): New function impl. (expand_vec_floor): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-floor-0.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-floor-1.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-floor-2.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-floor-3.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-floor-run-1.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-floor-run-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/math-floor-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-09-23RISC-V: Remove FP run test for ceil.Pan Li1-39/+0
FP16 is not well reconciled when linking. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-0.c: Remove. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-09-23Daily bump.GCC Administrator4-1/+243
2023-09-22c++ __integer_pack conversion again [PR111357]Jason Merrill1-2/+7
As Jakub pointed out, the real problem here is that in a partial substitution we're forgetting the conversion to the type of the non-type template argument, because maybe_convert_nontype_argument doesn't do anything with value-dependent arguments. I'm experimenting with changing that, but in the meantime we can work around it here. PR c++/111357 gcc/cp/ChangeLog: * pt.cc (expand_integer_pack): Use IMPLICIT_CONV_EXPR.
2023-09-22c++: constexpr and designated initializerJason Merrill2-1/+7
The change of active member being non-constant (before C++20) results in a CONSTRUCTOR with a null value for the first field, don't crash. gcc/cp/ChangeLog: * constexpr.cc (free_constructor): Handle null ce->value. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/constexpr-union7.C: New test.
2023-09-22c++: unroll pragma in templates [PR111529]Jason Merrill3-12/+25
We were failing to handle ANNOTATE_EXPR in tsubst_copy_and_build, leading to problems with substitution of any wrapped expressions. Let's also not tell users that lambda templates are available in C++14. PR c++/111529 gcc/cp/ChangeLog: * parser.cc (cp_parser_lambda_declarator_opt): Don't suggest -std=c++14 for lambda templates. * pt.cc (tsubst_expr): Move ANNOTATE_EXPR handling... (tsubst_copy_and_build): ...here. gcc/testsuite/ChangeLog: * g++.dg/ext/unroll-4.C: New test.
2023-09-22RISC-V: Refine the code gen for ceil auto vectorization.Pan Li5-47/+54
We vectorized below ceil code already. void test_ceil (float *out, float *in, int count) { for (unsigned i = 0; i < count; i++) out[i] = __builtin_ceilf (in[i]); } Before this patch: vfmv.v.x v4,fa0 // can be removed vfabs.v v0,v1 vmv1r.v v2,v1 // can be removed vmflt.vv v0,v0,v4 // can be refined to vmflt.vf vfcvt.x.f.v v3,v1,v0.t vfcvt.f.x.v v2,v3,v0.t vfsgnj.vv v2,v2,v1 After this patch: vfabs.v v1,v2 vmflt.vf v0,v1,fa5 vfcvt.x.f.v v3,v2,v0.t vfcvt.f.x.v v1,v3,v0.t vfsgnj.vv v1,v1,v2 We can generate better code include below items. * Remove vfmv.v.f. * Take vmflt.vf instead of vmflt.vv. * Remove vmv1r.v. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vec_float_cmp_mask): Refactor. (emit_vec_float_cmp_mask): Rename. (expand_vec_copysign): Ditto. (emit_vec_copysign): Ditto. (emit_vec_abs): New function impl. (emit_vec_cvt_x_f): Ditto. (emit_vec_cvt_f_x): Ditto. (expand_vec_ceil): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c: Adjust body check. * gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-09-22RISC-V: Add VLS mode widen ternary testsJuzhe-Zhong7-0/+328
gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS modes. * gcc.target/riscv/rvv/autovec/vls/wfma-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/wfma-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/wfma-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/wfms-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/wfnma-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/wfnms-1.c: New test.
2023-09-22RISC-V: Add VLS widen binary combine patternsJuzhe-Zhong13-0/+710
Regression passed. Committed. gcc/ChangeLog: * config/riscv/vector-iterators.md: Extend VLS modes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS modes cond tests. * gcc.target/riscv/rvv/autovec/vls/wadd-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/wadd-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/wadd-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/wadd-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/wmul-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/wmul-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/wmul-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/wsub-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/wsub-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/wsub-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/wsub-4.c: New test.
2023-09-22c++: missing SFINAE in grok_array_decl [PR111493]Patrick Palka2-3/+37
We should guard both the diagnostic and backward compatibilty fallback code with tf_error, so that in a SFINAE context we don't issue any diagnostics and correctly treat ill-formed C++23 multidimensional subscript operator expressions as such. PR c++/111493 gcc/cp/ChangeLog: * decl2.cc (grok_array_decl): Guard diagnostic and backward compatibility fallback code paths with tf_error. gcc/testsuite/ChangeLog: * g++.dg/cpp23/subscript15.C: New test.
2023-09-22c++: constraint rewriting during ttp coercion [PR111485]Patrick Palka3-2/+44
In order to compare the constraints of a ttp with that of its argument, we rewrite the ttp's constraints in terms of the argument template's template parameters. The substitution to achieve this currently uses a single level of template arguments, but that never does the right thing because a ttp's template parameters always have level >= 2. This patch fixes this by including the outer template arguments in the substitution, which ought to match the depth of the ttp. The second testcase demonstrates it's better to substitute the concrete outer template arguments instead of generic ones since a ttp's constraints could depend on outer parameters. PR c++/111485 gcc/cp/ChangeLog: * pt.cc (is_compatible_template_arg): New parameter 'args'. Add the outer template arguments 'args' to 'new_args'. (convert_template_argument): Pass 'args' to is_compatible_template_arg. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-ttp5.C: New test. * g++.dg/cpp2a/concepts-ttp6.C: New test.
2023-09-22RISC-V: Move ceil test cases to unop folderPan Li8-0/+0
gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/math-ceil-0.c: Moved to... * gcc.target/riscv/rvv/autovec/unop/math-ceil-0.c: ...here. * gcc.target/riscv/rvv/autovec/math-ceil-1.c: Moved to... * gcc.target/riscv/rvv/autovec/unop/math-ceil-1.c: ...here. * gcc.target/riscv/rvv/autovec/math-ceil-2.c: Moved to... * gcc.target/riscv/rvv/autovec/unop/math-ceil-2.c: ...here. * gcc.target/riscv/rvv/autovec/math-ceil-3.c: Moved to... * gcc.target/riscv/rvv/autovec/unop/math-ceil-3.c: ...here. * gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: Moved to... * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-0.c: ...here. * gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: Moved to... * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-1.c: ...here. * gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: Moved to... * gcc.target/riscv/rvv/autovec/unop/math-ceil-run-2.c: ...here. * gcc.target/riscv/rvv/autovec/test-math.h: Moved to... * gcc.target/riscv/rvv/autovec/unop/test-math.h: ...here. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-09-22RISC-V: Remove @ of vec_duplicate patternJuzhe-Zhong2-4/+2
It's obvious the @ of vec_duplicate pattern is duplicate. Regression passed. Committed. gcc/ChangeLog: * config/riscv/riscv-v.cc (gen_const_vector_dup): Use global expand function. * config/riscv/vector.md (@vec_duplicate<mode>): Remove @. (vec_duplicate<mode>): Ditto.
2023-09-22RISC-V: Add VLS conditional patterns supportJuzhe-Zhong31-118/+2059
Regression passed. Committed. gcc/ChangeLog: * config/riscv/autovec.md: Add VLS conditional patterns. * config/riscv/riscv-protos.h (expand_cond_unop): Ditto. (expand_cond_binop): Ditto. (expand_cond_ternop): Ditto. * config/riscv/riscv-v.cc (expand_cond_unop): Ditto. (expand_cond_binop): Ditto. (expand_cond_ternop): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS conditional tests. * gcc.target/riscv/rvv/autovec/vls/cond_add-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_add-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_and-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_div-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_div-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_max-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_max-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_min-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_min-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_not-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c: New test.
2023-09-22RISC-V: Rename the test macro for math autovec testPan Li8-9/+9
Rename TEST_CEIL to TEST_UNARY_CALL for the underlying function autovec patch testing. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/test-math.h: Rename. * gcc.target/riscv/rvv/autovec/math-ceil-0.c: Ditto. * gcc.target/riscv/rvv/autovec/math-ceil-1.c: Ditto. * gcc.target/riscv/rvv/autovec/math-ceil-2.c: Ditto. * gcc.target/riscv/rvv/autovec/math-ceil-3.c: Ditto. * gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: Ditto. * gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-09-22RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]xuli3-2/+22
Consider this following case: typedef int32_t vnx32si __attribute__ ((vector_size (128))); __attribute__ ((noipa)) void permute_##TYPE (TYPE values1, TYPE values2, \ TYPE *out) \ { \ TYPE v \ = __builtin_shufflevector (values1, values2, MASK_##NUNITS (0, NUNITS)); \ *(TYPE *) out = v; \ } T (vnx32si, 32) \ TEST_ALL (PERMUTE) Before this patch: li a4,31 vsetvli a5,zero,e32,m8,ta,ma vl8re32.v v24,0(a0) vid.v v8 vrsub.vx v8,v8,a4 vrgather.vv v16,v24,v8 vs8r.v v16,0(a2) ret The index vector register "v8" occupies 8 registers. We should optimize it into vrgatherei16.vv which is using int16 as the index elements. After this patch: vsetvli a5,zero,e16,m4,ta,ma li a4,31 vid.v v4 vl8re32.v v16,0(a0) vrsub.vx v4,v4,a4 vsetvli zero,zero,e32,m8,ta,ma vrgatherei16.vv v8,v16,v4 vs8r.v v8,0(a2) ret With vrgatherei16.vv, the v8 will occupy 4 registers instead of 8. Lower the register consuming and register pressure. PR target/111451 gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Optimization of vrgather.vv into vrgatherei16.vv. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Adjust case. * gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto.
2023-09-22RISC-V: Remove arch and abi option for run test case.Pan Li3-3/+3
Remove the -march and -mabi. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: Remove arch and abi. * gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-09-22RISC-V: Support combine cond extend and reduce sum to widen reduce sumLehua Ding6-0/+189
This patch support combining cond extend and reduce_sum to cond widen reduce_sum like combine the following three insns: (set (reg:RVVM2HI 149) (if_then_else:RVVM2HI (unspec:RVVMF8BI [ (const_vector:RVVMF8BI repeat [ (const_int 1 [0x1]) ]) (reg:DI 146) (const_int 2 [0x2]) repeated x2 (const_int 1 [0x1]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (const_vector:RVVM2HI repeat [ (const_int 0 [0]) ]) (unspec:RVVM2HI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF))) (set (reg:RVVM2HI 138) (if_then_else:RVVM2HI (reg:RVVMF8BI 135) (reg:RVVM2HI 148) (reg:RVVM2HI 149))) (set (reg:HI 150) (unspec:HI [ (reg:RVVM2HI 138) ] UNSPEC_REDUC_SUM)) into one insn: (set (reg:SI 147) (unspec:SI [ (if_then_else:RVVM2SI (reg:RVVMF16BI 135) (sign_extend:RVVM2SI (reg:RVVM1HI 136)) (if_then_else:RVVM2HI (unspec:RVVMF8BI [ (const_vector:RVVMF8BI repeat [ (const_int 1 [0x1]) ]) (reg:DI 146) (const_int 2 [0x2]) repeated x2 (const_int 1 [0x1]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (const_vector:RVVM2HI repeat [ (const_int 0 [0]) ]) (unspec:RVVM2HI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF))) ] UNSPEC_REDUC_SUM)) Consider the following C code: int16_t foo (int8_t *restrict a, int8_t *restrict pred) { int16_t sum = 0; for (int i = 0; i < 16; i += 1) if (pred[i]) sum += a[i]; return sum; } assembly before this patch: foo: vsetivli zero,16,e16,m2,ta,ma li a5,0 vmv.v.i v2,0 vsetvli zero,zero,e8,m1,ta,ma vl1re8.v v0,0(a1) vmsne.vi v0,v0,0 vsetvli zero,zero,e16,m2,ta,mu vle8.v v4,0(a0),v0.t vmv.s.x v1,a5 vsext.vf2 v2,v4,v0.t vredsum.vs v2,v2,v1 vmv.x.s a0,v2 slliw a0,a0,16 sraiw a0,a0,16 ret assembly after this patch: foo: li a5,0 vsetivli zero,16,e16,m1,ta,ma vmv.s.x v3,a5 vsetivli zero,16,e8,m1,ta,ma vl1re8.v v0,0(a1) vmsne.vi v0,v0,0 vle8.v v2,0(a0),v0.t vwredsum.vs v1,v2,v3,v0.t vsetivli zero,0,e16,m1,ta,ma vmv.x.s a0,v1 slliw a0,a0,16 sraiw a0,a0,16 ret gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_widen_reduc_plus_scal_<mode>): New combine patterns. * config/riscv/riscv-protos.h (enum insn_type): New insn_type. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: New test. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: New test.
2023-09-22RISC-V: Split VLS avl_type from NONVLMAX avl_typeLehua Ding2-21/+25
This patch split a VLS avl_type from the NONVLMAX avl_type, denoting those RVV insn with length set to the number of units of VLS modes. gcc/ChangeLog: * config/riscv/riscv-protos.h (enum avl_type): New VLS avl_type. * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Move comments.
2023-09-22RISC-V: Leverage __builtin_xx instead of math.h for testPan Li3-66/+63
The math.h may have problems in some environment, take __builtin__xx instead for testing. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c: Remove reference to math.h. * gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-09-22RISC-V: Support ceil and ceilf auto-vectorizationPan Li13-1/+472
Update in v4: * Add test for _Float16. * Remove unnecessary macro in def.h for test. Original log: This patch would like to support auto-vectorization for both the ceil and ceilf of math.h. It depends on the -ffast-math option. When we would like to call ceil/ceilf like v2 = ceil (v1), we will convert it into below insn (reference the implementation of llvm). * vfcvt.x.f v3, v1, RUP * vfcvt.f.x v2, v3 However, the floating point value may not need the cvt as above if its mantissa is zero. For example single precision floating point below. +-----------+---------------+ | float | binary layout | +-----------+---------------+ | 8388607.5 | 0x4affffff | | 8388608.0 | 0x4b000000 | | 8388609.0 | 0x4b000001 | +-----------+---------------+ All single floating point great than 8388608.0 will have all zero mantisaa. We leverage vmflt and mask to filter them out in vector and only do the cvt on mask. Befor this patch: math-ceil-1.c:21:1: missed: couldn't vectorize loop ... .L3: flw fa0,0(s0) addi s0,s0,4 addi s1,s1,4 call ceilf fsw fa0,-4(s1) bne s0,s2,.L3 After this patch: ... fsrmi 3 .L4: vfabs.v v0,v1 vmv1r.v v2,v1 vmflt.vv v0,v0,v4 sub a3,a3,a4 vfcvt.x.f.v v3,v1,v0.t vfcvt.f.x.v v2,v3,v0.t vfsgnj.vv v2,v2,v1 bne .L4 .L14: fsrm a6 ret Please note VLS mode is also involved in this patch and covered by the test cases. gcc/ChangeLog: * config/riscv/autovec.md (ceil<mode>2): New pattern. * config/riscv/riscv-protos.h (enum insn_flags): New enum type. (enum insn_type): Ditto. (expand_vec_ceil): New function decl. * config/riscv/riscv-v.cc (gen_ceil_const_fp): New function impl. (expand_vec_float_cmp_mask): Ditto. (expand_vec_copysign): Ditto. (expand_vec_ceil): Ditto. * config/riscv/vector.md: Add VLS mode support. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/math-ceil-0.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-1.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-2.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-3.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-run-0.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-run-1.c: New test. * gcc.target/riscv/rvv/autovec/math-ceil-run-2.c: New test. * gcc.target/riscv/rvv/autovec/test-math.h: New test. * gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-09-22Daily bump.GCC Administrator4-1/+265
2023-09-22RISC-V: Add VLS integer ABS supportJuzhe-Zhong2-3/+65
Regression passed. Committed. gcc/ChangeLog: * config/riscv/autovec.md: Extend VLS modes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/abs-2.c: New test.
2023-09-21RISC-V: Add more VLS unary testsJuzhe-Zhong3-0/+173
Notice we are missing these tests. Committed. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/abs-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/not-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/sqrt-1.c: New test.
2023-09-21RISC-V: Support VLS mult highJuzhe-Zhong3-0/+159
Regression passed. Committed. gcc/ChangeLog: * config/riscv/vector-iterators.md: Extend VLS modes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mult high. * gcc.target/riscv/rvv/autovec/vls/mulh-1.c: New test.
2023-09-21RISC-V: Adjusting the comments of the ↵Lehua Ding1-12/+21
emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions V2 Change: Use Robin's comments. This patch adjusts the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions. The purpose of the adjustment is to make it clear that vlmax here is not VLMAX as defined inside the RVV ISA. This is because this function is used by RVV mode (e.g. RVVM1SImode) in addition to VLS mode (V16QI). For RVV mode, it means the same thing, for VLS mode, it indicates setting the vl to the number of units of the mode. Changed the comment because I didn't think of a better name. If there is a suitable name, feel free to discuss it. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_insn): Adjust comments. (emit_nonvlmax_insn): Adjust comments. (emit_vlmax_insn_lra): Adjust comments. Co-Authored-By: Robin Dapp <rdapp.gcc@gmail.com>
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-*linux*.Iain Buclaw3-0/+63
gcc/ChangeLog: * config.gcc (*linux*): Set rust target_objs, and target_has_targetrustm, * config/t-linux (linux-rust.o): New rule. * config/linux-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for i[34567]86-*-mingw* and x86_64-*-mingw*.Iain Buclaw3-0/+46
gcc/ChangeLog: * config.gcc (i[34567]86-*-mingw* | x86_64-*-mingw*): Set rust_target_objs and target_has_targetrustm. * config/t-winnt (winnt-rust.o): New rule. * config/winnt-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-fuchsia*.Iain Buclaw3-0/+64
gcc/ChangeLog: * config.gcc (*-*-fuchsia): Set tmake_rule, rust_target_objs, and target_has_targetrustm. * config/fuchsia-rust.cc: New file. * config/t-fuchsia: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-vxworks*Iain Buclaw3-0/+47
gcc/ChangeLog: * config.gcc (*-*-vxworks*): Set rust_target_objs and target_has_targetrustm. * config/t-vxworks (vxworks-rust.o): New rule. * config/vxworks-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-dragonfly*Iain Buclaw3-0/+46
gcc/ChangeLog: * config.gcc (*-*-dragonfly*): Set rust_target_objs and target_has_targetrustm. * config/t-dragonfly (dragonfly-rust.o): New rule. * config/dragonfly-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-solaris2*.Iain Buclaw3-0/+47
gcc/ChangeLog: * config.gcc (*-*-solaris2*): Set rust_target_objs and target_has_targetrustm. * config/t-sol2 (sol2-rust.o): New rule. * config/sol2-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-openbsd*Iain Buclaw3-0/+47
gcc/ChangeLog: * config.gcc (*-*-openbsd*): Set rust_target_objs and target_has_targetrustm. * config/t-openbsd (openbsd-rust.o): New rule. * config/openbsd-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-netbsd*Iain Buclaw3-0/+46
gcc/ChangeLog: * config.gcc (*-*-netbsd*): Set rust_target_objs and target_has_targetrustm. * config/t-netbsd (netbsd-rust.o): New rule. * config/netbsd-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-freebsd*Iain Buclaw3-0/+46
gcc/ChangeLog: * config.gcc (*-*-freebsd*): Set rust_target_objs and target_has_targetrustm. * config/t-freebsd (freebsd-rust.o): New rule. * config/freebsd-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_OS_INFO for *-*-darwin*Iain Buclaw3-0/+50
gcc/ChangeLog: * config.gcc (*-*-darwin*): Set rust_target_objs and target_has_targetrustm. * config/t-darwin (darwin-rust.o): New rule. * config/darwin-rust.cc: New file.
2023-09-21rust: Implement TARGET_RUST_CPU_INFO for i[34567]86-*-* and x86_64-*-*Iain Buclaw3-0/+155
There are still quite a lot of the previously reverted i386-rust.cc missing, so it's only a partial reimplementation. gcc/ChangeLog: * config/i386/t-i386 (i386-rust.o): New rule. * config/i386/i386-rust.cc: New file. * config/i386/i386-rust.h: New file.
2023-09-21rust: Reintroduce TARGET_RUST_OS_INFO hookIain Buclaw4-0/+16
gcc/ChangeLog: * doc/tm.texi: Regenerate. * doc/tm.texi.in: Document TARGET_RUST_OS_INFO. gcc/rust/ChangeLog: * rust-session-manager.cc (Session::init): Call targetrustm.rust_os_info. * rust-target.def (rust_os_info): New hook.
2023-09-21rust: Reintroduce TARGET_RUST_CPU_INFO hookIain Buclaw6-3/+42
gcc/ChangeLog: * doc/tm.texi: Regenerate. * doc/tm.texi.in: Add @node for Rust language and ABI, and document TARGET_RUST_CPU_INFO. gcc/rust/ChangeLog: * rust-lang.cc (rust_add_target_info): Remove sorry. * rust-session-manager.cc: Replace include of target.h with include of tm.h and rust-target.h. (Session::init): Call targetrustm.rust_cpu_info. * rust-target.def (rust_cpu_info): New hook. * rust-target.h (rust_add_target_info): Declare.
2023-09-21rust: Add skeleton support and documentation for targetrustm hooks.Iain Buclaw11-3/+220
gcc/ChangeLog: * Makefile.in (tm_rust_file_list, tm_rust_include_list, TM_RUST_H, RUST_TARGET_DEF, RUST_TARGET_H, RUST_TARGET_OBJS): New variables. (tm_rust.h, cs-tm_rust.h, default-rust.o, rust/rust-target-hooks-def.h, s-rust-target-hooks-def-h): New rules. (s-tm-texi): Also check timestamp on rust-target.def. (generated_files): Add TM_RUST_H and rust-target-hooks-def.h. (build/genhooks.o): Also depend on RUST_TARGET_DEF. * config.gcc (tm_rust_file, rust_target_objs, target_has_targetrustm): New variables. * configure: Regenerate. * configure.ac (tm_rust_file_list, tm_rust_include_list, rust_target_objs): Add substitutes. * doc/tm.texi: Regenerate. * doc/tm.texi.in (targetrustm): Document. (target_has_targetrustm): Document. * genhooks.cc: Include rust/rust-target.def. * config/default-rust.cc: New file. gcc/rust/ChangeLog: * rust-target-def.h: New file. * rust-target.def: New file. * rust-target.h: New file.
2023-09-21RISC-V: Enable undefined support for RVV auto-vectorization[PR110751]Juzhe-Zhong22-53/+105
Now GCC middle-end can support undefined value which is traslated into (scratch:mode). This patch is to enable RISC-V backend undefine value in ELSE value of COND_LEN_xxx/COND_xxx. Consider this following case: __attribute__((noipa)) void vrem_int8_t (int8_t * __restrict dst, int8_t * __restrict a, int8_t * __restrict b, int n) { for (int i = 0; i < n; i++) dst[i] = a[i] % b[i]; } Before this patch: vrem_int8_t: ble a3,zero,.L5 vsetvli a5,zero,e8,m1,ta,ma vmv.v.i v4,0 ---> redundant. .L3: vsetvli a5,a3,e8,m1,tu,ma ---> should be TA. vmv1r.v v1,v4 ---> redudant. vle8.v v3,0(a1) vle8.v v2,0(a2) sub a3,a3,a5 vrem.vv v1,v3,v2 vse8.v v1,0(a0) add a1,a1,a5 add a2,a2,a5 add a0,a0,a5 bne a3,zero,.L3 .L5: ret After this patch: vrem_int8_t: ble a3,zero,.L5 .L3: vsetvli a5,a3,e8,m1,ta,ma vle8.v v1,0(a1) vle8.v v2,0(a2) sub a3,a3,a5 vrem.vv v1,v1,v2 vse8.v v1,0(a0) add a1,a1,a5 add a2,a2,a5 add a0,a0,a5 bne a3,zero,.L3 .L5: ret PR target/110751 gcc/ChangeLog: * config/riscv/autovec.md: Enable scratch rtx in ELSE operand. * config/riscv/predicates.md (autovec_else_operand): New predicate. * config/riscv/riscv-v.cc (get_else_operand): New function. (expand_cond_len_unop): Adapt ELSE value. (expand_cond_len_binop): Ditto. (expand_cond_len_ternop): Ditto. * config/riscv/riscv.cc (riscv_preferred_else_value): New function. (TARGET_PREFERRED_ELSE_VALUE): New targethook. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Adapt test. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Ditto. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Ditto.
2023-09-21RISC-V: Fix SUBREG move of VLS mode[PR111486]Juzhe-Zhong2-1/+13
This patch fixes this bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111486 Before this patch, we can only handle (subreg:DI (reg:V8QI)) The PR ICE: during RTL pass: reload testcase.c: In function 'foo': testcase.c:8:1: internal compiler error: in require, at machmode.h:313 8 | } | ^ 0xa40cd2 opt_mode<machine_mode>::require() const /repo/gcc-trunk/gcc/machmode.h:313 0xa47091 opt_mode<machine_mode>::require() const /repo/gcc-trunk/gcc/config/riscv/riscv.cc:2546 0xa47091 riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*) /repo/gcc-trunk/gcc/config/riscv/riscv.cc:2543 0x1f1df10 gen_movdi(rtx_def*, rtx_def*) /repo/gcc-trunk/gcc/config/riscv/riscv.md:2024 0x10f1423 rtx_insn* insn_gen_fn::operator()<rtx_def*, rtx_def*>(rtx_def*, rtx_def*) const /repo/gcc-trunk/gcc/recog.h:411 0x10f1423 emit_move_insn_1(rtx_def*, rtx_def*) /repo/gcc-trunk/gcc/expr.cc:4164 0x10f183d emit_move_insn(rtx_def*, rtx_def*) /repo/gcc-trunk/gcc/expr.cc:4334 0x13070ec lra_emit_move(rtx_def*, rtx_def*) /repo/gcc-trunk/gcc/lra.cc:509 0x132295b curr_insn_transform /repo/gcc-trunk/gcc/lra-constraints.cc:4748 0x1324335 lra_constraints(bool) /repo/gcc-trunk/gcc/lra-constraints.cc:5488 0x130a3d4 lra(_IO_FILE*) /repo/gcc-trunk/gcc/lra.cc:2419 0x12bb629 do_reload /repo/gcc-trunk/gcc/ira.cc:5970 0x12bb629 execute /repo/gcc-trunk/gcc/ira.cc:6156 Because of (subreg:DI (reg:V2QI)) PR target/111486 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Fix bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr111486.c: New test.
2023-09-21check undefine_p for one more vrJiufu Guo2-1/+9
The root cause of PR111355 and PR111482 is missing to check if vr0 is undefined_p before call vr0.lower_bound. In the pattern "(X + C) / N", (if (INTEGRAL_TYPE_P (type) && get_range_query (cfun)->range_of_expr (vr0, @0)) (if (...) (plus (op @0 @2) { wide_int_to_tree (type, plus_op1 (c)); }) (if (TYPE_UNSIGNED (type) && c.sign_mask () < 0 ... && wi::geu_p (vr0.lower_bound (), -c)) In "(if (...)", there is code to prevent vr0's undefined_p, But in the "else" part, vr0's undefined_p is not checked before "wi::geu_p (vr0.lower_bound (), -c)". PR tree-optimization/111355 gcc/ChangeLog: * match.pd ((X + C) / N): Update pattern. gcc/testsuite/ChangeLog: * gcc.dg/pr111355.c: New test.
2023-09-21using overflow_free_p to simplify patternJiufu Guo1-30/+6
In r14-3582, an "overflow_free_p" interface is added. The pattern of "(t * 2) / 2" in match.pd can be simplified by using this interface. gcc/ChangeLog: * match.pd ((t * 2) / 2): Update to use overflow_free_p.
2023-09-21RISC-V: Optimized for strided load/store with stride == element width[PR111450]xuli5-17/+250
When stride == element width, vlsse should be optimized into vle.v. vsse should be optimized into vse.v. PR target/111450 gcc/ChangeLog: * config/riscv/constraints.md (c01): const_int 1. (c02): const_int 2. (c04): const_int 4. (c08): const_int 8. * config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for stride operand. (vector_eew16_stride_operand): Ditto. (vector_eew32_stride_operand): Ditto. (vector_eew64_stride_operand): Ditto. * config/riscv/vector-iterators.md: New iterator for stride operand. * config/riscv/vector.md: Add stride = element width constraint. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111450.c: New test.
2023-09-21RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic namesLehua Ding2-16/+16
This little rename vector_gs_scale_operand_16/32 to more generic names const_1_or_2/4_operand. So it's a little better understood when offered for use elsewhere. gcc/ChangeLog: * config/riscv/predicates.md (const_1_or_2_operand): Rename. (const_1_or_4_operand): Ditto. (vector_gs_scale_operand_16): Ditto. (vector_gs_scale_operand_32): Ditto. * config/riscv/vector-iterators.md: Adjust.
2023-09-21RISC-V: Support VLS INT <-> FP conversionsJuzhe-Zhong15-16/+882
Support INT <-> FP VLS auto-vectorization patterns. Regression passed. Committed. gcc/ChangeLog: * config/riscv/autovec.md: Extend VLS modes. * config/riscv/vector-iterators.md: Ditto. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/convert-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-10.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-11.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-12.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-7.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-8.c: New test. * gcc.target/riscv/rvv/autovec/vls/convert-9.c: New test.
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