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2024-07-30RISC-V: Add configure check for B extention supportEdwin Lu4-0/+50
Binutils 2.42 and before don't recognize the b extension in the march strings even though it supports zba_zbb_zbs. Add a configure check to ignore the b in the march string if found. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): Skip b in march string * config.in: Regenerate. * configure: Regenerate. * configure.ac: Add B assembler check Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-07-30testsuite: fix whitespace in dg-require-effective-target directivesSam James3-3/+3
PR middle-end/54400 PR target/98161 * gcc.dg/vect/bb-slp-layout-18.c: Fix whitespace in dg directive. * gcc.dg/vect/bb-slp-pr54400.c: Likewise. * gcc.target/i386/pr98161.c: Likewise.
2024-07-30gimple ssa: Teach switch conversion to optimize powers of 2 switchesFilip Kastl6-6/+555
Sometimes a switch has case numbers that are powers of 2. Switch conversion usually isn't able to optimize these switches. This patch adds "exponential index transformation" to switch conversion. After switch conversion applies this transformation on the switch the index variable of the switch becomes the exponent instead of the whole value. For example: switch (i) { case (1 << 0): return 0; case (1 << 1): return 1; case (1 << 2): return 2; ... case (1 << 30): return 30; default: return 31; } gets transformed roughly into switch (log2(i)) { case 0: return 0; case 1: return 1; case 2: return 2; ... case 30: return 30; default: return 31; } This enables switch conversion to further optimize the switch. This patch only enables this transformation if there are optabs for FFS so that the base 2 logarithm can be computed efficiently at runtime. gcc/ChangeLog: * tree-switch-conversion.cc (can_log2): New static function to check if gen_log2 can be used on current target. (gen_log2): New static function to generate efficient GIMPLE code for taking an exact base 2 log. (gen_pow2p): New static function to generate efficient GIMPLE code for checking if a value is a power of 2. (switch_conversion::switch_conversion): Track if the transformation happened. (switch_conversion::is_exp_index_transform_viable): New function to decide whether the transformation should be applied. (switch_conversion::exp_index_transform): New function to execute the transformation. (switch_conversion::gen_inbound_check): Don't remove the default BB if the transformation happened. (switch_conversion::expand): Execute the transform if it is viable. Skip the "sufficiently small case range" test if the transformation is going to be executed. * tree-switch-conversion.h: Add is_exp_index_transform_viable and exp_index_transform. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/switch-3.c: Disable switch conversion. * gcc.target/i386/switch-exp-transform-1.c: New test. * gcc.target/i386/switch-exp-transform-2.c: New test. * gcc.target/i386/switch-exp-transform-3.c: New test. Signed-off-by: Filip Kastl <fkastl@suse.cz>
2024-07-30libbacktrace: fix syntax of Windows registration functionsIan Lance Taylor1-2/+2
Adjust the syntax to keep MSVC happy. Fixes https://github.com/ianlancetaylor/libbacktrace/issues/131 * pecoff.c (LDR_DLL_NOTIFICATION): Put function modifier inside parentheses. (LDR_REGISTER_FUNCTION): Likewise.
2024-07-30testsuite: fix whitespace in dg-do assemble directiveSam James1-1/+1
* gcc.target/aarch64/simd/vmmla.c: Fix whitespace in dg directive.
2024-07-30testsuite: fix whitespace in dg-do preprocess directiveSam James1-1/+1
PR preprocessor/90581 * c-c++-common/cpp/fmax-include-depth.c: Fix whitespace in dg directive.
2024-07-30testsuite: fix whitespace in dg-do compile directivesSam James29-29/+29
Nothing seems to change here in reality at least on x86_64-pc-linux-gnu, but important to fix nonetheless in case people copy it. PR rtl-optimization/48633 PR tree-optimization/83072 PR tree-optimization/83073 PR tree-optimization/96542 PR tree-optimization/96707 PR tree-optimization/97567 PR target/69225 PR target/89929 PR target/96562 * g++.dg/pr48633.C: Fix whitespace in dg directive. * g++.dg/pr96707.C: Likewise. * g++.target/i386/mv28.C: Likewise. * gcc.dg/Warray-bounds-flex-arrays-1.c: Likewise. * gcc.dg/pr83072-2.c: Likewise. * gcc.dg/pr83073.c: Likewise. * gcc.dg/pr96542.c: Likewise. * gcc.dg/pr97567-2.c: Likewise. * gcc.target/i386/avx512fp16-11a.c: Likewise. * gcc.target/i386/avx512fp16-13.c: Likewise. * gcc.target/i386/avx512fp16-14.c: Likewise. * gcc.target/i386/avx512fp16-conjugation-1.c: Likewise. * gcc.target/i386/avx512fp16-neg-1a.c: Likewise. * gcc.target/i386/avx512fp16-set1-pch-1a.c: Likewise. * gcc.target/i386/avx512fp16vl-conjugation-1.c: Likewise. * gcc.target/i386/avx512fp16vl-neg-1a.c: Likewise. * gcc.target/i386/avx512fp16vl-set1-pch-1a.c: Likewise. * gcc.target/i386/avx512vlfp16-11a.c: Likewise. * gcc.target/i386/pr69225-1.c: Likewise. * gcc.target/i386/pr69225-2.c: Likewise. * gcc.target/i386/pr69225-3.c: Likewise. * gcc.target/i386/pr69225-4.c: Likewise. * gcc.target/i386/pr69225-5.c: Likewise. * gcc.target/i386/pr69225-6.c: Likewise. * gcc.target/i386/pr69225-7.c: Likewise. * gcc.target/i386/pr96562-1.c: Likewise. * gcc.target/riscv/rv32e_stack.c: Likewise. * gfortran.dg/c-interop/removed-restrictions-3.f90: Likewise. * gnat.dg/renaming1.adb: Likewise.
2024-07-30RISC-V: Add basic support for the Zacas extensionGianluca Guida49-13/+901
This patch adds support for amocas.{b|h|w|d}. Support for amocas.q (64/128 bit cas for rv32/64) will be added in a future patch. Extension: https://github.com/riscv/riscv-zacas Ratification: https://jira.riscv.org/browse/RVS-680 gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zacas extension. * config/riscv/arch-canonicalize: Make zacas imply zaamo. * config/riscv/riscv.opt: Add zacas. * config/riscv/sync.md (zacas_atomic_cas_value<mode>): New pattern. (atomic_compare_and_swap<mode>): Use new pattern for compare-and-swap ops. (zalrsc_atomic_cas_value_strong<mode>): Rename atomic_cas_value_strong. * doc/sourcebuild.texi: Add Zacas documentation. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add zacas testsuite infra support. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: Remove zacas to continue to test the lr/sc pairs. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto. * gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: Ditto. * gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c: New test. * gcc.target/riscv/amo/zacas-char-requires-zabha.c: New test. * gcc.target/riscv/amo/zacas-char-requires-zacas.c: New test. * gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c: New test. * gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-char-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c: New test. * gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c: New test. Co-authored-by: Patrick O'Neill <patrick@rivosinc.com> Tested-by: Andrea Parri <andrea@rivosinc.com> Signed-Off-By: Gianluca Guida <gianluca@rivosinc.com>
2024-07-30RISC-V: Remove configure check for zabhaPatrick O'Neill4-51/+3
This patch removes the zabha configure check since it's not a breaking change and updates the existing zaamo/zalrsc comment. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): Remove zabha configure check handling and clarify zaamo/zalrsc comment. * config.in: Regenerate. * configure: Regenerate. * configure.ac: Remove zabha configure check. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2024-07-30libstdc++: Fix overwriting files with fs::copy_file on WindowsJonathan Wakely5-33/+199
There are no inode numbers on Windows filesystems, so stat_type::st_ino is always zero and the check for equivalent files in do_copy_file was incorrectly identifying distinct files as equivalent. This caused copy_file to incorrectly report errors when trying to overwrite existing files. The fs::equivalent function already does the right thing on Windows, so factor that logic out into a new function that can be reused by fs::copy_file. The tests for fs::copy_file were quite inadequate, so this also adds checks for that function's error conditions. libstdc++-v3/ChangeLog: * src/c++17/fs_ops.cc (auto_win_file_handle): Change constructor parameter from const path& to const wchar_t*. (fs::equiv_files): New function. (fs::equivalent): Use equiv_files. * src/filesystem/ops-common.h (fs::equiv_files): Declare. (do_copy_file): Use equiv_files. * src/filesystem/ops.cc (fs::equiv_files): Define. (fs::copy, fs::equivalent): Use equiv_files. * testsuite/27_io/filesystem/operations/copy.cc: Test overwriting directory contents recursively. * testsuite/27_io/filesystem/operations/copy_file.cc: Test overwriting existing files.
2024-07-30libstdc++: Fix fs::hard_link_count behaviour on MinGW [PR113663]Lennox Shou Hao Ho2-22/+74
std::filesystem::hard_link_count() always returns 1 on mingw-w64ucrt-11.0.1-r3 on Windows 10 19045 hard_link_count() queries _wstat64() on MinGW-w64 The MSFT documentation claims _wstat64() will always return 1 *non*-NTFS volumes https://learn.microsoft.com/en-us/previous-versions/visualstudio/visual-studio-2013/14h5k7ff(v=vs.120) My tests suggest that is not always true - hard_link_count()/_wstat64() still returns 1 on NTFS. GetFileInformationByHandle does return the correct result of 2. Please see the PR for a minimal repro. This patch changes the Windows implementation to always call GetFileInformationByHandle. PR libstdc++/113663 libstdc++-v3/ChangeLog: * src/c++17/fs_ops.cc (fs::equivalent): Moved helper class auto_handle to anonymous namespace as auto_win_file_handle. (fs::hard_link_count): Changed Windows implementation to use information provided by GetFileInformationByHandle which is more reliable. * testsuite/27_io/filesystem/operations/hard_link_count.cc: New test. Signed-off-by: "Lennox" Shou Hao Ho <lennoxhoe@gmail.com> Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
2024-07-30c++: diagnose usage of co_await and co_yield in default args [PR115906]Arsen Arsenović5-3/+80
This is a partial fix for PR115906. Per [expr.await] 2s3, "An await-expression shall not appear in a default argument ([dcl.fct.default])". This patch introduces the diagnostic in that case, and in the case of a co_yield (as co_yield is defined in terms of co_await, so prerequisites of co_await hold). PR c++/115906 - [coroutines] missing diagnostic and ICE when co_await used as default argument in function declaration gcc/cp/ChangeLog: PR c++/115906 * parser.cc (cp_parser_unary_expression): Reject await expressions if use of local variables is currently forbidden. (cp_parser_yield_expression): Reject yield expressions if use of local variables is currently forbidden. gcc/testsuite/ChangeLog: PR c++/115906 * g++.dg/coroutines/pr115906-yield.C: New test. * g++.dg/coroutines/pr115906.C: New test. * g++.dg/coroutines/co-await-syntax-02-outside-fn.C: Don't rely on default arguments. * g++.dg/coroutines/co-yield-syntax-01-outside-fn.C: Ditto.
2024-07-30c++: fix ICE on FUNCTION_DECLs inside coroutines [PR115906]Arsen Arsenovic2-2/+21
When register_local_var_uses iterates a BIND_EXPRs BIND_EXPR_VARS, it fails to account for the fact that FUNCTION_DECLs might be present, and later passes it to DECL_HAS_VALUE_EXPR_P. This leads to a tree check failure in DECL_HAS_VALUE_EXPR_P: tree check: expected var_decl or parm_decl or result_decl, have function_decl in register_local_var_uses We only care about PARM_DECL and VAR_DECL, so select only those. PR c++/115906 - [coroutines] missing diagnostic and ICE when co_await used as default argument in function declaration gcc/cp/ChangeLog: PR c++/115906 * coroutines.cc (register_local_var_uses): Only process PARM_DECL and VAR_DECLs. gcc/testsuite/ChangeLog: PR c++/115906 * g++.dg/coroutines/coro-function-decl.C: New test.
2024-07-30SVE intrinsics: Add strength reduction for division by constant.Jennifer Schmitz6-57/+1031
This patch folds SVE division where all divisor elements are the same power of 2 to svasrd (signed) or svlsr (unsigned). Tests were added to check 1) whether the transform is applied (existing test harness was amended), and 2) correctness using runtime tests for all input types of svdiv; for signed and unsigned integers, several corner cases were covered. The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression. OK for mainline? Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com> gcc/ * config/aarch64/aarch64-sve-builtins-base.cc (svdiv_impl::fold): Implement strength reduction. gcc/testsuite/ * gcc.target/aarch64/sve/div_const_run.c: New test. * gcc.target/aarch64/sve/acle/asm/div_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/div_u64.c: Likewise.
2024-07-30c++: make source_location follow DECL_RAMP_FNArsen Arsenović2-1/+69
This fixes the value of current_function in compiler generated coroutine code. PR c++/110855 - std::source_location doesn't work with C++20 coroutine gcc/cp/ChangeLog: PR c++/110855 * cp-gimplify.cc (fold_builtin_source_location): Use the name of the DECL_RAMP_FN of the current function if present. gcc/testsuite/ChangeLog: PR c++/110855 * g++.dg/coroutines/pr110855.C: New test.
2024-07-30testsuite: fix dg-do run whitespaceSam James5-5/+5
This caused the tests to not be run. I may do further passes for non-run next. Tested on x86_64-pc-linux-gnu and checked test logs before/after. PR c/53548 PR target/101529 PR tree-optimization/102359 * c-c++-common/fam-in-union-alone-in-struct-1.c: Fix whitespace in dg directive. * c-c++-common/fam-in-union-alone-in-struct-2.c: Likewise. * c-c++-common/torture/builtin-shufflevector-2.c: Likewise. * g++.dg/pr102359_2.C: Likewise. * g++.target/i386/mvc1.C: Likewise.
2024-07-30Fix warnings for tree formats in gfc_errorPaul-Antoine Arras1-0/+4
This enables proper warnings for formats like %qD. gcc/c-family/ChangeLog: * c-format.cc (gcc_gfc_char_table): Add formats for tree objects.
2024-07-30gfortran.dg/compiler-directive_2.f: Update dg-errorTobias Burnus1-1/+1
This is a fallout of commit r15-2378-g29b1587e7d3466 OpenMP/Fortran: Fix handling of 'declare target' with 'link' clause [PR115559] where the '!GCC$' attributes were added in reverse order. Result: The error diagnostic for the stdcall/fastcall was reversed. Solution: Swap the order in dg-error. gcc/testsuite/ChangeLog: * gfortran.dg/compiler-directive_2.f: Update dg-error.
2024-07-30AVR: Propose to use attribute signal(n) via AVR-LibC's ISR_N.Georg-Johann Lay1-7/+23
gcc/ * doc/extend.texi (AVR Function Attributes): Propose to use attribute signal(n) via AVR-LibC's ISR_N from avr/interrupt.h
2024-07-30RISC-V: Take Xmode instead of Pmode for ussub expandingPan Li1-12/+12
The Pmode is designed for pointer, thus leverage the Xmode instead for the expanding of the ussub. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_ussub): Promote to Xmode instead of Pmode. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-07-29xtensa: Add missing speed cost for TYPE_FARITH in TARGET_INSN_COSTTakayuki 'January June' Suwa1-0/+1
According to the implemented pipeline model, this cost can be assumed to be 1 clock cycle. gcc/ChangeLog: * config/xtensa/xtensa.cc (xtensa_insn_cost): Add a case statement for TYPE_FARITH.
2024-07-29xtensa: Fix suboptimal loading of pooled constant value into hardware ↵Takayuki 'January June' Suwa1-5/+5
single-precision FP register We would like to implement the following to store a single-precision FP constant in a hardware FP register: - Load the bit-exact integer image of the pooled single-precision FP constant into an address (integer) register - Then, assign from that address register to a hardware single-precision FP register .literal_position .literal .LC1, 0x3f800000 ... l32r a9, .LC1 wfr f0, a9 However, it was emitted as follows: - Load the address of the FP constant entry in litpool into an address register - Then, dereference the address via that address register into a hardware single-precision FP register .literal_position .literal .LC1, 0x3f800000 .literal .LC2, .LC1 ... l32r a9, .LC2 lsi f0, a9, 0 It is obviously inefficient to read the pool twice. gcc/ChangeLog: * config/xtensa/xtensa.md (movsf_internal): Reorder alternative that corresponds to L32R machine instruction, and prefix alternatives that correspond to LSI/SSI instructions with the constraint character '^' so that they are disparaged by reload/LRA.
2024-07-29xtensa: Fix the regression introduce by r15-959-gbe9b3f4375e7Takayuki 'January June' Suwa3-14/+7
It is not wrong but also not optimal to specify that sibcalls require register A0 in RTX generation pass, by misleading DFA into thinking it is being used in function body. It would be better to specify it in pro_and_epilogue as with 'return' insn in order to avoid incorrect removing load that restores A0 in subsequent passes, but since it is not possible to modify each sibcall there, as a workaround we will preface it with a 'use' as before. This patch effectively reverts commit r15-959-gbe9b3f4375e7 gcc/ChangeLog: * config/xtensa/xtensa-protos.h (xtensa_expand_call): Remove the third argument. * config/xtensa/xtensa.cc (xtensa_expand_call): Remove the third argument and the code that uses it. * config/xtensa/xtensa.md (call, call_value, sibcall, sibcall_value): Remove each Boolean constant specified in the third argument of xtensa_expand_call. (sibcall_epilogue): Add emitting '(use A0_REG)' after calling xtensa_expand_epilogue.
2024-07-30Refine constraint "Bk" to define_special_memory_constraint.liuhongt2-1/+34
For below pattern, RA may still allocate r162 as v/k register, try to reload for address with leaq __libc_tsd_CTYPE_B@gottpoff(%rip), %rsi which result a linker error. (set (reg:DI 162) (mem/u/c:DI (const:DI (unspec:DI [(symbol_ref:DI ("a") [flags 0x60] <var_decl 0x7f621f6e1c60 a>)] UNSPEC_GOTNTPOFF)) Quote from H.J for why linker issue an error. >What do these do: > > leaq __libc_tsd_CTYPE_B@gottpoff(%rip), %rax > vmovq (%rax), %xmm0 > >From x86-64 TLS psABI: > >The assembler generates for the x@gottpoff(%rip) expressions a R X86 >64 GOTTPOFF relocation for the symbol x which requests the linker to >generate a GOT entry with a R X86 64 TPOFF64 relocation. The offset of >the GOT entry relative to the end of the instruction is then used in >the instruction. The R X86 64 TPOFF64 relocation is pro- cessed at >program startup time by the dynamic linker by looking up the symbol x >in the modules loaded at that point. The offset is written in the GOT >entry and later loaded by the addq instruction. > >The above code sequence looks wrong to me. gcc/ChangeLog: PR target/116043 * config/i386/constraints.md (Bk): Refine to define_special_memory_constraint. gcc/testsuite/ChangeLog: * gcc.target/i386/pr116043.c: New test.
2024-07-30i386: Add non-optimize prefetchi intrinsHaochen Jiang2-0/+35
Under -O0, with the "newly" introduced intrins, the variable will be transformed as mem instead of the origin symbol_ref. The compiler will then treat the operand as invalid and turn the operation into nop, which is not expected. Use macro for non-optimize to keep the variable as symbol_ref just as how prefetch intrin does. gcc/ChangeLog: * config/i386/prfchiintrin.h (_m_prefetchit0): Add macro for non-optimized option. (_m_prefetchit1): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/prefetchi-1b.c: New test.
2024-07-30Daily bump.GCC Administrator7-1/+174
2024-07-29xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructionsTakayuki 'January June' Suwa2-12/+66
[U]FLOAT.S machine instruction in Xtensa ISA, which converts an integer to a hardware single-precision FP register, has the ability to divide the result by power of two (0 to 15th). Similarly, [U]TRUNC.S instruction, which truncates single-precision FP to integer, can multiply the source value by power of two in advance, but neither of these currently uses this function (always specified with 0th power of two, i.e. a scaling factor of 1). This patch unleashes the scaling ability of the above instructions. /* example */ float test0(int a) { return a / 2.f; } float test1(unsigned int a) { return a / 32768.f; } int test2(float a) { return a * 2; } unsigned int test3(float a) { return a * 32768; } ;; before test0: movi.n a9, 0x3f float.s f0, a2, 0 slli a9, a9, 24 wfr f1, a9 mul.s f0, f0, f1 rfr a2, f0 ret.n test1: movi.n a9, 7 ufloat.s f0, a2, 0 slli a9, a9, 27 wfr f1, a9 mul.s f0, f0, f1 rfr a2, f0 ret.n test2: wfr f1, a2 add.s f0, f1, f1 trunc.s a2, f0, 0 ret.n test3: movi.n a9, 0x47 slli a9, a9, 24 wfr f1, a2 wfr f2, a9 mul.s f0, f1, f2 utrunc.s a2, f0, 0 ret.n ;; after test0: float.s f0, a2, 1 rfr a2, f0 ret.n test1: ufloat.s f0, a2, 15 rfr a2, f0 ret.n test2: wfr f0, a2 trunc.s a2, f0, 1 ret.n test3: wfr f0, a2 utrunc.s a2, f0, 15 ret.n gcc/ChangeLog: * config/xtensa/predicates.md (fix_scaling_operand, float_scaling_operand): New predicates. * config/xtensa/xtensa.md (any_fix/m_fix/s_fix, any_float/m_float/s_float): New code iterators and their attributes. (fix<s_fix>_truncsfsi2): Change from "fix_truncsfsi2". (*fix<s_fix>_truncsfsi2_2x, *fix<s_fix>_truncsfsi2_scaled): New insn definitions. (float<s_float>sisf2): Change from "floatsisf2". (*float<s_float>sisf2_scaled): New insn definition.
2024-07-29xtensa: Make use of std::swap where appropriateTakayuki 'January June' Suwa2-16/+6
No functional changes. gcc/ChangeLog: * config/xtensa/xtensa.cc (gen_int_relational, gen_float_relational): Replace tempvar-based value-swapping codes with std::swap. * config/xtensa/xtensa.md (movdi_internal, movdf_internal): Ditto.
2024-07-29[target/116104] Fix test guarding UINTVAL to extract shift countJeff Law1-1/+1
Minor oversight in the ext-dce bits. If the shift count is a constant vector, then we shouldn't be extracting values with [U]INTVAL. We guarded that test with CONSTANT_P, when it should have been CONSTANT_INT_P. Shows up on gcn, but I wouldn't be terribly surprised if it could be triggered elsewhere. Verified the testcase compiles on gcn. Haven't done a libgcc build for gcn though. Also verified x86 bootstraps and regression tests cleanly. Pushing to the trunk. PR target/116104 gcc/ * ext-dce.cc (carry_backpropagate): Fix test guarding UINTVAL extraction of shift count.
2024-07-29Polish libstdc++ 'dg-final' action 'file-io-diff'Thomas Schwinge1-8/+11
Follow-up to recent commit 515da03a838db05443ebcc4c543a405bed764188 "libstdc++: Add file-io-diff to replace @diff@ markup in I/O tests". Currently, if a 'dg-final' action 'file-io-diff' passes, we print nothing (should: 'PASS: [...]'), but if it fails, we just print: 'FAIL: files differ', for example ('*.log' file): [...] FAIL: 27_io/basic_ostream/inserters_other/wchar_t/2.cc -std=gnu++17 (test for excess errors) [...] UNRESOLVED: 27_io/basic_ostream/inserters_other/wchar_t/2.cc -std=gnu++17 compilation failed to produce executable diff: wostream_inserter_other_in.txt: No such file or directory diff: wostream_inserter_other_out.txt: No such file or directory FAIL: files differ diff: wostream_inserter_other_in.txt: No such file or directory diff: wostream_inserter_other_out.txt: No such file or directory When later the '*.sum' files get sorted, these 'FAIL: files differ' instances aren't grouped anymore with the other test cases' results, but they appear en bloc, lexically sorted between ('e[...]' and 's[...]'), for example: [...] PASS: ext/vstring/types/23767.cc -std=gnu++17 (test for excess errors) FAIL: files differ FAIL: files differ FAIL: files differ PASS: special_functions/01_assoc_laguerre/check_nan.cc -std=gnu++17 (test for excess errors) [...] Also, we shouldn't emit the actual 'diff' into the '*.sum' file, but just into the '*.log* file, and there's no need for 'spawn'/'expect', as we're not matching any specific messages. libstdc++-v3/ * testsuite/lib/libstdc++.exp (file-io-diff): Polish.
2024-07-29testsuite: fix PR111613 testSam James1-0/+0
PR ipa/111613 * gcc.c-torture/pr111613.c: Rename to.. * gcc.c-torture/execute/pr111613.c: ...this.
2024-07-29c++: generic lambda in default template argument [PR88313]Patrick Palka2-14/+35
Here we're rejecting the generic lambda inside the default template argument ultimately because auto_is_implicit_function_template_parm_p doesn't get set during parsing of the lambda's parameter list, due to the !processing_template_parmlist restriction. But when parsing a lambda parameter list we should always set that flag regardless of where the lambda appears. This patch makes sure of this via a local lambda_p flag. PR c++/88313 gcc/cp/ChangeLog: * parser.cc (cp_parser_lambda_declarator_opt): Pass lambda_p=true to cp_parser_parameter_declaration_clause. (cp_parser_direct_declarator): Pass lambda_p=false to to cp_parser_parameter_declaration_clause. (cp_parser_parameter_declaration_clause): Add bool lambda_p parameter. Consider lambda_p instead of current_class_type when setting parser->auto_is_implicit_function_template_parm_p. Don't consider processing_template_parmlist. (cp_parser_requirement_parameter_list): Pass lambda_p=false to cp_parser_parameter_declaration_clause. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/lambda-targ6.C: New test. Reviewed-by: Jason Merrill <jason@redhat.com>
2024-07-29doc: Improve punctuation and grammar in -fdiagnostics-format docsJonathan Wakely1-2/+3
The hyphen can be misunderstood to mean "emitted to -" i.e. stdout. Refer to both forms by name, rather than using "the former" for one and referring to the other by name. gcc/ChangeLog: * doc/invoke.texi (Diagnostic Message Formatting Options): Replace hyphen with a new sentence. Replace "the former" with the actual value.
2024-07-29gcc: xtensa: disable late-combine by defaultMax Filippov1-0/+13
gcc/ * config/xtensa/xtensa.cc (xtensa_option_override_after_change): New function. (TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): Define as xtensa_option_override_after_change. (xtensa_option_override): Call xtensa_option_override_after_change.
2024-07-29Revert "PR116080: Fix tail call dejagnu checks"Andi Kleen3-13/+5
This reverts commit ee41cd863b7c38ee3bc415ea7154954aa6facca3.
2024-07-29testsuite: make PR115277 test an execute oneSam James1-0/+0
PR middle-end/115277 * gcc.c-torture/compile/pr115277.c: Rename to... * gcc.c-torture/execute/pr115277.c: ...this.
2024-07-29AVR: avr.cc - Fix a typo in a diagnostic.Georg-Johann Lay1-1/+1
gcc/ * config/avr/avr.cc (avr_set_current_function): Fix typo in error message.
2024-07-29libgomp.texi: Update 'Device Information Routines' sectionTobias Burnus1-15/+33
Update 'OpenMP Runtime Library Routines' by adding a note that invoking inside a target region might invoke unspecified behavior. Additionally, update omp_{get,set}_default_device for omp_{initial,invalid}_device named constants. libgomp/ChangeLog: * libgomp.texi (OpenMP Runtime Library Routines): Add missing title to some commented still undocumented items. (Device Information Routines): Update.
2024-07-29rs6000, add comment to VEC_IC definitionCarl Love1-1/+2
This patch adds a comment to the VEC_IC definition to clarify the V1TI "TARGET_POWER10" mode that was added. gcc/ChangeLog: * config/rs6000/vector.md: Add comment for the VEC_IC define_mode_iterator.
2024-07-29Widening-Mul: Try .SAT_SUB for PLUS_EXPR when one op is IMMPan Li1-0/+1
After add the matching for .SAT_SUB when one op is IMM, there will be a new root PLUS_EXPR for the .SAT_SUB pattern. For example, Form 3: #define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \ T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_3 (T x) \ { \ return x >= IMM ? x - IMM : 0; \ } DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 11) And then we will have gimple before widening-mul as below. Thus, try the .SAT_SUB for the PLUS_EXPR. 4 │ __attribute__((noinline)) 5 │ uint64_t sat_u_sub_imm11_uint64_t_fmt_3 (uint64_t x) 6 │ { 7 │ long unsigned int _1; 8 │ uint64_t _3; 9 │ 10 │ <bb 2> [local count: 1073741824]: 11 │ _1 = MAX_EXPR <x_2(D), 11>; 12 │ _3 = _1 + 18446744073709551605; 13 │ return _3; 14 │ 15 │ } The below test suites are passed for this patch. 1. The rv64gcv fully regression tests. 2. The x86 bootstrap tests. 3. The x86 fully regression tests. gcc/ChangeLog: * tree-ssa-math-opts.cc (math_opts_dom_walker::after_dom_children): Try .SAT_SUB for PLUS_EXPR case. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-07-29OpenMP/Fortran: Fix handling of 'declare target' with 'link' clause [PR115559]Tobias Burnus3-26/+192
Contrary to a normal 'declare target', the 'declare target link' attribute also needs to set node->offloadable and push the offload_vars in the front end. Linked variables require that the data is mapped. For module variables, this can happen anywhere. For variables in an external subprograms or the main programm, this can only happen in the either that program itself or in an internal subprogram. - Whether a variable is just normally mapped or linked then becomes relevant if a device routine exists that can access that variable, i.e. an internal procedure has then to be marked as declare target. PR fortran/115559 gcc/fortran/ChangeLog: * trans-common.cc (build_common_decl): Add 'omp declare target' and 'omp declare target link' variables to offload_vars. * trans-decl.cc (add_attributes_to_decl): Likewise; update args and call decl_attributes. (get_proc_pointer_decl, gfc_get_extern_function_decl, build_function_decl): Update calls. (gfc_get_symbol_decl): Likewise; move after 'DECL_STATIC (t)=1' to avoid errors with symtab_node::get_create. libgomp/ChangeLog: * testsuite/libgomp.fortran/declare-target-link.f90: New test.
2024-07-29libgomp: Fix declare target link with offset array-section mapping [PR116107]Tobias Burnus2-2/+64
Assume that 'int var[100]' is 'omp declare target link(var)'. When now mapping an array section with offset such as 'map(to:var[20:10])', the device-side link pointer has to store &<device-storage-data>[0] minus the offset such that var[20] will access <device-storage-data>[0]. But the offset calculation was missed such that the device-side 'var' pointed to the first element of the mapped data - and var[20] points beyond at some invalid memory. PR middle-end/116107 libgomp/ChangeLog: * target.c (gomp_map_vars_internal): Honor array mapping offsets with declare-target 'link' variables. * testsuite/libgomp.c-c++-common/target-link-2.c: New test.
2024-07-29Fix ICE with -fdump-tree-morefJan Hubicka1-3/+4
gcc/ChangeLog: PR ipa/116055 * ipa-modref.cc (analyze_function): Do not ICE when flags regress.
2024-07-29testsuite: Fix up consteval-prop21.C for 32-bit targets [PR115986]Jakub Jelinek1-1/+7
The test fails on 32-bit targets (which don't support __int128 type). Using unsigned long long instead still ICEs before the fix and passes after it on those targets. 2024-07-29 Jakub Jelinek <jakub@redhat.com> PR c++/115986 * g++.dg/cpp2a/consteval-prop21.C (operator "" _c): Use unsigned long long rather than __uint128_t for return type if int128 is unsupported.
2024-07-29vect: Fix single_imm_use in tree_vect_patternsFeng Xue1-1/+2
Since pattern statement coexists with normal statements in a way that it is not linked into function body, we should not invoke utility procedures that depends on def/use graph on pattern statement, such as counting uses of a pseudo value defined by a pattern statement. This patch is to fix a bug of this type in vect pattern formation. 2024-06-14 Feng Xue <fxue@os.amperecomputing.com> gcc/ * tree-vect-patterns.cc (vect_recog_bitfield_ref_pattern): Only call single_imm_use if statement is not generated from pattern recognition.
2024-07-29i386: Fix AVX512 intrin macro typoHaochen Jiang9-10/+105
There are several typo in AVX512 intrins macro define. Correct them to solve errors when compiled with -O0. gcc/ChangeLog: * config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask): Correct operand order. (_mm_mask_fpclass_sd_mask): Ditto. (_mm256_maskz_reduce_round_ss): Use __builtin_ia32_reducess_mask_round instead of __builtin_ia32_reducesd_mask_round. (_mm_reduce_round_sd): Use -1 as mask since it is non-mask. (_mm_reduce_round_ss): Ditto. * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8): Correct operand usage. (_mm_mask_alignr_epi8): Ditto. * config/i386/avx512vlintrin.h (_mm_mask_alignr_epi64): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512bw-vpalignr-1b.c: New test. * gcc.target/i386/avx512dq-vfpclasssd-1b.c: Ditto. * gcc.target/i386/avx512dq-vfpclassss-1b.c: Ditto. * gcc.target/i386/avx512dq-vreducesd-1b.c: Ditto. * gcc.target/i386/avx512dq-vreducess-1b.c: Ditto. * gcc.target/i386/avx512vl-valignq-1b.c: Ditto.
2024-07-29Daily bump.GCC Administrator7-1/+97
2024-07-29testsuite: fix dg-add-options vs. dg-options orderingSam James1-1/+1
Per gccint, dg-add-options must be placed after all dg-options directives. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/cmpmem-2.c: Fix dg-add-options order.
2024-07-29testsuite: fix dg-do ordering wrt dg-require-*Sam James6-6/+6
Per gccint, dg-do must precede dg-require-effective-target or dg-require-support. Fix a handful of deviant cases. gcc/testsuite/ChangeLog: PR middle-end/25521 PR debug/93122 * gcc.dg/pr25521.c: Fix dg-do directive order. * gcc.dg/vect/vect-simd-clone-19.c: Likewise. * gcc.target/arm/stack-protector-7.c: Likewise. * gcc.target/arm/stack-protector-8.c: Likewise. * gcc.target/powerpc/pr93122.c: Likewise. libstdc++-v3/ChangeLog: PR libstdc++/110572 * testsuite/18_support/type_info/110572.cc: Fix dg-do directive order.
2024-07-28c++: if consteval and consteval propagation [PR115583]Jason Merrill2-2/+22
During speculative constant folding of an if consteval, we take the false branch, but the true branch is an immediate function context, so we don't want to to cp_fold_immediate it. So we could check IF_STMT_CONSTEVAL_P here. But beyond that, we don't want to do this inside a call, only when first parsing a function. PR c++/115583 gcc/cp/ChangeLog: * constexpr.cc (cxx_eval_conditional_expression): Don't cp_fold_immediate for if consteval. gcc/testsuite/ChangeLog: * g++.dg/cpp23/consteval-if13.C: New test.
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