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2023-08-31
Darwin: homogenize spelling of macOS
Francois-Xavier Coudert
17
-30
/
+28
2023-08-31
RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec
Pan Li
3
-31
/
+132
2023-08-31
RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovec
Pan Li
3
-25
/
+124
2023-08-31
aarch64: Fix return register handling in untyped_call
Richard Sandiford
1
-1
/
+19
2023-08-31
rs6000: Update instruction counts to match vec_* calls [PR111228]
Peter Bergner
8
-12
/
+12
2023-08-31
RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec
Pan Li
3
-27
/
+127
2023-08-31
RISC-V: Support rounding mode for VFMADD/VFMACC autovec
Pan Li
4
-23
/
+125
2023-08-31
middle-end/111253 - partly revert r11-6508-gabb1b6058c09a7
Richard Biener
2
-1
/
+32
2023-08-31
RISC-V: Add vector_scalar_shift_operand
Palmer Dabbelt
2
-3
/
+8
2023-08-31
RISC-V: Add Vector cost model framework for RVV
Juzhe-Zhong
5
-1
/
+134
2023-08-31
rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]
Jeevitha
4
-5
/
+38
2023-08-31
RISC-V: Change vsetvl tail and mask policy to default policy
Lehua Ding
8
-13
/
+26
2023-08-31
Fix gcc.dg/tree-ssa/forwprop-42.c
Richard Biener
1
-1
/
+2
2023-08-31
RISC-V: Refactor and clean emit_{vlmax,nonvlmax}_xxx functions
Lehua Ding
7
-952
/
+587
2023-08-31
Adjust gcc.target/i386/pr52252-{atom,core}.c
Richard Biener
2
-2
/
+2
2023-08-31
rs6000: call vector load/store with length only on 64-bit Power10
Haochen Gui
2
-4
/
+23
2023-08-31
arc: Honor SWAP option for lsl16 instruction
Claudiu Zissulescu
2
-2
/
+2
2023-08-31
arm: Remove unsigned variant of vcaddq_m
Stamatis Markianos-Wright
5
-29
/
+21
2023-08-31
Refactor vector HF/BF mode iterators and patterns.
liuhongt
1
-130
/
+108
2023-08-31
RISC-V: Fix vsetvl pass ICE
Lehua Ding
2
-1
/
+20
2023-08-31
Add overflow API for plus minus mult on range
Jiufu Guo
5
-0
/
+154
2023-08-31
Daily bump.
GCC Administrator
6
-1
/
+321
2023-08-30
analyzer: implement reference count checking for CPython plugin [PR107646]
Eric Feng
10
-44
/
+550
2023-08-30
Analyzer: include algorithm header
Francois-Xavier Coudert
1
-0
/
+1
2023-08-30
pru: Add cstore expansion patterns
Dimitar Dimitrov
9
-0
/
+126
2023-08-30
c++: CWG 2359, wrong copy-init with designated init [PR91319]
Marek Polacek
2
-0
/
+31
2023-08-30
c++: disallow constinit on functions [PR111173]
Marek Polacek
2
-0
/
+8
2023-08-30
tree-optimization/111228 - fix testcase
Richard Biener
1
-1
/
+1
2023-08-30
test: Add xfail into slp-reduc-7.c for RVV VLA vectorization
Juzhe-Zhong
1
-1
/
+1
2023-08-30
test: Adapt slp-26.c check for RVV
Juzhe-Zhong
1
-4
/
+4
2023-08-30
fortran: Restore interface to its previous state on error [PR48776]
Mikael Morin
4
-6
/
+113
2023-08-30
tree-optimization/111228 - combine two VEC_PERM_EXPRs
Richard Biener
2
-3
/
+155
2023-08-30
RISC-V: Remove movmisalign pattern for VLA modes
Juzhe-Zhong
1
-11
/
+0
2023-08-30
test: Fix XPASS of RVV
Juzhe-Zhong
6
-6
/
+6
2023-08-30
test: Add xfail for riscv_vector
Juzhe-Zhong
3
-3
/
+3
2023-08-30
RISC-V: support cm.mva01s cm.mvsa01 in zcmp
Die Li
5
-0
/
+85
2023-08-30
RISC-V: support cm.popretz in zcmp
Fei Gao
5
-25
/
+509
2023-08-30
RISC-V: support cm.push cm.pop cm.popret in zcmp
Fei Gao
11
-52
/
+2137
2023-08-30
tree-ssa-strlen: Fix up handling of conditionally zero memcpy [PR110914]
Jakub Jelinek
2
-1
/
+24
2023-08-30
store-merging: Fix up >= 64 bit insertion [PR111015]
Jakub Jelinek
2
-4
/
+33
2023-08-30
middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LANES to ivopts/alias
Juzhe-Zhong
2
-0
/
+7
2023-08-30
RISC-V: Make arch-24.c to test "success" case
Tsukasa OI
1
-3
/
+1
2023-08-30
RISC-V: Make sure we get VL REG operand for VLMAX vsetvl
Juzhe-Zhong
1
-4
/
+12
2023-08-30
RISC-V: Enable movmisalign for VLS modes
Juzhe-Zhong
3
-5
/
+57
2023-08-30
Daily bump.
GCC Administrator
8
-1
/
+300
2023-08-29
RISC-V: Use splitter to generate zicond in another case
Philipp Tomsich
2
-0
/
+45
2023-08-29
analyzer: new warning: -Wanalyzer-overlapping-buffers [PR99860]
David Malcolm
11
-2
/
+722
2023-08-29
c++: tweaks for explicit conversion fns diagnostic
Marek Polacek
4
-4
/
+77
2023-08-29
RISC-V: Added zvfh support for zfa extensions.
Jin Ma
4
-5
/
+104
2023-08-29
RISC-V: generate builtin macro for compilation with strict alignment
Edwin Lu
12
-0
/
+144
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