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2023-08-31Darwin: homogenize spelling of macOSFrancois-Xavier Coudert17-30/+28
2023-08-31RISC-V: Support rounding mode for VFNMADD/VFNMACC autovecPan Li3-31/+132
2023-08-31RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovecPan Li3-25/+124
2023-08-31aarch64: Fix return register handling in untyped_callRichard Sandiford1-1/+19
2023-08-31rs6000: Update instruction counts to match vec_* calls [PR111228]Peter Bergner8-12/+12
2023-08-31RISC-V: Support rounding mode for VFMSAC/VFMSUB autovecPan Li3-27/+127
2023-08-31RISC-V: Support rounding mode for VFMADD/VFMACC autovecPan Li4-23/+125
2023-08-31middle-end/111253 - partly revert r11-6508-gabb1b6058c09a7Richard Biener2-1/+32
2023-08-31RISC-V: Add vector_scalar_shift_operandPalmer Dabbelt2-3/+8
2023-08-31RISC-V: Add Vector cost model framework for RVVJuzhe-Zhong5-1/+134
2023-08-31rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]Jeevitha4-5/+38
2023-08-31RISC-V: Change vsetvl tail and mask policy to default policyLehua Ding8-13/+26
2023-08-31Fix gcc.dg/tree-ssa/forwprop-42.cRichard Biener1-1/+2
2023-08-31RISC-V: Refactor and clean emit_{vlmax,nonvlmax}_xxx functionsLehua Ding7-952/+587
2023-08-31Adjust gcc.target/i386/pr52252-{atom,core}.cRichard Biener2-2/+2
2023-08-31rs6000: call vector load/store with length only on 64-bit Power10Haochen Gui2-4/+23
2023-08-31arc: Honor SWAP option for lsl16 instructionClaudiu Zissulescu2-2/+2
2023-08-31arm: Remove unsigned variant of vcaddq_mStamatis Markianos-Wright5-29/+21
2023-08-31Refactor vector HF/BF mode iterators and patterns.liuhongt1-130/+108
2023-08-31RISC-V: Fix vsetvl pass ICELehua Ding2-1/+20
2023-08-31Add overflow API for plus minus mult on rangeJiufu Guo5-0/+154
2023-08-31Daily bump.GCC Administrator6-1/+321
2023-08-30analyzer: implement reference count checking for CPython plugin [PR107646]Eric Feng10-44/+550
2023-08-30Analyzer: include algorithm headerFrancois-Xavier Coudert1-0/+1
2023-08-30pru: Add cstore expansion patternsDimitar Dimitrov9-0/+126
2023-08-30c++: CWG 2359, wrong copy-init with designated init [PR91319]Marek Polacek2-0/+31
2023-08-30c++: disallow constinit on functions [PR111173]Marek Polacek2-0/+8
2023-08-30tree-optimization/111228 - fix testcaseRichard Biener1-1/+1
2023-08-30test: Add xfail into slp-reduc-7.c for RVV VLA vectorizationJuzhe-Zhong1-1/+1
2023-08-30test: Adapt slp-26.c check for RVVJuzhe-Zhong1-4/+4
2023-08-30fortran: Restore interface to its previous state on error [PR48776]Mikael Morin4-6/+113
2023-08-30tree-optimization/111228 - combine two VEC_PERM_EXPRsRichard Biener2-3/+155
2023-08-30RISC-V: Remove movmisalign pattern for VLA modesJuzhe-Zhong1-11/+0
2023-08-30test: Fix XPASS of RVVJuzhe-Zhong6-6/+6
2023-08-30test: Add xfail for riscv_vectorJuzhe-Zhong3-3/+3
2023-08-30RISC-V: support cm.mva01s cm.mvsa01 in zcmpDie Li5-0/+85
2023-08-30RISC-V: support cm.popretz in zcmpFei Gao5-25/+509
2023-08-30RISC-V: support cm.push cm.pop cm.popret in zcmpFei Gao11-52/+2137
2023-08-30tree-ssa-strlen: Fix up handling of conditionally zero memcpy [PR110914]Jakub Jelinek2-1/+24
2023-08-30store-merging: Fix up >= 64 bit insertion [PR111015]Jakub Jelinek2-4/+33
2023-08-30middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LANES to ivopts/aliasJuzhe-Zhong2-0/+7
2023-08-30RISC-V: Make arch-24.c to test "success" caseTsukasa OI1-3/+1
2023-08-30RISC-V: Make sure we get VL REG operand for VLMAX vsetvlJuzhe-Zhong1-4/+12
2023-08-30RISC-V: Enable movmisalign for VLS modesJuzhe-Zhong3-5/+57
2023-08-30Daily bump.GCC Administrator8-1/+300
2023-08-29RISC-V: Use splitter to generate zicond in another casePhilipp Tomsich2-0/+45
2023-08-29analyzer: new warning: -Wanalyzer-overlapping-buffers [PR99860]David Malcolm11-2/+722
2023-08-29c++: tweaks for explicit conversion fns diagnosticMarek Polacek4-4/+77
2023-08-29RISC-V: Added zvfh support for zfa extensions.Jin Ma4-5/+104
2023-08-29RISC-V: generate builtin macro for compilation with strict alignmentEdwin Lu12-0/+144