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2023-04-21configure: Only create serdep.tmp if neededPeter Foley2-0/+4
2023-04-21gcc/m2: Drop references to $(P)Arsen Arsenović2-3/+3
2023-04-21Adjust x86 testsuite for recent if-conversion cost checkingJeff Law1-1/+4
2023-04-21aarch64: Emit single-instruction for smin (x, 0) and smax (x, 0)Kyrylo Tkachov3-15/+97
2023-04-21PR target/108779 aarch64: Implement -mtp= optionKyrylo Tkachov11-1/+94
2023-04-21aarch64: PR target/99195 Add scheme to optimise away vec_concat with zeroes o...Kyrylo Tkachov3-6/+87
2023-04-21c++, tree: optimize walk_tree_1 and cp_walk_subtreesPatrick Palka2-118/+119
2023-04-21 Add Ajit Kumar Agarwal to write after approval“ajit.kumar.agarwal@ibm.com”1-0/+1
2023-04-21Fix boostrap failure in tree-ssa-loop-ch.ccJan Hubicka1-7/+9
2023-04-21expansion: make layout of x_shift*cost[][][] more efficientVineet Gupta1-14/+13
2023-04-21MAINTAINERS: add Vineet Gupta to write after approvalVineet Gupta1-0/+1
2023-04-21[aarch64] Use force_reg instead of copy_to_mode_reg.Prathamesh Kulkarni1-6/+6
2023-04-21i386: Remove REG_OK_FOR_INDEX/REG_OK_FOR_BASE and their derivativesUros Bizjak3-50/+34
2023-04-21Fix latent bug in loop header copying which forgets to update the loop header...Jan Hubicka1-0/+13
2023-04-21Add safe_is_aRichard Biener1-0/+13
2023-04-21Add operator* to gimple_stmt_iterator and gphi_iteratorRichard Biener1-0/+4
2023-04-21Stabilize inlinerJan Hubicka1-13/+70
2023-04-21Cleanup odr_types_equivalent_pJan Hubicka1-6/+9
2023-04-21PR modula2/109586 cc1gm2 ICE when compiling large source files.Gaius Mulley1-2/+2
2023-04-21tree-optimization/109573 - avoid ICEing on unexpected live defRichard Biener2-3/+95
2023-04-21Use correct CFG orders for DF worklist processingRichard Biener1-16/+20
2023-04-21change inverted_post_order_compute to inverted_rev_post_order_computeRichard Biener6-44/+53
2023-04-21change DF to use the proper CFG order for DF_FORWARD problemsRichard Biener2-32/+34
2023-04-21RISC-V: Defer vsetvli insertion to later if possible [PR108270]Juzhe-Zhong5-3/+47
2023-04-21riscv: Fix <bitmanip_insn> fallout.Robin Dapp1-1/+1
2023-04-21rs6000: xfail float128 comparison test case that fails on powerpc64.Haochen Gui1-0/+1
2023-04-21testsuite: make ppc_cpu_supports_hw as effective target keyword [PR108728]Haochen Gui1-0/+1
2023-04-21Fix LCM dataflow CFG orderRichard Biener1-23/+24
2023-04-21LoongArch: Fix MUSL_DYNAMIC_LINKERPeng Fan1-1/+6
2023-04-21RISC-V: Add local user vsetvl instruction elimination [PR109547]Juzhe-Zhong4-3/+85
2023-04-21Daily bump.GCC Administrator6-1/+541
2023-04-20update_web_docs_git: Allow setting TEXI2*, add git build defaultArsen Arsenović1-3/+14
2023-04-20c++: simplify TEMPLATE_TYPE_PARM level loweringPatrick Palka1-21/+16
2023-04-20c++: use TREE_VEC for trailing args of variadic built-in traitsPatrick Palka6-28/+43
2023-04-20c++: make strip_typedefs generalize strip_typedefs_exprPatrick Palka1-59/+25
2023-04-20doc: Remove repeated word (typo)Alejandro Colomar1-1/+1
2023-04-20Do not ignore UNDEFINED ranges when determining PHI equivalences.Andrew MacLeod5-10/+117
2023-04-20tree-vect-patterns: One small vect_recog_ctz_ffs_pattern tweak [PR109011]Jakub Jelinek1-1/+1
2023-04-20c: Avoid -Wenum-int-mismatch warning for redeclaration of builtin acc_on_devi...Jakub Jelinek2-1/+31
2023-04-20[LRA]: Exclude some hard regs for multi-reg inout reload pseudos used in asm ...Vladimir N. Makarov1-0/+28
2023-04-20arch: Use VIRTUAL_REGISTER_P predicate.Uros Bizjak7-20/+11
2023-04-20i386: Handle sign-extract for QImode operations with high registers [PR78952]Uros Bizjak3-186/+237
2023-04-20[PR target/108248] [RISC-V] Break down some bitmanip insn typesRaphael Zinsly3-6/+8
2023-04-20RISC-V: Fix RVV register orderJuzhe-Zhong4-31/+50
2023-04-20RISC-V: Fix riscv/arch-19.c with different ISA spec versionKito Cheng1-2/+2
2023-04-20RISC-V: Fix wrong check of register occurrences [PR109535]Ju-Zhe Zhong3-1/+168
2023-04-20RISC-V: Fix simplify_ior_optimization.c on rv32Kito Cheng1-1/+1
2023-04-20amdgcn: bug fix ldexp insnAndrew Stubbs1-16/+9
2023-04-20amdgcn: update target-supports.expAndrew Stubbs1-5/+10
2023-04-20tree: Add 3+ argument fndecl_built_in_pJakub Jelinek10-33/+48