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2023-11-20testsuite: arm: fix arm_movt cut&pastoAlexandre Oliva1-1/+1
I got spurious fails of tests that required arm_thumb1_movt_ok on a target cpu that did not support movt. Looking into it, I found the arm_movt property to have been cut&pasted into other procs that checked for different properties. They shouldn't share the same test results cache entry, so I'm changing their prop names. Or rather its prop name, because the other occurrence was already fixed recently. for gcc/testsuite/ChangeLog * lib/target-supports.exp (check_effective_target_arm_thumb1_cbz_ok): Fix prop name cut&pasto.
2023-11-20testsuite: analyzer: expect alignment warning with -fshort-enumsAlexandre Oliva2-2/+2
On targets that have -fshort-enums enabled by default, the type casts in the pr108251 analyzer tests warn that the byte-aligned enums may not be sufficiently aligned to be a struct connection *. The function can't know better, the warning is reasonable, the code doesn't expected enums to be shorter and less aligned than the struct. Rather than use -fno-short-enums, I decided to embrace the warning on targets that have short_enums enabled by default. However, C++ doesn't issue the warning, because even with -fshort-enums, enumeration types are not TYPE_PACKED, and the expression is not sufficiently simplified by the C++ front-end for check_and_warn_address_or_pointer_of_packed_member to identify the insufficiently aligned pointer. So don't expect the warning there. for gcc/testsuite/ChangeLog * c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early-O2.c: Expect "unaligned pointer value" warning on short_enums targets, but not in c++. * c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c: Likewise.
2023-11-20testsuite: scev: expect fail on ilp32Alexandre Oliva3-3/+6
I've recently patched scev-3.c and scev-5.c because it only passed by accident on ia32. It also fails on some (but not all) arm-eabi variants. It seems hard to characterize the conditions in which the optimization is supposed to pass, but expecting them to fail on ilp32 targets, though probably a little excessive and possibly noisy, is not quite as alarming as getting a fail in test reports, so I propose changing the xfail marker from ia32 to ilp32. I'm also proposing to add a similar marker to scev-4.c. Though it doesn't appear to be failing for me, I've got reports that suggest it still does for others, and it certainly did for us as well. for gcc/testsuite/ChangeLog * gcc.dg/tree-ssa/scev-3.c: xfail on all ilp32 targets, though some of these do pass. * gcc.dg/tree-ssa/scev-4.c: Likewise. * gcc.dg/tree-ssa/scev-5.c: Likewise.
2023-11-20Initial support for AVX10.1Haochen Jiang36-18/+579
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Add avx10_set and version and detect avx10.1. (cpu_indicator_init): Handle avx10.1-512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_1_256_SET): New. (OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1. (ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512. Add indicator for explicit no-avx512 and no-avx10.1 options. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for AVX10_1_256 and AVX10_1_512. * config/i386/cpuid.h (bit_AVX10): New. (bit_AVX10_256): Ditto. (bit_AVX10_512): Ditto. * config/i386/driver-i386.cc (check_avx10_avx512_features): New. (host_detect_local_cpu): Do not append "-mno-" options under specific scenarios to avoid emitting a warning. * config/i386/i386-isa.def (EVEX512): Add DEF_PTA(EVEX512). (AVX10_1_256): Add DEF_PTA(AVX10_1_256). (AVX10_1_512): Add DEF_PTA(AVX10_1_512). * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and -mavx10.1-512. (ix86_function_specific_save): Save explicit no indicator. (ix86_function_specific_restore): Restore explicit no indicator. (ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and avx10.1-512. (ix86_valid_target_attribute_tree): Handle avx512 function attributes with avx10.1 command line option. (ix86_option_override_internal): Handle AVX10.1 options. * config/i386/i386.h: Add PTA_EVEX512 for AVX512 target machines. * config/i386/i386.opt: Add variable ix86_no_avx512_explicit and ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512. * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256 and avx10.1-512. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-1.c: New test. * gcc.target/i386/avx10_1-10.c: Ditto. * gcc.target/i386/avx10_1-11.c: Ditto. * gcc.target/i386/avx10_1-12.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. * gcc.target/i386/avx10_1-15.c: Ditto. * gcc.target/i386/avx10_1-16.c: Ditto. * gcc.target/i386/avx10_1-17.c: Ditto. * gcc.target/i386/avx10_1-18.c: Ditto. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-2.c: Ditto. * gcc.target/i386/avx10_1-20.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-4.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-7.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/avx10_1-9.c: Ditto.
2023-11-19c++: compare one level of template parmsJason Merrill1-57/+33
There should never be a reason to compare more than one level of template parameters; additional levels are for the enclosing context, which is either irrelevant (for a template template parameter) or already compared (for a member template). Also, the comp_template_parms handling of type parameters was wrongly checking for TEMPLATE_TYPE_PARM when a type parameter appears here as a TYPE_DECL. gcc/cp/ChangeLog: * pt.cc (comp_template_parms): Just one level. (template_parameter_lists_equivalent_p): Likewise.
2023-11-19c++: add DECL_IMPLICIT_TEMPLATE_PARM_P macroJason Merrill4-3/+23
Let's use a more informative name instead of DECL_VIRTUAL_P directly. gcc/cp/ChangeLog: * cp-tree.h (DECL_TEMPLATE_PARM_CHECK): New. (DECL_IMPLICIT_TEMPLATE_PARM_P): New. (decl_template_parm_check): New. * mangle.cc (write_closure_template_head): Use it. * parser.cc (synthesize_implicit_template_parm): Likewise. * pt.cc (template_parameters_equivalent_p): Likewise.
2023-11-20Add i?86-*-* and x86_64-*-* to vect_logical_reducliuhongt1-1/+2
x86 backend support reduc_{and,ior,xor>_scal_m for vector integer modes. gcc/testsuite/ChangeLog: * lib/target-supports.exp (vect_logical_reduc): Add i?86-*-* and x86_64-*-*.
2023-11-20Support reduc_{plus,xor,and,ior}_scal_m for vector integer mode.liuhongt3-3/+199
BB vectorizer relies on the backend support of .REDUC_{PLUS,IOR,XOR,AND} to vectorize reduction. gcc/ChangeLog: PR target/112325 * config/i386/sse.md (reduc_<code>_scal_<mode>): New expander. (REDUC_ANY_LOGIC_MODE): New iterator. (REDUC_PLUS_MODE): Extend to VxHI/SI/DImode. (REDUC_SSE_PLUS_MODE): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr112325-1.c: New test. * gcc.target/i386/pr112325-2.c: New test.
2023-11-20RISC-V: Implement -mmemcpy-strategy= options[PR112537]xuli9-1/+80
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537 -mmemcpy-strategy=[auto|libcall|scalar|vector] auto: Current status, use scalar or vector instructions. libcall: Always use a library call. scalar: Only use scalar instructions. vector: Only use vector instructions. PR target/112537 gcc/ChangeLog: * config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum): Strategy enum. * config/riscv/riscv-string.cc (riscv_expand_block_move): Disabled based on options. (expand_block_move): Ditto. * config/riscv/riscv.opt: Add -mmemcpy-strategy=. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/cpymem-strategy-1.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy-2.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy-5.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy.h: New test.
2023-11-20LoongArch: Modify MUSL_DYNAMIC_LINKER.Lulu Cheng1-3/+3
Use no suffix at all in the musl dynamic linker name for hard float ABI. Use -sf and -sp suffixes in musl dynamic linker name for soft float and single precision ABIs. The following table outlines the musl interpreter names for the LoongArch64 ABI names. musl interpreter | LoongArch64 ABI --------------------------- | ----------------- ld-musl-loongarch64.so.1 | loongarch64-lp64d ld-musl-loongarch64-sp.so.1 | loongarch64-lp64f ld-musl-loongarch64-sf.so.1 | loongarch64-lp64s gcc/ChangeLog: * config/loongarch/gnu-user.h (MUSL_ABI_SPEC): Modify suffix.
2023-11-20Daily bump.GCC Administrator9-1/+161
2023-11-20RISC-V: Optimize constant AVL for LRA patternJuzhe-Zhong2-3/+33
This optimization was discovered in the tuple move splitted bug fix patch. Before this patch: vsetivli zero,4,e16,mf2,ta,ma lhu a3,96(a5) vlseg8e16.v v1,(a5) lw a4,%lo(e)(a2) vsetvli a6,zero,e64,m2,ta,ma addi a0,a7,8 vse16.v v1,0(a7) vse16.v v2,0(a0) addi a0,a0,8 vse16.v v3,0(a0) addi a0,a0,8 vse16.v v4,0(a0) addi a0,a0,8 vse16.v v5,0(a0) addi a0,a0,8 vse16.v v6,0(a0) addi a0,a0,8 vse16.v v7,0(a0) addi a0,a0,8 vse16.v v8,0(a0) After this patch: vsetivli zero,4,e64,m2,ta,ma addi a0,a7,8 vlseg8e16.v v1,(a5) vse16.v v1,0(a7) vse16.v v2,0(a0) addi a0,a0,8 vse16.v v3,0(a0) addi a0,a0,8 vse16.v v4,0(a0) addi a0,a0,8 vse16.v v5,0(a0) addi a0,a0,8 vse16.v v6,0(a0) addi a0,a0,8 vse16.v v7,0(a0) addi a0,a0,8 vse16.v v8,0(a0) gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Optimize constant AVL. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/post-ra-avl.c: New test.
2023-11-19c++: Set DECL_CONTEXT for __cxa_thread_atexit [PR99187]Nathaniel Shead3-2/+27
Modules streaming requires DECL_CONTEXT to be set on declarations that are streamed. This ensures that __cxa_thread_atexit is given translation unit context much like is already done with many other support functions. PR c++/99187 gcc/cp/ChangeLog: * cp-tree.h (enum cp_tree_index): Add CPTI_THREAD_ATEXIT. (thread_atexit_node): New. * decl.cc (get_thread_atexit_node): Cache in thread_atexit_node. gcc/testsuite/ChangeLog: * g++.dg/modules/pr99187.C: New test. Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com> Signed-off-by: Nathan Sidwell <nathan@acm.org>
2023-11-19[committed] RISC-V: Infrastructure for instruction fusionPhilipp Tomsich3-35/+314
I've been meaning to extract this and upstream it for a long time. The work is primarily Philipp from VRULL with one case added by Raphael and light bugfixing on my part. Essentially there's 10 distinct fusions supported and they can be selected individually by building a suitable mask in the uarch tuning structure. Additional cases can be added -- the bulk of the effort is in recognizing the two fusible instructions. The cases supported in this patch are all from the Veyron V1 processor, though the hope is they will be useful elsewhere. I would encourage those familiar with other uarch implementations to enable fusion cases for those uarchs and extend the set of supported cases if any are missing. gcc/ * config/riscv/riscv-protos.h (extract_base_offset_in_addr): Prototype. * config/riscv/riscv.cc (riscv_fusion_pairs): New enum. (riscv_tune_param): Add fusible_ops field. (riscv_tune_param_rocket_tune_info): Initialize new field. (riscv_tune_param_sifive_7_tune_info): Likewise. (thead_c906_tune_info): Likewise. (generic_oo_tune_info): Likewise. (optimize_size_tune_info): Likewise. (riscv_macro_fusion_p): New function. (riscv_fusion_enabled_p): Likewise. (riscv_macro_fusion_pair_p): Likewise. (TARGET_SCHED_MACRO_FUSION_P): Define. (TARGET_SCHED_MACRO_FUSION_PAIR_P): Likewise. (extract_base_offset_in_addr): Moved into riscv.cc from... * config/riscv/thead.cc: Here. Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com> Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
2023-11-19[committed] Fix missing mode on a few unspec/unspec_volatile operandsJeff Law5-11/+11
This is fix for a minor problem Jivan and I found while testing the ext-dce work originally from Joern. The ext-dce pass will transform zero/sign extensions into subreg accesses when the upper bits are actually unused. So it's more likely with the ext-dce work to get a sequence like this prior to combine: > >> (insn 10 9 11 2 (set (reg:SI 144) >> (unspec_volatile [ >> (const_int 0 [0]) >> ] UNSPECV_FRFLAGS)) "j.c":11:3 discrim 1 362 {riscv_frflags} >> (nil)) >> (insn 11 10 55 2 (set (reg:DI 140 [ _12 ]) >> (subreg:DI (reg:SI 144) 0)) "j.c":11:3 discrim 1 206 {*movdi_64bit} >> (expr_list:REG_DEAD (reg:SI 144) >> (nil))) When we try to combine insn 10->11 we'll ultimately call simplify_subreg with something like (subreg:DI (unspec_volatile [...]) 0) Note the lack of a mode on the unspec_volatile. That in turn will cause simplify_subreg to trigger an assertion. The modeless unspec is generated by the RISC-V backend and the more I've pondered this issue over the last few days the more I'm convinced it's a backend bug. Basically if the LHS of the set has a mode, then the RHS of the set should have a mode as well. I've audited the various backends and only found a few problems which are fixed by this patch. I've tested the relevant ports in my tester. c6x, sh, mips and s390[x]. There are other patterns that are potentially problematical in various ports. They have a REG destination and an UNSPEC source, but the REG has no mode in the pattern. Since it wasn't clear what mode to give the UNSPEC, I left those alone. gcc/ * config/c6x/c6x.md (mvilc): Add mode to UNSPEC source. * config/mips/mips.md (rdhwr_synci_step_<mode>): Likewise. * config/riscv/riscv.md (riscv_frcsr, riscv_frflags): Likewise. * config/s390/s390.md (@split_stack_call<mode>): Likewise. (@split_stack_cond_call<mode>): Likewise. * config/sh/sh.md (sp_switch_1): Likewise.
2023-11-19testsuite: Don't use -mfloat128 with AIX.David Edelsohn1-3/+3
AIX doesn't support IEEE 128 floating point. Don't add the -mfloat128 on AIX. gcc/testsuite/ChangeLog: * lib/target-supports.exp (add_options_for___float128): Only add -mfloat128 to powerpc*-*-linux*. Signed-off-by: David Edelsohn <dje.gcc@gmail.com>
2023-11-19Makefile.tpl: Avoid race condition in generating site.exp from the top levelLewis Hyatt2-12/+28
A command like "make -j 2 check-gcc-c check-gcc-c++" run in the top level of a fresh build directory does not work reliably. That will spawn two independent make processes inside the "gcc" directory, and each of those will attempt to create site.exp if it doesn't exist and will interfere with each other, producing often a corrupted or empty site.exp. Resolve that by making these targets depend on a new phony target which makes sure site.exp is created first before starting the recursive makes. ChangeLog: * Makefile.in: Regenerate. * Makefile.tpl: Add dependency on site.exp to check-gcc-* targets
2023-11-19libcpp: split decls out to rich-location.hDavid Malcolm16-672/+713
The various decls relating to rich_location are in libcpp/include/line-map.h, but they don't relate to line maps. Split them out to their own header: libcpp/include/rich-location.h No functional change intended. gcc/ChangeLog: * Makefile.in (CPPLIB_H): Add libcpp/include/rich-location.h. * coretypes.h (class rich_location): New forward decl. gcc/analyzer/ChangeLog: * analyzer.h: Include "rich-location.h". gcc/c-family/ChangeLog: * c-lex.cc: Include "rich-location.h". gcc/cp/ChangeLog: * mapper-client.cc: Include "rich-location.h". gcc/ChangeLog: * diagnostic.h: Include "rich-location.h". * edit-context.h (class fixit_hint): New forward decl. * gcc-rich-location.h: Include "rich-location.h". * genmatch.cc: Likewise. * pretty-print.h: Likewise. gcc/rust/ChangeLog: * rust-location.h: Include "rich-location.h". libcpp/ChangeLog: * Makefile.in (TAGS_SOURCES): Add "include/rich-location.h". * include/cpplib.h (class rich_location): New forward decl. * include/line-map.h (class range_label) (enum range_display_kind, struct location_range) (class semi_embedded_vec, class rich_location, class label_text) (class range_label, class fixit_hint): Move to... * include/rich-location.h: ...this new file. * internal.h: Include "rich-location.h". Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-11-19RISC-V: Fix bug of tuple move splitterJuzhe-Zhong2-0/+20
PR target/112561 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_tuple_move): Fix bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112561.c: New test.
2023-11-18analyzer: new warning: -Wanalyzer-undefined-behavior-strtok [PR107573]David Malcolm19-17/+619
This patch: - adds support to the analyzer for tracking API-private state or which we don't have a decl (such as strtok's internal state), - uses it to implement a new -Wanalyzer-undefined-behavior-strtok which warns when strtok (NULL, delim) is called as the first call to strtok after main. gcc/analyzer/ChangeLog: PR analyzer/107573 * analyzer.h (register_known_functions): Add region_model_manager param. * analyzer.opt (Wanalyzer-undefined-behavior-strtok): New. * call-summary.cc (call_summary_replay::convert_region_from_summary_1): Handle RK_PRIVATE. * engine.cc (impl_run_checkers): Pass model manager to register_known_functions. * kf.cc (class undefined_function_behavior): New. (class kf_strtok): New. (register_known_functions): Add region_model_manager param. Use it to register "strtok". * region-model-manager.cc (region_model_manager::get_or_create_conjured_svalue): Add "idx" param. * region-model-manager.h (region_model_manager::get_or_create_conjured_svalue): Add "idx" param. (region_model_manager::get_root_region): New accessor. * region-model.cc (region_model::scan_for_null_terminator): Handle "expr" being null. (region_model::get_representative_path_var_1): Handle RK_PRIVATE. * region-model.h (region_model::called_from_main_p): Make public. * region.cc (region::get_memory_space): Handle RK_PRIVATE. (region::can_have_initial_svalue_p): Handle MEMSPACE_PRIVATE. (private_region::dump_to_pp): New. * region.h (MEMSPACE_PRIVATE): New. (RK_PRIVATE): New. (class private_region): New. (is_a_helper <const private_region *>::test): New. * store.cc (store::replay_call_summary_cluster): Handle RK_PRIVATE. * svalue.h (struct conjured_svalue::key_t): Add "idx" param to ctor and "m_idx" field. (class conjured_svalue::conjured_svalue): Likewise. gcc/ChangeLog: PR analyzer/107573 * doc/invoke.texi: Add -Wanalyzer-undefined-behavior-strtok. gcc/testsuite/ChangeLog: PR analyzer/107573 * c-c++-common/analyzer/strtok-1.c: New test. * c-c++-common/analyzer/strtok-2.c: New test. * c-c++-common/analyzer/strtok-3.c: New test. * c-c++-common/analyzer/strtok-4.c: New test. * c-c++-common/analyzer/strtok-cppreference.c: New test. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-11-19Daily bump.GCC Administrator9-1/+448
2023-11-18MAINTAINERS: Update my email address.Petter Tomner1-2/+2
Update my email address in the MAINTAINERS file. 2023-11-18 Petter Tomner <tomner@bahnhof.se> ChangeLog: * MAINTAINERS: Update my email address.
2023-11-18libstdc++: Check string value_type in std::make_format_args [PR112607]Jonathan Wakely2-4/+38
libstdc++-v3/ChangeLog: PR libstdc++/112607 * include/std/format (basic_format_arg::_S_to_arg_type): Check value_type for basic_string_view and basic_string specializations. * testsuite/std/format/arguments/112607.cc: New test.
2023-11-18libstdc++: Add fast path for std::format("{}", x) [PR110801]Jonathan Wakely1-1/+163
This optimizes the simple case of formatting a single string, integer or bool, with no format-specifier (so no padding, alignment, alternate form etc.) libstdc++-v3/ChangeLog: PR libstdc++/110801 * include/std/format (_Sink_iter::_M_reserve): New member function. (_Sink::_Reservation): New nested class. (_Sink::_M_reserve, _Sink::_M_bump): New virtual functions. (_Seq_sink::_M_reserve, _Seq_sink::_M_bump): New virtual overrides. (_Iter_sink<O, ContigIter>::_M_reserve): Likewise. (__do_vformat_to): Use new functions to optimize "{}" case.
2023-11-19LoongArch: Fix "-mexplict-relocs=none -mcmodel=medium" producing %call36 ↵Xi Ruoyao1-4/+2
when the assembler does not support it Even if !HAVE_AS_SUPPORT_CALL36, const_call_insn_operand should still return false when -mexplict-relocs=none -mcmodel=medium to make loongarch_legitimize_call_address emit la.local or la.global. gcc/ChangeLog: * config/loongarch/predicates.md (const_call_insn_operand): Remove buggy "HAVE_AS_SUPPORT_CALL36" conditions. Change "1" to "true" to make the coding style consistent.
2023-11-19LoongArch: Add fine-grained control for LAM_BH and LAMCASXi Ruoyao7-10/+27
gcc/ChangeLog: * config/loongarch/genopts/isa-evolution.in: (lam-bh, lamcas): Add. * config/loongarch/loongarch-str.h: Regenerate. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch-cpucfg-map.h: Regenerate. * config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Include OPTION_MASK_ISA_LAM_BH and OPTION_MASK_ISA_LAMCAS. * config/loongarch/sync.md (atomic_add<mode:SHORT>): Use TARGET_LAM_BH instead of ISA_BASE_IS_LA64V110. Remove empty lines from assembly output. (atomic_exchange<mode>_short): Likewise. (atomic_exchange<mode:SHORT>): Likewise. (atomic_fetch_add<mode>_short): Likewise. (atomic_fetch_add<mode:SHORT>): Likewise. (atomic_cas_value_strong<mode>_amcas): Use TARGET_LAMCAS instead of ISA_BASE_IS_LA64V110. (atomic_compare_and_swap<mode>): Likewise. (atomic_compare_and_swap<mode:GPR>): Likewise. (atomic_compare_and_swap<mode:SHORT>): Likewise. * config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump status if -mlam-bh and -mlamcas if -fverbose-asm.
2023-11-19LoongArch: Don't emit dbar 0x700 if -mld-seq-saXi Ruoyao2-5/+6
This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that two loads on the same address won't be reordered with each other". Thus we can omit the "load-load" barrier dbar 0x700. This is only a micro-optimization because dbar 0x700 is already treated as nop if the hardware supports LD_SEQ_SA. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_print_operand): Don't print dbar 0x700 if TARGET_LD_SEQ_SA. * config/loongarch/sync.md (atomic_load<mode>): Likewise.
2023-11-19LoongArch: Take the advantage of -mdiv32 if it's enabledXi Ruoyao3-5/+68
With -mdiv32, we can assume div.w[u] and mod.w[u] works on low 32 bits of a 64-bit GPR even if it's not sign-extended. gcc/ChangeLog: * config/loongarch/loongarch.md (DIV): New mode iterator. (<optab:ANY_DIV><mode:GPR>3): Don't expand if TARGET_DIV32. (<optab:ANY_DIV>di3_fake): Disable if TARGET_DIV32. (*<optab:ANY_DIV><mode:GPR>3): Allow SImode if TARGET_DIV32. (<optab:ANY_DIV>si3_extended): New insn if TARGET_DIV32. gcc/testsuite/ChangeLog: * gcc.target/loongarch/div-div32.c: New test. * gcc.target/loongarch/div-no-div32.c: New test.
2023-11-19LoongArch: Add evolution features of base ISA revisionsXi Ruoyao3-18/+52
* config/loongarch/loongarch-def.h: (loongarch_isa_base_features): Declare. Define it in ... * config/loongarch/loongarch-cpu.cc (loongarch_isa_base_features): ... here. (fill_native_cpu_config): If we know the base ISA of the CPU model from PRID, use it instead of la64 (v1.0). Check if all expected features of this base ISA is available, emit a warning if not. * config/loongarch/loongarch-opts.cc (config_target_isa): Enable the features implied by the base ISA if not -march=native.
2023-11-19LoongArch: genopts: Add infrastructure to generate code for new features in ↵Xi Ruoyao10-36/+245
ISA evolution LoongArch v1.10 introduced the concept of ISA evolution. During ISA evolution, many independent features can be added and enumerated via CPUCFG. Add a data file into genopts storing the CPUCFG word, bit, the name of the command line option controlling if this feature should be used for compilation, and the text description. Make genstr.sh process these info and add the command line options into loongarch.opt and loongarch-str.h, and generate a new file loongarch-cpucfg-map.h for mapping CPUCFG output to the corresponding option. When handling -march=native, use the information in loongarch-cpucfg-map.h to generate the corresponding option mask. Enable the features implied by -march setting unless the user has explicitly disabled the feature. The added options (-mdiv32 and -mld-seq-sa) are not really handled yet. They'll be used in the following patches. gcc/ChangeLog: * config/loongarch/genopts/isa-evolution.in: New data file. * config/loongarch/genopts/genstr.sh: Translate info in isa-evolution.in when generating loongarch-str.h, loongarch.opt, and loongarch-cpucfg-map.h. * config/loongarch/genopts/loongarch.opt.in (isa_evolution): New variable. * config/loongarch/t-loongarch: (loongarch-cpucfg-map.h): New rule. (loongarch-str.h): Depend on isa-evolution.in. (loongarch.opt): Depend on isa-evolution.in. (loongarch-cpu.o): Depend on loongarch-cpucfg-map.h. * config/loongarch/loongarch-str.h: Regenerate. * config/loongarch/loongarch-def.h (loongarch_isa): Add field for evolution features. Add helper function to enable features in this field. Probe native CPU capability and save the corresponding options into preset. * config/loongarch/loongarch-cpu.cc (fill_native_cpu_config): Probe native CPU capability and save the corresponding options into preset. (cache_cpucfg): Simplify with C++11-style for loop. (cpucfg_useful_idx, N_CPUCFG_WORDS): Move to ... * config/loongarch/loongarch.cc (loongarch_option_override_internal): Enable the ISA evolution feature options implied by -march and not explicitly disabled. (loongarch_asm_code_end): New function, print ISA information as comments in the assembly if -fverbose-asm. It makes easier to debug things like -march=native. (TARGET_ASM_CODE_END): Define. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch-cpucfg-map.h: Generate. (cpucfg_useful_idx, N_CPUCFG_WORDS) ... here.
2023-11-19LoongArch: Fix internal error running "gcc -march=native" on LA664Xi Ruoyao5-0/+9
On LA664, the PRID preset is ISA_BASE_LA64V110 but the base architecture is guessed ISA_BASE_LA64V100. This causes a warning to be outputed: cc1: warning: base architecture 'la64' differs from PRID preset '?' But we've not set the "?" above in loongarch_isa_base_strings, thus it's a nullptr and then an ICE is triggered. Add ISA_BASE_LA64V110 to genopts and initialize loongarch_isa_base_strings[ISA_BASE_LA64V110] correctly to fix the ICE. The warning itself will be fixed later. gcc/ChangeLog: * config/loongarch/genopts/loongarch-strings: (STR_ISA_BASE_LA64V110): Add. * config/loongarch/genopts/loongarch.opt.in: (ISA_BASE_LA64V110): Add. * config/loongarch/loongarch-def.c (loongarch_isa_base_strings): Initialize [ISA_BASE_LA64V110] to STR_ISA_BASE_LA64V110. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch-str.h: Regenerate.
2023-11-18gcov: Improve -fprofile-update=atomicSebastian Huber4-16/+114
The code coverage support uses counters to determine which edges in the control flow graph were executed. If a counter overflows, then the code coverage information is invalid. Therefore the counter type should be a 64-bit integer. In multi-threaded applications, it is important that the counter increments are atomic. This is not the case by default. The user can enable atomic counter increments through the -fprofile-update=atomic and -fprofile-update=prefer-atomic options. If the target supports 64-bit atomic operations, then everything is fine. If not and -fprofile-update=prefer-atomic was chosen by the user, then non-atomic counter increments will be used. However, if the target does not support the required atomic operations and -fprofile-atomic=update was chosen by the user, then a warning was issued and as a forced fallback to non-atomic operations was done. This is probably not what a user wants. There is still hardware on the market which does not have atomic operations and is used for multi-threaded applications. A user which selects -fprofile-update=atomic wants consistent code coverage data and not random data. This patch removes the fallback to non-atomic operations for -fprofile-update=atomic the target platform supports libatomic. To mitigate potential performance issues an optimization for systems which only support 32-bit atomic operations is provided. Here, the edge counter increments are done like this: low = __atomic_add_fetch_4 (&counter.low, 1, MEMMODEL_RELAXED); high_inc = low == 0 ? 1 : 0; __atomic_add_fetch_4 (&counter.high, high_inc, MEMMODEL_RELAXED); In gimple_gen_time_profiler() this split operation cannot be used, since the updated counter value is also required. Here, a library call is emitted. This is not a performance issue since the update is only done if counters[0] == 0. gcc/c-family/ChangeLog: * c-cppbuiltin.cc (c_cpp_builtins): Define __LIBGCC_HAVE_LIBATOMIC for libgcov. gcc/ChangeLog: * doc/invoke.texi (-fprofile-update): Clarify default method. Document the atomic method behaviour. * tree-profile.cc (enum counter_update_method): New. (counter_update): Likewise. (gen_counter_update): Use counter_update_method. Split the atomic counter update in two 32-bit atomic operations if necessary. (tree_profiling): Select counter_update_method. libgcc/ChangeLog: * libgcov.h (GCOV_SUPPORTS_ATOMIC): Always define it. Set it also to 1, if __LIBGCC_HAVE_LIBATOMIC is defined.
2023-11-18gcov: Add gen_counter_update()Sebastian Huber1-71/+62
Move the counter update to the new gen_counter_update() helper function. Use it in gimple_gen_edge_profiler() and gimple_gen_time_profiler(). The resulting gimple instructions should be identical with the exception of the removed unshare_expr() call. The unshare_expr() call was used in gimple_gen_edge_profiler(). gcc/ChangeLog: * tree-profile.cc (gen_assign_counter_update): New. (gen_counter_update): Likewise. (gimple_gen_edge_profiler): Use gen_counter_update(). (gimple_gen_time_profiler): Likewise.
2023-11-18Add TARGET_HAVE_LIBATOMICSebastian Huber4-0/+17
Add target data to indicate if libatomic is available. gcc/ChangeLog: * config/rtems.h (TARGET_HAVE_LIBATOMIC): Define. * doc/tm.texi: Regenerate. * doc/tm.texi.in (TARGET_HAVE_LIBATOMIC): Add. * target.def (have_libatomic): New.
2023-11-18gcov: Remove TARGET_GCOV_TYPE_SIZE target hookSebastian Huber10-53/+4
This reverts commit 8cdcea51c0fd753e6a652c9b236e91b3a6e0911c. gcc/c-family/ChangeLog: * c-cppbuiltin.cc (c_cpp_builtins): Do not define __LIBGCC_GCOV_TYPE_SIZE. gcc/ChangeLog: * config/sparc/rtemself.h (SPARC_GCOV_TYPE_SIZE): Remove. * config/sparc/sparc.cc (sparc_gcov_type_size): Likewise. (TARGET_GCOV_TYPE_SIZE): Likewise. * coverage.cc (get_gcov_type): Use LONG_LONG_TYPE_SIZE instead of removed target hook. * doc/tm.texi: Regenerate. * doc/tm.texi.in (TARGET_GCOV_TYPE_SIZE): Remove. * target.def: Likewise. * targhooks.cc (default_gcov_type_size): Likewise. * targhooks.h (default_gcov_type_size): Likewise. libgcc/ChangeLog: * libgcov.h (gcov_type): Use LONG_LONG_TYPE_SIZE. (gcov_type_unsigned): Likewise.
2023-11-18RISC-V: Fix mismatched new delete for unique_ptrKito Cheng1-3/+3
gcc/ChangeLog: * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Use char[] for std::unique_ptr to prevent mismatched new delete issue. (riscv_process_one_target_attr): Ditto. (riscv_process_target_attr): Ditto.
2023-11-18MAINTAINERS: Update my e-mail addressFrederik Harwath1-1/+1
* MAINTAINERS: Change my address.
2023-11-18RISC-V: Refactor RVV iterators[NFC]Juzhe-Zhong1-507/+94
This patch refactors RVV iteratros for easier maintain. E.g. (define_mode_iterator V [ RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") ]) change it into: (define_mode_iterator V [VI VF_ZVFHMIN]) gcc/ChangeLog: * config/riscv/vector-iterators.md: Refactor iterators.
2023-11-18Testsuite: remove unused variablesFrancois-Xavier Coudert2-2/+0
Missing from earlier commit, which removed the only use of those two variables. gcc/testsuite/ChangeLog: * gfortran.dg/coarray/caf.exp: Remove unused variable. * gfortran.dg/dg.exp: Remove unused variable.
2023-11-18libsanitizer: fix build on darwinFrancois-Xavier Coudert1-0/+2
Upstream report of the issue at https://github.com/llvm/llvm-project/issues/72639 libsanitizer/ChangeLog: * asan/asan_mac.cpp: Protect Apple blocks behind the MISSING_BLOCKS_SUPPORT macro.
2023-11-18LoongArch: atomic_load and atomic_store are implemented using dbar grading.Lulu Cheng1-5/+65
Because the la464 memory model design allows the same address load out of order, so in the following test example, the Load of 23 lines may be executed first over the load of 21 lines, resulting in an error. So when memmodel is MEMMODEL_RELAXED, the load instruction will be followed by "dbar 0x700" when implementing _atomic_load. 1 void * 2 gomp_ptrlock_get_slow (gomp_ptrlock_t *ptrlock) 3 { 4 int *intptr; 5 uintptr_t oldval = 1; 6 7 __atomic_compare_exchange_n (ptrlock, &oldval, 2, false, 8 MEMMODEL_RELAXED, MEMMODEL_RELAXED); 9 10 /* futex works on ints, not pointers. 11 But a valid work share pointer will be at least 12 8 byte aligned, so it is safe to assume the low 13 32-bits of the pointer won't contain values 1 or 2. */ 14 __asm volatile ("" : "=r" (intptr) : "0" (ptrlock)); 15 #if __BYTE_ORDER == __BIG_ENDIAN 16 if (sizeof (*ptrlock) > sizeof (int)) 17 intptr += (sizeof (*ptrlock) / sizeof (int)) - 1; 18 #endif 19 do 20 do_wait (intptr, 2); 21 while (__atomic_load_n (intptr, MEMMODEL_RELAXED) == 2); 22 __asm volatile ("" : : : "memory"); 23 return (void *) __atomic_load_n (ptrlock, MEMMODEL_ACQUIRE); 24 } gcc/ChangeLog: * config/loongarch/sync.md (atomic_load<mode>): New template.
2023-11-18LoongArch: Implement atomic operations using LoongArch1.1 instructions.Lulu Cheng4-49/+147
1. short and char type calls for atomic_add_fetch and __atomic_fetch_add are implemented using amadd{_db}.{b/h}. 2. Use amcas{_db}.{b/h/w/d} to implement __atomic_compare_exchange_n and __atomic_compare_exchange. 3. The short and char types of the functions __atomic_exchange and __atomic_exchange_n are implemented using amswap{_db}.{b/h}. gcc/ChangeLog: * config/loongarch/loongarch-def.h: Add comments. * config/loongarch/loongarch-opts.h (ISA_BASE_IS_LA64V110): Define macro. * config/loongarch/loongarch.cc (loongarch_memmodel_needs_rel_acq_fence): Remove redundant code implementations. * config/loongarch/sync.md (d): Added QI, HI support. (atomic_add<mode>): New template. (atomic_exchange<mode>_short): Likewise. (atomic_cas_value_strong<mode>_amcas): Likewise.. (atomic_fetch_add<mode>_short): Likewise.
2023-11-18LoongArch: Add LA664 support.Lulu Cheng11-13/+51
Define ISA_BASE_LA64V110, which represents the base instruction set defined in LoongArch1.1. Support the configure setting --with-arch =la664, and support -march=la664,-mtune=la664. gcc/ChangeLog: * config.gcc: Support LA664. * config/loongarch/genopts/loongarch-strings: Likewise. * config/loongarch/genopts/loongarch.opt.in: Likewise. * config/loongarch/loongarch-cpu.cc (fill_native_cpu_config): Likewise. * config/loongarch/loongarch-def.c: Likewise. * config/loongarch/loongarch-def.h (N_ISA_BASE_TYPES): Likewise. (ISA_BASE_LA64V110): Define macro. (N_ARCH_TYPES): Update value. (N_TUNE_TYPES): Update value. (CPU_LA664): New macro. * config/loongarch/loongarch-opts.cc (isa_default_abi): Likewise. (isa_base_compat_p): Likewise. * config/loongarch/loongarch-opts.h (TARGET_64BIT): This parameter is enabled when la_target.isa.base is equal to ISA_BASE_LA64V100 or ISA_BASE_LA64V110. (TARGET_uARCH_LA664): Define macro. * config/loongarch/loongarch-str.h (STR_CPU_LA664): Likewise. * config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width): Add LA664 support. * config/loongarch/loongarch.opt: Regenerate.
2023-11-18LoongArch: Add code generation support for call36 function calls.Lulu Cheng14-36/+268
When compiling with '-mcmodel=medium', the function call is made through 'pcaddu18i+jirl' if binutils supports call36, otherwise the native implementation 'pcalau12i+jirl' is used. gcc/ChangeLog: * config.in: Regenerate. * config/loongarch/loongarch-opts.h (HAVE_AS_SUPPORT_CALL36): Define macro. * config/loongarch/loongarch.cc (loongarch_legitimize_call_address): If binutils supports call36, the function call is not split over expand. * config/loongarch/loongarch.md: Add call36 generation code. * config/loongarch/predicates.md: Likewise. * configure: Regenerate. * configure.ac: Check whether binutils supports call36. gcc/testsuite/ChangeLog: * gcc.target/loongarch/func-call-medium-5.c: If the assembler supports call36, the test is abandoned. * gcc.target/loongarch/func-call-medium-6.c: Likewise. * gcc.target/loongarch/func-call-medium-7.c: Likewise. * gcc.target/loongarch/func-call-medium-8.c: Likewise. * lib/target-supports.exp: Added a function to see if the assembler supports the call36 relocation. * gcc.target/loongarch/func-call-medium-call36-1.c: New test. * gcc.target/loongarch/func-call-medium-call36.c: New test. Co-authored-by: Xi Ruoyao <xry111@xry111.site>
2023-11-17analyzer: new warning: -Wanalyzer-infinite-loop [PR106147]David Malcolm38-86/+1547
This patch implements a new analyzer warning: -Wanalyzer-infinite-loop. It works by examining the exploded graph once the latter has been fully built. It attempts to detect cycles in the exploded graph in which: - no externally visible work occurs - no escape is possible from the cycle once it has been entered - the program state is "sufficiently concrete" at each step: - no unknown activity could be occurring - the worklist was fully drained for each enode in the cycle i.e. every enode in the cycle is processed For example, it correctly complains about this bogus "for" loop: int sum = 0; for (struct node *iter = n; iter; iter->next) sum += n->val; return sum; like this: infinite-loop-linked-list.c: In function ‘for_loop_noop_next’: infinite-loop-linked-list.c:110:31: warning: infinite loop [CWE-835] [-Wanalyzer-infinite-loop] 110 | for (struct node *iter = n; iter; iter->next) | ^~~~ ‘for_loop_noop_next’: events 1-5 | | 110 | for (struct node *iter = n; iter; iter->next) | | ^~~~ | | | | | (1) infinite loop here | | (2) when ‘iter’ is non-NULL: always following ‘true’ branch... | | (5) ...to here | 111 | sum += n->val; | | ~~~~~~~~~~~~~ | | | | | | | (3) ...to here | | (4) looping back... | gcc/ChangeLog: PR analyzer/106147 * Makefile.in (ANALYZER_OBJS): Add analyzer/infinite-loop.o. * doc/invoke.texi: Add -fdump-analyzer-infinite-loop and -Wanalyzer-infinite-loop. Add missing CWE link for -Wanalyzer-infinite-recursion. * timevar.def (TV_ANALYZER_INFINITE_LOOPS): New. gcc/analyzer/ChangeLog: PR analyzer/106147 * analyzer.opt (Wanalyzer-infinite-loop): New option. (fdump-analyzer-infinite-loop): New option. * checker-event.h (start_cfg_edge_event::get_desc): Drop "final". (start_cfg_edge_event::maybe_describe_condition): Convert from private to protected. * checker-path.h (checker_path::get_logger): New. * diagnostic-manager.cc (process_worklist_item): Update for new context param of maybe_update_for_edge. * engine.cc (impl_region_model_context::impl_region_model_context): Add out_could_have_done_work param to both ctors and use it to initialize mm_out_could_have_done_work. (impl_region_model_context::maybe_did_work): New vfunc implementation. (exploded_node::on_stmt): Add out_could_have_done_work param and pass to ctxt ctor. (exploded_node::on_stmt_pre): Treat setjmp and longjmp as "doing work". (exploded_node::on_longjmp): Likewise. (exploded_edge::exploded_edge): Add "could_do_work" param and use it to initialize m_could_do_work_p. (exploded_edge::dump_dot_label): Add result of could_do_work_p. (exploded_graph::add_function_entry): Mark edge as doing no work. (exploded_graph::add_edge): Add "could_do_work" param and pass to exploded_edge ctor. (add_tainted_args_callback): Treat as doing no work. (exploded_graph::process_worklist): Likewise when merging nodes. (maybe_process_run_of_before_supernode_enodes::item): Likewise. (exploded_graph::maybe_create_dynamic_call): Likewise. (exploded_graph::process_node): Likewise for phi nodes. Pass in a "could_have_done_work" bool when handling stmts and use when creating edges. Assume work is done at bifurcation. (exploded_path::feasible_p): Update for new context param of maybe_update_for_edge. (feasibility_state::feasibility_state): New ctor. (feasibility_state::operator=): New. (feasibility_state::maybe_update_for_edge): Add ctxt param and use it. Fix missing newline when logging state. (impl_run_checkers): Call exploded_graph::detect_infinite_loops. * exploded-graph.h (impl_region_model_context::impl_region_model_context): Add out_could_have_done_work param to both ctors. (impl_region_model_context::maybe_did_work): New decl. (impl_region_model_context::checking_for_infinite_loop_p): New. (impl_region_model_context::on_unusable_in_infinite_loop): New. (impl_region_model_context::m_out_could_have_done_work): New field. (exploded_node::on_stmt): Add "out_could_have_done_work" param. (exploded_edge::exploded_edge): Add "could_do_work" param. (exploded_edge::could_do_work_p): New accessor. (exploded_edge::m_could_do_work_p): New field. (exploded_graph::add_edge): Add "could_do_work" param. (exploded_graph::detect_infinite_loops): New decl. (feasibility_state::feasibility_state): New ctor. (feasibility_state::operator=): New decl. (feasibility_state::maybe_update_for_edge): Add ctxt param. * infinite-loop.cc: New file. * program-state.cc (program_state::on_edge): Log the rejected constraint when region_model::maybe_update_for_edge fails. * region-model.cc (region_model::on_assignment): Treat any writes other than to the stack as "doing work". (region_model::on_stmt_pre): Treat all asm stmts as "doing work". (region_model::on_call_post): Likewise for all calls to functions with unknown side effects. (region_model::handle_phi): Add svals_changing_meaning param. Mark widening svalue in phi nodes as changing meaning. (unusable_in_infinite_loop_constraint_p): New. (region_model::add_constraint): If we're checking for an infinite loop, bail out on unusable svalues, or if we don't have a definite true/false for the constraint. (region_model::update_for_phis): Gather all svalues changing meaning in phi nodes, and purge constraints involving them. (region_model::replay_call_summary): Treat all call summaries as doing work. (region_model::can_merge_with_p): Purge constraints involving svalues that change meaning. (model_merger::on_widening_reuse): New. (test_iteration_1): Likewise. (selftest::test_iteration_1): Remove assertion that model6 "knows" that i < 157. * region-model.h (region_model::handle_phi): Add svals_changing_meaning param (region_model_context::maybe_did_work): New pure virtual func. (region_model_context::checking_for_infinite_loop_p): Likewise. (region_model_context::on_unusable_in_infinite_loop): Likewise. (noop_region_model_context::maybe_did_work): Implement. (noop_region_model_context::checking_for_infinite_loop_p): Likewise. (noop_region_model_context::on_unusable_in_infinite_loop): Likewise. (region_model_context_decorator::maybe_did_work): Implement. (region_model_context_decorator::checking_for_infinite_loop_p): Likewise. (region_model_context_decorator::on_unusable_in_infinite_loop): Likewise. (model_merger::on_widening_reuse): New decl. (model_merger::m_svals_changing_meaning): New field. * sm-signal.cc (register_signal_handler::impl_transition): Assume the edge "does work". * supergraph.cc (supernode::get_start_location): Use CFG edge's goto_locus if available. (supernode::get_end_location): Likewise. (cfg_superedge::dump_label_to_pp): Dump edges with a "goto_locus" * supergraph.h (cfg_superedge::get_goto_locus): New. * svalue.cc (svalue::can_merge_p): Call on_widening_reuse for widening values. (involvement_visitor::visit_widening_svalue): New. (svalue::involves_p): Update assertion to allow widening svalues. gcc/testsuite/ChangeLog: PR analyzer/106147 * c-c++-common/analyzer/gzio-2.c: Add dg-warning for infinite loop, marked as xfail. * c-c++-common/analyzer/infinite-loop-2.c: New test. * c-c++-common/analyzer/infinite-loop-4.c: New test. * c-c++-common/analyzer/infinite-loop-crc32c.c: New test. * c-c++-common/analyzer/infinite-loop-doom-d_main-IdentifyVersion.c: New test. * c-c++-common/analyzer/infinite-loop-doom-v_video.c: New test. * c-c++-common/analyzer/infinite-loop-g_error.c: New test. * c-c++-common/analyzer/infinite-loop-linked-list.c: New test. * c-c++-common/analyzer/infinite-recursion-inlining.c: Add dg-warning directives for infinite loop. * c-c++-common/analyzer/inlining-4-multiline.c: Update expected paths for event 5 having a location. * gcc.dg/analyzer/boxed-malloc-1.c: Add dg-warning for infinite loop. * gcc.dg/analyzer/data-model-20.c: Likewise. Add comment about suspect code, and create... * gcc.dg/analyzer/data-model-20a.c: ...this new test by cleaning it up. * gcc.dg/analyzer/edges-1.c: Add a placeholder statement to avoid the "...to here" from the if stmt occurring at the "while", and thus being treated as a bogus event. * gcc.dg/analyzer/explode-2a.c: Add dg-warning for infinite loop. * gcc.dg/analyzer/infinite-loop-1.c: New test. * gcc.dg/analyzer/malloc-1.c: Add dg-warning for infinite loop. * gcc.dg/analyzer/out-of-bounds-coreutils.c: Add TODO. * gcc.dg/analyzer/paths-4.c: Add dg-warning for infinite loop. * gcc.dg/analyzer/pr103892.c: Likewise. * gcc.dg/analyzer/pr93546.c: Likewise. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-11-18Daily bump.GCC Administrator6-1/+245
2023-11-17vect: Pass truth type to vect_get_vec_defs.Robin Dapp3-9/+75
For conditional operations the mask is loop invariant and cannot be stored explicitly. By default, for reductions, we deduce the vectype from the statement or the loop but this does not work for conditional operations. Therefore this patch passes the truth type of the reduction input vectype for the mask operand instead. This will override the other choices and make sure we have the proper mask vectype. gcc/ChangeLog: PR middle-end/112406 PR middle-end/112552 * tree-vect-loop.cc (vect_transform_reduction): Pass truth vectype for mask operand. gcc/testsuite/ChangeLog: * gcc.target/aarch64/pr112406.c: New test. * gcc.target/riscv/rvv/autovec/pr112552.c: New test.
2023-11-17libstdc++: Regenerate config.h.inJonathan Wakely1-1/+1
libstdc++-v3/ChangeLog: * config.h.in: Regenerate.
2023-11-17libstdc++: Define C++26 saturation arithmetic functions (P0543R3)Jonathan Wakely12-0/+455
This was approved for C++26 last week at the WG21 meeting in Kona. libstdc++-v3/ChangeLog: * include/Makefile.am: Add new header. * include/Makefile.in: Regenerate. * include/bits/version.def (saturation_arithmetic): Define. * include/bits/version.h: Regenerate. * include/std/numeric: Include new header. * include/bits/sat_arith.h: New file. * testsuite/26_numerics/saturation/add.cc: New test. * testsuite/26_numerics/saturation/cast.cc: New test. * testsuite/26_numerics/saturation/div.cc: New test. * testsuite/26_numerics/saturation/mul.cc: New test. * testsuite/26_numerics/saturation/sub.cc: New test. * testsuite/26_numerics/saturation/version.cc: New test.
2023-11-17c++: Implement C++ DR 2406 - [[fallthrough]] attribute and iteration statementsJakub Jelinek5-9/+143
The following patch implements CWG 2406 - [[fallthrough]] attribute and iteration statements The genericization of some loops leaves nothing at all or just a label after a body of a loop, so if the loop is later followed by case or default label in a switch, the fallthrough statement isn't diagnosed. The following patch implements it by marking the IFN_FALLTHROUGH call in such a case, such that during gimplification it can be pedantically diagnosed even if it is followed by case or default label or some normal labels followed by case/default labels. While looking into this, I've discovered other problems. expand_FALLTHROUGH_r is removing the IFN_FALLTHROUGH calls from the IL, but wasn't telling that to walk_gimple_stmt/walk_gimple_seq_mod, so the callers would then skip the next statement after it, and it would return non-NULL if the removed stmt was last in the sequence. This could lead to wi->callback_result being set even if it didn't appear at the very end of switch sequence. The patch makes use of wi->removed_stmt such that the callers properly know what happened, and use different way to handle the end of switch sequence case. That change discovered a bug in the gimple-walk handling of wi->removed_stmt. If that flag is set, the callback is telling the callers that the current statement has been removed and so the innermost walk_gimple_seq_mod shouldn't gsi_next. The problem is that wi->removed_stmt is only reset at the start of a walk_gimple_stmt, but that can be too late for some cases. If we have two nested gimple sequences, say GIMPLE_BIND as the last stmt of some gimple seq, we remove the last statement inside of that GIMPLE_BIND, set wi->removed_stmt there, don't do gsi_next correctly because already gsi_remove moved us to the next stmt, there is no next stmt, so we return back to the caller, but wi->removed_stmt is still set and so we don't do gsi_next even in the outer sequence, despite the GIMPLE_BIND (etc.) not being removed. That means we walk the GIMPLE_BIND with its whole sequence again. The patch fixes that by resetting wi->removed_stmt after we've used that flag in walk_gimple_seq_mod. Nothing really uses that flag after the outermost walk_gimple_seq_mod, it is just a private notification that the stmt callback has removed a stmt. 2023-11-17 Jakub Jelinek <jakub@redhat.com> PR c++/107571 gcc/ * gimplify.cc (expand_FALLTHROUGH_r): Use wi->removed_stmt after gsi_remove, change the way of passing fallthrough stmt at the end of sequence to expand_FALLTHROUGH. Diagnose IFN_FALLTHROUGH with GF_CALL_NOTHROW flag. (expand_FALLTHROUGH): Change loc into array of 2 location_t elts, don't test wi.callback_result, instead check whether first elt is not UNKNOWN_LOCATION and in that case pedwarn with the second location. * gimple-walk.cc (walk_gimple_seq_mod): Clear wi->removed_stmt after the flag has been used. * internal-fn.def (FALLTHROUGH): Mention in comment the special meaning of the TREE_NOTHROW/GF_CALL_NOTHROW flag on the calls. gcc/c-family/ * c-gimplify.cc (genericize_c_loop): For C++ mark IFN_FALLTHROUGH call at the end of loop body as TREE_NOTHROW. gcc/testsuite/ * g++.dg/DRs/dr2406.C: New test.
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