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2020-02-12real: Fix roundeven on inf/nan [PR93663]Jakub Jelinek4-14/+29
As can be seen in the testcase, roundeven with inf or nan arguments ICE because of those asserts where nothing prevents from is_halfway_below being called with those arguments. The following patch fixes that by just returning false for rvc_inf/rvc_nan like it returns for rvc_zero, so that we handle roundeven with all those values as round. Inf/NaN are not halfway in between two integers... 2020-02-12 Jakub Jelinek <jakub@redhat.com> PR middle-end/93663 * real.c (is_even): Make static. Function comment fix. (is_halfway_below): Make static, don't assert R is not inf/nan, instead return false for those. Small formatting fixes. * gcc.dg/torture/builtin-round-roundeven.c (main): Add tests for DBL_MAX, inf, their negations and nan.
2020-02-12libstdc++: Add missing std:: qualification of a forward callFrançois Dumont2-1/+7
* include/bits/hashtable.h (_Hashtable<>(_Hashtable&&, std::allocator_type&)): Add missing std namespace qualification to forward call.
2020-02-12PR middle-end/93646 - confusing -Wstringop-truncation on strncat where ↵Martin Sebor4-12/+67
-Wstringop-overflow is expected gcc/ChangeLog: PR middle-end/93646 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename... (handle_builtin_stxncpy_strncat): ...to this. Change first argument. Issue only -Wstringop-overflow strncat, never -Wstringop-truncation. (strlen_check_and_optimize_call): Adjust callee name. gcc/testsuite/ChangeLog: PR middle-end/93646 * gcc.dg/Wstringop-overflow-31.c: New test.
2020-02-12Drop unused comparison shortening pattern and consolidate remaining ↵Jeff Law2-62/+12
comparison shortening patterns. * config/h8300/h8300.md (comparison shortening peepholes): Drop (and (xor)) variant. Combine other two into single peephole.
2020-02-12[AArch64] Set ctz rtx_cost (PR93565)Wilco Dijkstra4-0/+51
Combine sometimes behaves oddly and duplicates ctz to remove an unnecessary sign extension. Avoid this by setting the cost for ctz to be higher than that of a simple ALU instruction. Deepsjeng performance improves by ~0.6%. gcc/ PR rtl-optimization/93565 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs. testsuite/ PR rtl-optimization/93565 * gcc.target/aarch64/pr93565.c: New test.
2020-02-12[AArch64] Improve popcount expansionWilco Dijkstra6-3/+48
The popcount expansion uses umov to extend the result and move it back to the integer register file. If we model ADDV as a zero-extending operation, fmov can be used to move back to the integer side. This results in a ~0.5% speedup on deepsjeng on Cortex-A57. A typical __builtin_popcount expansion is now: fmov s0, w0 cnt v0.8b, v0.8b addv b0, v0.8b fmov w0, s0 gcc/ * config/aarch64/aarch64-simd.md (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern. * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of generating separate ADDV and zero_extend patterns. * config/aarch64/iterators.md (VDQV_E): New iterator. testsuite/ * gcc.target/aarch64/popcnt2.c: New test.
2020-02-12Clean up dead patterns, splitters, expanders and peepholes on the H8 port.Jeff Law4-427/+13
* config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns, expanders, splits, etc. (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise. (stpcpy_internal_<mode>, stpcpy splitter): Likewise. (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise. * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function. (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused function prototype. (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
2020-02-12c++: Add new test [PR88819]Marek Polacek2-0/+15
Fixed by r10-1975-g59febe0ece37bedab7f42ae51b9f2b7a372d2950. 2020-02-12 Marek Polacek <polacek@redhat.com> PR c++/88819 * g++.dg/cpp2a/nontype-class32.C: New test.
2020-02-12c++: Fix ICE-on-invalid with broken attribute [PR93684]Marek Polacek4-1/+16
We crash when parsing [[a:: because we see a CPP_SCOPE and then we're trying to consume a CPP_EOF token. So peek before consuming it. PR c++/93684 - ICE-on-invalid with broken attribute. * parser.c (cp_parser_std_attribute): Peek a token first before consuming it. * g++.dg/parse/attr4.C: New test.
2020-02-12i386: Fix up vec_extract_lo* patterns [PR93670]Jakub Jelinek4-5/+108
The VEXTRACT* insns have way too many different CPUID feature flags (ATT syntax) vextractf128 $imm, %ymm, %xmm/mem AVX vextracti128 $imm, %ymm, %xmm/mem AVX2 vextract{f,i}32x4 $imm, %ymm, %xmm/mem {k}{z} AVX512VL+AVX512F vextract{f,i}32x4 $imm, %zmm, %xmm/mem {k}{z} AVX512F vextract{f,i}64x2 $imm, %ymm, %xmm/mem {k}{z} AVX512VL+AVX512DQ vextract{f,i}64x2 $imm, %zmm, %xmm/mem {k}{z} AVX512DQ vextract{f,i}32x8 $imm, %zmm, %ymm/mem {k}{z} AVX512DQ vextract{f,i}64x4 $imm, %zmm, %ymm/mem {k}{z} AVX512F As the testcase shows and the patch too, we didn't get it right in all cases. The first hunk is about avx512vl_vextractf128v8s[if] incorrectly requiring TARGET_AVX512DQ. The corresponding insn is the first vextract{f,i}32x4 above, so it requires VL+F, and the builtins have it correct (TARGET_AVX512VL implies TARGET_AVX512F): BDESC (OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_UQI) BDESC (OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_UQI) We only need TARGET_AVX512DQ for avx512vl_vextractf128v4d[if]. The second hunk is about vec_extract_lo_v16s[if]{,_mask}. These are using the vextract{f,i}32x8 insns (AVX512DQ above), but we weren't requiring that, but instead incorrectly && 1 for non-masked and && (64 == 64 && TARGET_AVX512VL) for masked insns. This is extraction from ZMM, so it doesn't need VL for anything. The hunk actually only requires TARGET_AVX512DQ when the insn is masked, if it is not masked, when TARGET_AVX512DQ isn't available we can use vextract{f,i}64x4 instead which is available already in TARGET_AVX512F and does the same thing, extracts the low 256 bits from 512 bits vector (often we split it into just nothing, but there are some special cases like when using xmm16+ when we can't without AVX512VL). The last hunk is about vec_extract_lo_v8s[if]{,_mask}. The non-_mask suffixed ones are ok already and just split into nothing (lowpart subreg). The masked ones were incorrectly requiring TARGET_AVX512VL and TARGET_AVX512DQ, when we only need TARGET_AVX512VL. 2020-02-12 Jakub Jelinek <jakub@redhat.com> PR target/93670 * config/i386/sse.md (VI48F_256_DQ): New mode iterator. (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove TARGET_AVX512DQ from condition. (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition> instead of <mask_mode512bit_condition> in condition. If TARGET_AVX512DQ is false, emit vextract*64x4 instead of vextract*32x8. (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition> from condition. * gcc.target/i386/avx512vl-pr93670.c: New test.
2020-02-12testsuite/93697 fix inconsistent warning in testcaseRichard Biener2-2/+7
The warning was emitted inconsistently on targets, so disable it since the testcase was for an ICE. 2020-02-12 Richard Biener <rguenther@suse.de> PR testsuite/93697 * gcc.dg/pr93661.c: Pass -w, remove dg-warning.
2020-02-11[IRA] Fix PR91052 by skipping multiple_sets insn in combine_and_move_insnsKewen Lin2-0/+10
As PR91052's comments show, commit r272731 exposed one issue in function combine_and_move_insns. Function combine_and_move_insns perform the unexpected movement which alter live interval of some register, leading incorrect value to be used. See PR91052 for details. 2020-02-12 Kewen Lin <linkw@gcc.gnu.org> PR target/91052 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
2020-02-11analyzer: use ultimate alias target at calls (PR 93288)David Malcolm9-16/+91
PR analyzer/93288 reports an ICE in a C++ testcase when calling a constructor. The issue is that when building the supergraph, we encounter the cgraph edge to "__ct_comp ", the DECL_COMPLETE_CONSTRUCTOR_P, and this node's DECL_STRUCT_FUNCTION has a NULL CFG, which the analyzer reads through, leading to the ICE. This patch reworks function and fndecl lookup at calls throughout the analyzer so that it looks for the ultimate_alias_target of the callee. In the case above, this means using the "__ct_base " for the ctor, which has a CFG, fixing the ICE. Getting this right allows for some simple C++ cases involving ctors to work, so the patch also adds some test coverage for that. gcc/analyzer/ChangeLog: PR analyzer/93288 * analysis-plan.cc (analysis_plan::use_summary_p): Look through the ultimate_alias_target when getting the called function. * engine.cc (exploded_node::on_stmt): Rename second "ctxt" to "sm_ctxt". Use the region_model's get_fndecl_for_call rather than gimple_call_fndecl. * region-model.cc (region_model::get_fndecl_for_call): Use ultimate_alias_target on fndecl. * supergraph.cc (get_ultimate_function_for_cgraph_edge): New function. (supergraph_call_edge): Use it when rejecting edges without functions. (supergraph::supergraph): Use it to get the function for the cgraph_edge when building interprocedural superedges. (callgraph_superedge::get_callee_function): Use it. * supergraph.h (supergraph::get_num_snodes): Make param const. (supergraph::function_to_num_snodes_t): Make first type param const. gcc/testsuite/ChangeLog: PR analyzer/93288 * g++.dg/analyzer/malloc.C: Add test coverage for a double-free called in a constructor. * g++.dg/analyzer/pr93288.C: New test.
2020-02-12rs6000: Use strlen instead of sizeof - 1Segher Boessenkool2-6/+13
It is easier to read and understand strlen ("string") than it is to read and understand sizeof ("string") - 1 . * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof where strlen is more legible. (rs6000_builtin_vectorized_libmass): Ditto. (rs6000_print_options_internal): Ditto.
2020-02-11analyzer: g++ testsuite supportDavid Malcolm4-0/+82
PR analyzer/93288 reports a C++-specific ICE with -fanalyzer. This patch creates the beginnings of a C++ test suite for the analyzer, so that there's a place to put test coverage for the fix. It adds a regression test for PR analyzer/93212, an ICE fixed in r10-5970-g32077b693df8e3ed0424031a322df23822bf2f7e. gcc/testsuite/ChangeLog: PR analyzer/93212 * g++.dg/analyzer/analyzer.exp: New subdirectory and .exp suite. * g++.dg/analyzer/malloc.C: New test. * g++.dg/analyzer/pr93212.C: New test.
2020-02-12Daily bump.GCC Administrator1-1/+1
2020-02-12c++: Fix implicit friend operator==.Jason Merrill7-11/+140
It seems that in writing testcases for the operator<=> proposal I didn't include any tests for implicitly declared friend operator==, and consequently it didn't work. 2020-02-11 Jason Merrill <jason@redhat.com> PR c++/93675 * class.c (add_implicitly_declared_members): Use do_friend. * method.c (implicitly_declare_fn): Fix friend handling. (decl_remember_implicit_trigger_p): New. (synthesize_method): Use it. * decl2.c (mark_used): Use it.
2020-02-11PR tree-optimization/93683 - ICE on calloc with unused return value in ↵Martin Sebor4-0/+30
ao_ref_init_from_ptr_and_size gcc/testsuite/ChangeLog: PR tree-optimization/93683 * gcc.dg/tree-ssa/ssa-dse-39.c: New test. gcc/ChangeLog: PR tree-optimization/93683 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
2020-02-11Add ppc_ieee128_ok target-supports procWill Schmidt3-0/+26
Add a target_supports entry to check that the __ieee128 keyword is understood by the target. Also add a dg-requires check to the existing pr92796 testcase. [testsuite] * lib/target-supports.exp (check_effective_target_ppc_ieee128_ok): New. * gcc.target/powerpc/pr92796.c: Add a require-effective-target statement for ppc_ieee128_ok.
2020-02-11Rename -mprefixed-addr to be -mprefixed, and document it.Michael Meissner8-27/+68
2020-02-11 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/predicates.md (cint34_operand): Rename the -mprefixed-addr option to be -mprefixed. * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename the -mprefixed-addr option to be -mprefixed. (OTHER_FUTURE_MASKS): Likewise. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename the -mprefixed-addr option to be -mprefixed. Change error messages to refer to -mprefixed. (num_insns_constant_gpr): Rename the -mprefixed-addr option to be -mprefixed. (rs6000_legitimate_offset_address_p): Likewise. (rs6000_mode_dependent_address): Likewise. (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be "-mprefixed" for target attributes and pragmas. (address_to_insn_form): Rename the -mprefixed-addr option to be -mprefixed. (rs6000_adjust_insn_length): Likewise. * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the -mprefixed-addr option to be -mprefixed. (ASM_OUTPUT_OPCODE): Likewise. * config/rs6000/rs6000.md (prefixed insn attribute): Rename the -mprefixed-addr option to be -mprefixed. * config/rs6000/rs6000.opt (-mprefixed): Rename the -mprefixed-addr option to be prefixed. Change the option from being undocumented to being documented. * doc/invoke.texi (RS/6000 and PowerPC Options): Document the -mprefixed option. Update the -mpcrel documentation to mention -mprefixed.
2020-02-11analyzer: fix ICE due to missing state_change purging (PR 93374)David Malcolm7-15/+52
PR analyzer/93374 reports an ICE within state_change::validate due to an m_new_sid in a recorded state-change being out of range of the svalues of the region_model of the new state. During get_or_create_node we attempt to merge the new state with the state of each of the existing enodes at the program point (in the absence of sm-state differences), simplifying the state at each attempt, and potentially reusing a node if we get a match. This state-merging invalidates any svalue_ids within any state_change object. The root cause is that, although the code was purging any such svalue_ids for the case where no match was found during merging, it was failing to purge them for the case where a matching enode *was* found for the merged state, leading to an invalid state_change along the exploded_edge to the reused enode. This patch moves the invalidation code to cover both cases, fixing the ICE. It also extends state_change validation so that states are also checked. gcc/analyzer/ChangeLog: PR analyzer/93374 * engine.cc (exploded_edge::exploded_edge): Add ext_state param and pass it to change.validate. (exploded_graph::get_or_create_node): Move purging of change svalues to also cover the case of reusing an existing enode. (exploded_graph::add_edge): Pass m_ext_state to exploded_edge's ctor. * exploded-graph.h (exploded_edge::exploded_edge): Add ext_state param. * program-state.cc (state_change::sm_change::validate): Likewise. Assert that m_sm_idx is sane. Use ext_state to validate m_old_state and m_new_state. (state_change::validate): Add ext_state param and pass it to the sm_change validate calls. * program-state.h (state_change::sm_change::validate): Add ext_state param. (state_change::validate): Likewise. gcc/testsuite/ChangeLog: PR analyzer/93374 * gcc.dg/analyzer/torture/pr93374.c: New test.
2020-02-11analyzer: fix ICE in "__analyzer_dump_exploded_nodes" on non-empty worklist ↵David Malcolm4-4/+50
(PR 93669) gcc/analyzer/ChangeLog: PR analyzer/93669 * engine.cc (exploded_graph::dump_exploded_nodes): Handle missing case of STATUS_WORKLIST in implementation of "__analyzer_dump_exploded_nodes". gcc/testsuite/ChangeLog: PR analyzer/93669 * gcc.dg/analyzer/pr93669.c: New test.
2020-02-11analyzer: fix ICE with equiv_class constant (PR 93649)David Malcolm4-2/+86
gcc/analyzer/ChangeLog: PR analyzer/93649 * constraint-manager.cc (constraint_manager::add_constraint): When merging equivalence classes and updating m_constant, also update m_cst_sid. (constraint_manager::validate): If m_constant is non-NULL assert that m_cst_sid is non-null and is valid. gcc/testsuite/ChangeLog: PR analyzer/93649 * gcc.dg/analyzer/torture/pr93649.c: New test.
2020-02-11analyzer.opt: reword descriptions of two dump options (PR 93657)David Malcolm2-2/+8
gcc/analyzer/ChangeLog: PR analyzer/93657 * analyzer.opt (fdump-analyzer): Reword description. (fdump-analyzer-stderr): Likewise.
2020-02-11analyzer: workaround for nested pp_printfDavid Malcolm2-4/+39
The dumps from the analyzer sometimes contain garbled output. The root cause is due to nesting of calls to pp_printf: I'm using pp_printf with %qT to print types with a PP using default_tree_printer. default_tree_printer handles 'T' (and various other codes) via dump_generic_node (pp, t, 0, TDF_SLIM, 0); and dump_generic_node can call pp_printf in various ways, leading to a pp_printf within a pp_printf, and garbled output. I don't think it's feasible to fix pp_printf to be reentrant, in stage 4, at least, so for the moment this patch works around it in the analyzer. gcc/analyzer/ChangeLog: * region-model.cc (print_quoted_type): New function. (svalue::print): Use it to replace %qT. (region::dump_to_pp): Likewise. (region::dump_child_label): Likewise. (region::print_fields): Likewise.
2020-02-11regalloc/debug: fix buggy print_hard_reg_setHans-Peter Nilsson3-20/+30
* ira-conflicts.c (print_hard_reg_set): Correct output for sets including FIRST_PSEUDO_REGISTER - 1. * ira-color.c (print_hard_reg_set): Ditto. Before, for a target with FIRST_PSEUDO_REGISTER 20, you'd get "19-18" for (1<<19). For (1<<18)|(1<<19), you'd get "18". I was using ira-conflicts.c:print_hard_reg_set with a local patch to gdbinit.in in a debug-session, and noticed the erroneous output. I see there's an almost identical function in ira-color.c and on top of that, there's another function by the same name and with similar semantics in sel-sched-dump.c, but the last one doesn't try to print ranges.
2020-02-11Tweak testcases for pr70010Will Schmidt3-2/+9
[testsuite] * gcc.target/powerpc/pr70010-2.c: Add -maltivec. * gcc.target/powerpc/pr70010-3.c: Add -maltivec.
2020-02-11[GCC][PATCH][ARM]Add ACLE intrinsics for dot product (vusdot - vector, ↵Stam Markianos-Wright12-6/+385
v<us/su>dot - by element) for AArch32 AdvSIMD ARMv8.6 Extension This patch adds the ARMv8.6 Extension ACLE intrinsics for dot product operations (vector/by element) to the ARM back-end. These are: usdot (vector), <us/su>dot (by element). The functions are optional from ARMv8.2-a as -march=armv8.2-a+i8mm and for ARM they remain optional after as of ARMv8.6-a. The functions are declared in arm_neon.h, RTL patterns are defined to generate assembler and tests are added to verify and perform adequate checks. Regression testing on arm-none-eabi passed successfully. gcc/ChangeLog: 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com> * config/arm/arm-builtins.c (enum arm_type_qualifiers): (USTERNOP_QUALIFIERS): New define. (USMAC_LANE_QUADTUP_QUALIFIERS): New define. (SUMAC_LANE_QUADTUP_QUALIFIERS): New define. (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX. (arm_expand_builtin_1): Add qualifier_lane_quadtup_index. * config/arm/arm_neon.h (vusdot_s32): New. (vusdot_lane_s32): New. (vusdotq_lane_s32): New. (vsudot_lane_s32): New. (vsudotq_lane_s32): New. * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New. * config/arm/iterators.md (DOTPROD_I8MM): New. (sup, opsuffix): Add <us/su>. * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New. * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New. gcc/testsuite/ChangeLog: 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com> * gcc.target/arm/simd/vdot-2-1.c: New test. * gcc.target/arm/simd/vdot-2-2.c: New test. * gcc.target/arm/simd/vdot-2-3.c: New test. * gcc.target/arm/simd/vdot-2-4.c: New test.
2020-02-11tree-optimization/93661 properly guard tree_to_poly_int64Richard Biener1-0/+9
2020-02-11 Richard Biener <rguenther@suse.de> PR tree-optimization/93661 PR tree-optimization/93662 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard tree_to_poly_int64. * tree-sra.c (get_access_for_expr): Likewise. * gcc.dg/pr93661.c: New testcase.
2020-02-11tree-optimization/93661 properly guard tree_to_poly_int64Richard Biener4-2/+19
2020-02-11 Richard Biener <rguenther@suse.de> PR tree-optimization/93661 PR tree-optimization/93662 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard tree_to_poly_int64. * tree-sra.c (get_access_for_expr): Likewise. * gcc.dg/pr93661.c: New testcase.
2020-02-11c++: Fix static initialization from <=>.Jason Merrill4-7/+30
Constant evaluation of genericize_spaceship produced a CONSTRUCTOR, which we then wanted to bind to a reference, which we can't do. So wrap the result in a TARGET_EXPR so we get something with an address. We also need to handle treating the result of cxx_eval_binary_expression as a glvalue for SPACESHIP_EXPR. My earlier change to add uid_sensitive to maybe_constant_value was wrong; we don't even look at the cache when manifestly_const_eval, and I failed to adjust the later call to cxx_eval_outermost_constant_expr. gcc/cp/ChangeLog 2020-02-11 Jason Merrill <jason@redhat.com> PR c++/93650 PR c++/90691 * constexpr.c (maybe_constant_value): Correct earlier change. (cxx_eval_binary_expression) [SPACESHIP_EXPR]: Pass lval through. * method.c (genericize_spaceship): Wrap result in TARGET_EXPR.
2020-02-10c++: Fix return type deduction with an abbreviated function templatePatrick Palka10-32/+72
This patch fixes two issues with return type deduction in the presence of an abbreviated function template. The first issue (PR 69448) is that if a placeholder auto return type contains any modifiers such as & or *, then the abbreviated function template compensation in splice_late_return_type does not get performed for the underlying auto node, leading to incorrect return type deduction. This happens because splice_late_return_type does not consider that a placeholder auto return type might have modifiers. To fix this it seems we need to look through modifiers in the return type to obtain the location of the underlying auto node in order to replace it with the adjusted auto node. To that end this patch refactors the utility function find_type_usage to return a pointer to the matched tree, and uses it to find and replace the underlying auto node. The second issue (PR 80471) is that the AUTO_IS_DECLTYPE flag is not being preserved in splice_late_return_type when compensating for an abbreviated function template, leading to us treating a decltype(auto) return type as if it was an auto return type. Fixed by making make_auto_1 set the AUTO_IS_DECLTYPE flag whenever we're building a decltype(auto) node and adjusting callers appropriately. The test for PR 80471 is adjusted to expect the correct behavior. gcc/cp/ChangeLog: PR c++/69448 PR c++/80471 * type-utils.h (find_type_usage): Refactor to take a tree * and to return a tree *, and update documentation accordingly. * pt.c (make_auto_1): Set AUTO_IS_DECLTYPE when building a decltype(auto) node. (make_constrained_decltype_auto): No need to explicitly set AUTO_IS_DECLTYPE anymore. (splice_late_return_type): Use find_type_usage to find and replace a possibly nested auto node instead of using is_auto. Check test for is_auto into an assert when deciding whether to late_return_type. (type_uses_auto): Adjust the call to find_type_usage. * parser.c (cp_parser_decltype): No need to explicitly set AUTO_IS_DECLTYPE anymore. libcc1/ChangeLog: PR c++/69448 PR c++/80471 * libcp1plugin.cc (plugin_get_expr_type): No need to explicitly set AUTO_IS_DECLTYPE anymore. gcc/testsuite/ChangeLog: PR c++/69448 PR c++/80471 * g++.dg/concepts/abbrev3.C: New test. * g++.dg/cpp2a/concepts-pr80471.C: Adjust a static_assert to expect the correct behavior. * g++.dg/cpp0x/auto9.C: Adjust a dg-error directive.
2020-02-10c++: Improve dump_decl for standard conceptsPatrick Palka4-10/+36
This patch improves the pretty printing of standard concept definitions in error messages. In particular, standard concepts are now printed qualified whenever appropriate, and the "concept" specifier is printed only when the TFF_DECL_SPECIFIERS flag is specified. In the below test, the first error message changes from 9:15: error: ‘b’ was not declared in this scope; did you mean ‘concept b’? to 9:15: error: ‘b’ was not declared in this scope; did you mean ‘a::b’? gcc/cp/ChangeLog: * error.c (dump_decl) [CONCEPT_DECL]: Use dump_simple_decl. (dump_simple_decl): Handle standard concept definitions as well as variable concept definitions. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts6.C: New test.
2020-02-11Daily bump.GCC Administrator1-1/+1
2020-02-10analyzer.opt: fix typos in descriptions (PR 93659)David Malcolm2-2/+10
gcc/analyzer/ChangeLog: PR analyzer/93659 * analyzer.opt (-param=analyzer-max-recursion-depth=): Fix "tha" -> "that" typo. (Wanalyzer-use-of-uninitialized-value): Fix "initialized" -> "uninitialized" typo.
2020-02-10analyzer: handle vector types (PR 93350)David Malcolm4-1/+33
gcc/analyzer/ChangeLog: PR analyzer/93350 * region-model.cc (region_model::get_lvalue_1): Handle BIT_FIELD_REF. (make_region_for_type): Handle VECTOR_TYPE. gcc/testsuite/ChangeLog: PR analyzer/93350 * gcc.dg/analyzer/torture/pr93350.c: New test.
2020-02-10analyzer: fix ICE reporting NULL dereference (PR 93647)David Malcolm5-0/+36
gcc/analyzer/ChangeLog: PR analyzer/93647 * diagnostic-manager.cc (diagnostic_manager::prune_for_sm_diagnostic): Bulletproof against VAR being constant. * region-model.cc (region_model::get_lvalue_1): Provide a better error message when encountering an unhandled tree code. gcc/testsuite/ChangeLog: PR analyzer/93647 * gcc.dg/analyzer/torture/pr93647.c: New test.
2020-02-10i386: Fix -mavx -mno-mavx2 ICE with VEC_COND_EXPR [PR93637]Jakub Jelinek4-5/+40
As mentioned in the PR, for -mavx -mno-avx2 the backend does support vcondv4div4df and vcondv8siv8sf optabs (while generally 32-byte vectors aren't much supported in that case, it is performed using vandps/vandnps/vorps). The problem is that after the last generic vector lowering (where the VEC_COND_EXPR still compares two V4DF vectors and has two V4DI last operands and V4DI result and so is considered ok) fre4 folds the condition into constant, at which point the middle-end during expansion will try vcond_mask_optab and fall back to trying to expand it as the constant vector < 0 vcondv4div4di, but neither of them is supported for -mavx -mno-avx2 and thus we ICE. So, the options I see is either what the following patch does, also support vcond_mask_v4div4di and vcond_mask_v4siv4si already for TARGET_AVX, or require for vcondv4div4df and vcondv8siv8sf TARGET_AVX2 rather than current TARGET_AVX. 2020-02-10 Jakub Jelinek <jakub@redhat.com> PR target/93637 * config/i386/sse.md (VI_256_AVX2): New mode iterator. (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256. Change condition from TARGET_AVX2 to TARGET_AVX. * gcc.target/i386/avx-pr93637.c: New test.
2020-02-10analyzer: fix ICE with fortran constant arguments (PR 93405)David Malcolm4-0/+38
PR analyzer/93405 reports an ICE with -fanalyzer when passing a constant "by reference" in gfortran. The issue is that the constant is passed as an ADDR_EXPR of a CONST_DECL, and region_model::get_lvalue_1 doesn't know how to handle CONST_DECL. This patch implements it for CONST_DECL by providing a placeholder region, holding the CONST_DECL's value, fixing the ICE. gcc/analyzer/ChangeLog: PR analyzer/93405 * region-model.cc (region_model::get_lvalue_1): Implement CONST_DECL. gcc/testsuite/ChangeLog: PR analyzer/93405 * gfortran.dg/analyzer/pr93405.f90: New test.
2020-02-10analyzer: gfortran testsuite supportDavid Malcolm4-0/+102
This patch adds a gfortran.dg/analyzer subdirectory with an analyzer.exp, setting DEFAULT_FFLAGS on the tests run within it. It also adds a couple of simple proof-of-concept tests of e.g. detecting double-frees from gfortran. gcc/testsuite/ChangeLog: * gfortran.dg/analyzer/analyzer.exp: New subdirectory and .exp suite. * gfortran.dg/analyzer/malloc-example.f90: New test. * gfortran.dg/analyzer/malloc.f90: New test.
2020-02-10Fix libgcc build failure for FRV with recent versions of gas.Jeff Law3-4/+10
* config/frv/frvbegin.c: Use right flags for .ctors and .dtors sections. * config/frv/frvend.c: Similarly.
2020-02-10Darwin: -Wformat-diag fix (PR93641)Iain Sandoe2-1/+8
The length used for the comparison for 'CFStringRef' was only comparing for 'CFString', potentially allowing mismatched identifiers. 2020-02-10 Iain Sandoe <iain@sandoe.co.uk> PR other/93641 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last argument of strncmp.
2020-02-10Fix bogus duplicate attribute errors for submodule functions.Andrew Benson5-5/+50
PR fortran/83113 * array.c: Do not attempt to set the array spec for a submodule function symbol (as it has already been set in the corresponding module procedure interface). * symbol.c: Do not reject duplicate POINTER, ALLOCATABLE, or DIMENSION attributes in declarations of a submodule function. * gfortran.h: Add a macro that tests for a module procedure in a submodule. * gfortran.dg/pr83113.f90: New test.
2020-02-10PR c/93640 - The write_only and read_write attributes can be mistyped due to ↵Martin Sebor4-2/+33
invalid strncmp size argument gcc/c-family/ChangeLog: PR c/93640 * c-attribs.c (handle_access_attribute): Correct off-by-one mistakes. gcc/testsuite/ChangeLog: PR c/93640 * gcc.dg/attr-access.c: New test.
2020-02-10gcc.target/cris/dbr-1.c: New test.Hans-Peter Nilsson2-5/+15
Random spotting. Exposes the missed benefit for delay-slot filling of a splitter for indexed addressing mode (the [rN+M] one). To be considered for common instructions and perhaps only for suitable M; at least +-63 is obvious (when there's a register available) as both the original and the add fit in delay-slots.
2020-02-10gcc.target/cris/pr93372-3.c, -4.c...-35.c: New tests.Hans-Peter Nilsson32-0/+658
PR target/93372 * gcc.target/cris/pr93372-3.c, gcc.target/cris/pr93372-4.c, gcc.target/cris/pr93372-6.c, gcc.target/cris/pr93372-7.c, gcc.target/cris/pr93372-9.c, gcc.target/cris/pr93372-10.c, gcc.target/cris/pr93372-11.c, gcc.target/cris/pr93372-12.c, gcc.target/cris/pr93372-13.c, gcc.target/cris/pr93372-14.c, gcc.target/cris/pr93372-15.c, gcc.target/cris/pr93372-16.c, gcc.target/cris/pr93372-17.c, gcc.target/cris/pr93372-18.c, gcc.target/cris/pr93372-19.c, gcc.target/cris/pr93372-20.c, gcc.target/cris/pr93372-21.c, gcc.target/cris/pr93372-22.c, gcc.target/cris/pr93372-23.c, gcc.target/cris/pr93372-24.c, gcc.target/cris/pr93372-25.c, gcc.target/cris/pr93372-26.c, gcc.target/cris/pr93372-27.c, gcc.target/cris/pr93372-28.c, gcc.target/cris/pr93372-29.c, gcc.target/cris/pr93372-30.c, gcc.target/cris/pr93372-31.c, gcc.target/cris/pr93372-32.c, gcc.target/cris/pr93372-33.c, gcc.target/cris/pr93372-34.c, gcc.target/cris/pr93372-35.c: New tests. Check that somewhat-trivially eliminable compare-instructions are eliminated, for all instructions. Note that pr93372-23.c and pr93372-24.c are xfailed with cc0.
2020-02-10gcc.target/cris/pr93372-2.c, -5.c, -8.c: New tests.Hans-Peter Nilsson4-0/+56
* gcc.target/cris/pr93372-2.c, gcc.target/cris/pr93372-5.c, gcc.target/cris/pr93372-8.c: New tests. These tests fails miserably both at being an example of cc0 eliminating compare instructions, and post-cc0-CRIS at showing a significant improvement. They're here to track suboptimal comparison code for CRIS.
2020-02-10gcc.target/cris/pr93372-1.c: New test.Hans-Peter Nilsson2-0/+74
This test was separated from the posted and approved patch named "dbr: Filter-out TARGET_FLAGS_REGNUM from end_of_function_needs" and applied: it doesn't fail yet. It differs from the posted version in that function "g" is commented-out; see the added comment.
2020-02-10gcc.target/cris/cris.exp (check_effective_target_cc0): New.Hans-Peter Nilsson2-0/+15
To simplify separating the cc0-specific xfails, let's have an effective-target. This likely fits all targets.
2020-02-10cris: try to generate zero-based comparisonsHans-Peter Nilsson4-2/+70
* config/cris/cris.c (cris_reduce_compare): New function. * config/cris/cris-protos.h (cris_reduce_compare): Add prototype. * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4") (cstore<mode>4"): Apply cris_reduce_compare in expanders. The decc0ration work of the CRIS port made me look closer at the code for trivial comparisons, as in the condition for branches and conditional-stores, like in: void g(short int a, short int b) { short int c = a + b; if (c >= 0) foo (); } At -O2, the cc0 version of the CRIS port has an explicit *uneliminated* compare instruction ("cmp.w -1,$r10") instead of an (eliminated) compare against 0 (which below I'll call a zero-compare). This for the CRIS-cc0 version, but I see this also for a much older gcc, at 4.7. For the decc0rated port, the compare *is* a test against 0, eventually eliminated. To wit, for cc0 (mind the delay-slot): _g: subq 4,$sp add.w $r11,$r10 cmp.w -1,$r10 ble .L9 move $srp,[$sp] jsr _foo .L9: jump [$sp+] The compare instruction is expected to be eliminated, i.e. the following diff to the above is desired, modulo the missing sibling call, which corresponds to what I get from 4.7 and for the decc0rated port: !--- a Wed Feb 5 15:22:27 2020 !+++ b Wed Feb 5 15:22:51 2020 !@@ -1,8 +1,7 @@ ! _g: ! subq 4,$sp ! add.w $r11,$r10 !- cmp.w -1,$r10 !- ble .L9 !+ bmi .L9 ! move $srp,[$sp] ! ! jsr _foo Tracking this difference, I see that for both cc0-CRIS and the decc0rated CRIS, the comparison actually starts out as a compare against -1 at "expand" time, but is transformed for decc0rated CRIS to a zero-compare in "cse1". For CRIS-cc0 "cse1" does try to replace the compare with a zero-compare, but fails because at the same time it tries to replace the c operand with (a + b). Or some such; it fails and no other pass succeeds. I was not into fixing cc0-handling in core gcc, so I didn't look closer. BTW, at first, I was a bit surprised to see that for compares against a constant, a zero-compare is not canonical RTX for *all* conditions, and that instead only a subset of all RTX conditions against a constant are canonical, transforming one condition to the canonical one by adding 1 or -1 to the constant. It does makes sense at a closer look, but still not so much when emitting RTL. There are several places that mention in comments that emitting RTX as zero-compare is preferable, but nothing is done about it. Some generic code instead seems confused that the *target* is helped by seeing canonical RTX, or perhaps it (its authors) like me, confused about what a canonical comparison is. For example, prepare_cmp_insn calls canonicalize_comparison last before emitting the actual instructions. I see most ports for various port-specific reasons does their own massaging in their cbranch and cstore expanders. Still, the suboptimal compares *should* be fixed at expand time; better start out right than just relying on later optimizations. This kind of change is not acceptable in the current gcc development stage, at least as a change in generic code. However, it's problematic enough that I chose to fix this right now in the CRIS port. For that, I claim a possibly long-standing regression. After this, code before and after decc0ration is similar enough that I can spot compare-elimination-efforts and apply regression test-cases without them drowning in cc0-specific xfailing. I hope to eventually lift out cris_reduce_compare (renamed) into say expmed.c, called in e.g. emit_store_flag_1 (replacing the in-line code) and prepare_cmp_insn. Later.