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2020-06-24Daily bump.GCC Administrator12-1/+218
2020-06-23Allow --with-cpu=power10Aaron Sawdey1-2/+2
Update config.gcc so that we can use --with-cpu=power10. Also remove "future" from the 64-bit check as Segher suggests. * config.gcc: Identify power10 as a 64-bit processor and as valid for --with-cpu and --with-tune.
2020-06-23c++: Improve CTAD for aggregates [PR93976]Jason Merrill5-15/+171
P2082R1 adjusted the rules for class template argument deduction for an aggregate to better handle arrays and pack expansions. gcc/cp/ChangeLog: PR c++/93976 Implement C++20 P2082R1, Fixing CTAD for aggregates. * cp-tree.h (TPARMS_PRIMARY_TEMPLATE): Split out from... (DECL_PRIMARY_TEMPLATE): ...here. (builtin_guide_p): Declare. * decl.c (reshape_init_class): Handle bases of a template. (reshape_init_r): An array with dependent bound takes a single initializer. * pt.c (tsubst_default_argument): Shortcut {}. (unify_pack_expansion): Allow omitted arguments to trailing pack. (builtin_guide_p): New. (collect_ctor_idx_types): Give a trailing pack a {} default argument. Handle arrays better. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/class-deduction-aggr3.C: New test. * g++.dg/cpp2a/class-deduction-aggr4.C: New test.
2020-06-23Make forall statement in testsuite conforming.Thomas Koenig1-4/+4
The recent patch for dependency checking introduced one failing test case for pointer assignments in a forall statement. This test case was invalid because of an interdependency in a forall statement. This patch fixes that by removing that dependency. gcc/testsuite/ChangeLog: * gfortran.fortran-torture/execute/forall_5.f90: Make forall statement conforming.
2020-06-23coroutines: Add a cleanup expression for g-r-o when needed [PR95477].Iain Sandoe3-11/+156
The PR reports that we fail to destroy the object initially created from the get-return-object call. Fixed by adding a cleanup when the DTOR is non-trivial. In addition, to meet the specific wording that the call to get_return_object creates the glvalue for the return, we must construct that in-place in the return object to avoid a second copy/move CTOR. gcc/cp/ChangeLog: PR c++/95477 * coroutines.cc (morph_fn_to_coro): Apply a cleanup to the get return object when the DTOR is non-trivial. gcc/testsuite/ChangeLog: PR c++/95477 * g++.dg/coroutines/pr95477.C: New test. * g++.dg/coroutines/void-gro-non-class-coro.C: New test.
2020-06-23build: Change conditional include and empty.mk to -include in MakefilesDavid Edelsohn5-29/+21
GNU Make supports "-include" keyword to prevent warnings and errors due to inclusion of non-existent files. This patch changes gcc/ and libgcc/ to use "-include" in place of the historical conditional inclusion and use of empty.mk work-arounds. gcc/ChangeLog 2020-06-23 David Edelsohn <dje.gcc@gmail.com> * Makefile.in (LANG_MAKEFRAGS): Same. (tmake_file): Use -include. (xmake_file): Same. libgcc/ChangeLog 2020-06-23 David Edelsohn <dje.gcc@gmail.com> * Makefile.in: Remove uses of empty.mk. Use -include. * config/avr/t-avr: Use -include. * empty.mk: Delete. libgcc/config/avr/libf7/ChangeLog 2020-06-23 David Edelsohn <dje.gcc@gmail.com> * t-libf7: Same.
2020-06-23libiberty, include: add bsearch_rNick Alcock4-3/+130
libctf wants a bsearch that takes a void * arg pointer to avoid a nonportable use of __thread. bsearch_r is required, not optional, at this point because as far as I can see this obvious-sounding function is not implemented by anyone's libc. We can easily move it to AC_LIBOBJ later if it proves necessary to do so. include/ * libiberty.h (bsearch_r): New. libiberty/ * bsearch_r.c: New file. * Makefile.in (CFILES): Add bsearch_r.c. (REQUIRED_OFILES): Add bsearch_r.o. * functions.texi: Regenerate.
2020-06-23Remove superfluous spaceEric Botcazou1-1/+1
gcc/ada/ChangeLog: * gcc-interface/utils2.c (build_binary_op): Remove space.
2020-06-23Fix memory corruption with vector and variant recordEric Botcazou1-6/+12
The problem is that Has_Constrained_Partial_View must be tested on the base type of the designated type of an allocator. gcc/ada/ChangeLog: * gcc-interface/trans.c (gnat_to_gnu) <N_Allocator>: Minor tweaks. Call Has_Constrained_Partial_View on base type of designated type.
2020-06-23Emit debug info for integral variables firstEric Botcazou1-17/+25
This makes it possible for global dynamic types to reference the DIE of these integral variables. gcc/ada/ChangeLog: * gcc-interface/utils.c (gnat_write_global_declarations): Output integral global variables first and the imported functions later.
2020-06-23Minor tweak to elaborate_expression_1Eric Botcazou1-4/+13
gcc/ada/ChangeLog: * gcc-interface/decl.c (elaborate_expression_1): When GNAT encodings are not used, do not create a variable for debug info purposes if the expression is itself a user-declared variable.
2020-06-23Streamline implementation of renaming in gigiEric Botcazou4-119/+66
The main changes are 1) the bulk of the implementation is put back entirely in gnat_to_gnu_entity and 2) the handling of lvalues is unified, i.e. it no longer depends on the Materialize_Entity flag being present on the entity. gcc/ada/ChangeLog: * gcc-interface/ada-tree.h (DECL_RENAMED_OBJECT): Delete. * gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Always use the stabilized reference directly for renaming and create a variable pointing to it separately if requested. * gcc-interface/misc.c (gnat_print_decl): Adjust for deletion. * gcc-interface/trans.c (Identifier_to_gnu): Likewise. (gnat_to_gnu) <N_Object_Renaming_Declaration>: Do not deal with side-effects here. <N_Exception_Renaming_Declaration>: Likewise.
2020-06-23Minor cleanup in elaborate_expressionEric Botcazou1-2/+2
gcc/ada/ChangeLog: * gcc-interface/decl.c (elaborate_expression): Replace calls to Is_OK_Static_Expression with Compile_Time_Known_Value.
2020-06-23Emit user subtypes with -fgnat-encodings=minimalEric Botcazou1-12/+7
This changes the compiler to emit debug info for user-defined subtypes with -fgnat-encodings=minimal, as they might be needed by the debugger. gcc/ada/ChangeLog: * gcc-interface/decl.c (gnat_to_gnu_entity) <E_Record_Subtype>: Set debug type to the base type and only if the subtype is artificial.
2020-06-23Remove unintended checkinMichael Meissner1-1/+0
2020-06-23 Michael Meissner <meissner@linux.ibm.com> * REVISION: Delete file meant for a private branch.
2020-06-23Minor adjustment in assignment caseEric Botcazou1-4/+3
gcc/ada/ChangeLog: * gcc-interface/trans.c (gnat_to_gnu) <N_Assignment_Statement>: Do not test Is_Bit_Packed_Array in the memset path.
2020-06-23arm: PR target/95646: Do not clobber callee saved registers with CMSEAndre Simoes Dias Vieira2-1/+33
As reported in bugzilla when the -mcmse option is used while compiling for size (-Os) with a thumb-1 target the generated code will clear the registers r7-r10. These however are callee saved and should be preserved accross ABI boundaries. The reason this happens is because these registers are made "fixed" when optimising for size with Thumb-1 in a way to make sure they are not used, as pushing and popping hi-registers requires extra moves to and from LO_REGS. To fix this, this patch uses 'callee_saved_reg_p', which accounts for this optimisation, instead of 'call_used_or_fixed_reg_p'. Be aware of 'callee_saved_reg_p''s definition, as it does still take call used registers into account, which aren't callee_saved in my opinion, so it is a rather misnoemer, works in our advantage here though as it does exactly what we need. Regression tested on arm-none-eabi. Is this OK for trunk? (Will eventually backport to previous versions if stable.) gcc/ChangeLog: 2020-06-19 Andre Vieira <andre.simoesdiasvieira@arm.com> PR target/95646 * config/arm/arm.c: (cmse_nonsecure_entry_clear_before_return): Use 'callee_saved_reg_p' instead of 'calL_used_or_fixed_reg_p'. gcc/testsuite/ChangeLog: 2020-06-19 Andre Vieira <andre.simoesdiasvieira@arm.com> PR target/95646 * gcc.target/arm/pr95646.c: New test.
2020-06-23libstdc++: Adjust std::from_chars negative testsJonathan Wakely2-1/+10
Also test with an enumeration type. Move the dg-error directives outside the #if block, because DejaGnu would process them whether or not wchar_t support is present. libstdc++-v3/ChangeLog: * testsuite/20_util/from_chars/1_c++20_neg.cc: Check enumeration type. * testsuite/20_util/from_chars/1_neg.cc: Likewise. Move dg-error directives outside preprocessor condition.
2020-06-23handle dumpbase in offloading, adjust testsuiteAlexandre Oliva10-66/+185
Pass dumpbase on to mkoffloads and their offload-target compiler runs, using different suffixes for different offloading targets. Obey -save-temps in naming temporary files while at that. Adjust the testsuite offload dump scanning machinery to look for dump files named under the new conventions, iterating internally over all configured offload targets, or recognizing libgomp's testsuite's own iteration. for gcc/ChangeLog * collect-utils.h (dumppfx): New. * collect-utils.c (dumppfx): Likewise. * lto-wrapper.c (run_gcc): Set global dumppfx. (compile_offload_image): Pass a -dumpbase on to mkoffload. * config/nvptx/mkoffload.c (ptx_dumpbase): New. (main): Handle incoming -dumpbase. Set ptx_dumpbase. Obey save_temps. (compile_native): Pass -dumpbase et al to compiler. * config/gcn/mkoffload.c (gcn_dumpbase): New. (main): Handle incoming -dumpbase. Set gcn_dumpbase. Obey save_temps. Pass -dumpbase et al to offload target compiler. (compile_native): Pass -dumpbase et al to compiler. for gcc/testsuite/ChangeLog * lib/scanoffload.exp: New. * lib/scanoffloadrtl.exp: Load it. Replace ".o" with "" globally, and use scanoffload's scoff wrapper to fill it in. * lib/scanoffloadtree.exp: Likewise. for libgomp/ChangeLog * testsuite/lib/libgomp.exp: Load gcc lib scanoffload.exp. * testsuite/lib/libgomp-dg.exp: Drop now-obsolete -save-temps.
2020-06-23libstdc++: Implement P1972R2 changes to std::variant (PR 95832)Jonathan Wakely3-16/+44
G++ implements P1972R2 since r11-1597-0ca22d027ecc and so we no longer need the P0608R3 special case to prevent narrowing conversions to bool. Since non-GNU compilers don't necessarily implment P1972R2 yet, this may cause a regression for those compilers. There is no feature-test macro we can use to detect it though, so we'll have to live with it. libstdc++-v3/ChangeLog: PR libstdc++/95832 * include/std/variant (__detail::__variant::_Build_FUN): Remove partial specialization to prevent narrowing conversions to bool. * testsuite/20_util/variant/compile.cc: Test non-narrowing conversions to bool. * testsuite/20_util/variant/run.cc: Likewise.
2020-06-23libstdc++: Regenerate makefilesJonathan Wakely11-0/+11
libstdc++-v3/ChangeLog: * doc/Makefile.in: Regenerate. * include/Makefile.in: Regenerate. * libsupc++/Makefile.in: Regenerate. * po/Makefile.in: Regenerate. * python/Makefile.in: Regenerate. * src/Makefile.in: Regenerate. * src/c++11/Makefile.in: Regenerate. * src/c++17/Makefile.in: Regenerate. * src/c++98/Makefile.in: Regenerate. * src/filesystem/Makefile.in: Regenerate. * testsuite/Makefile.in: Regenerate.
2020-06-23Add REVISIONMichael Meissner1-0/+1
gcc/ 2020-06-23 Michael Meissner <meissner@linux.ibm.com> * REVISION: New file.
2020-06-23Handle AR_FULL vs. AR_FULL in dependency checking.Thomas Koenig2-0/+17
Previously, handling of full vs. full references failed to take AR_FULL vs. AR_FULL into account. A change in dependency checking in gcc 10 created a code path that could lead there; with this patch, this is now correctly handled. gcc/fortran/ChangeLog: 2020-06-23 Thomas Koenig <tkoenig@gcc.gnu.org> PR fortran/95812 * dependency.c (ref_same_as_full_array): Handle case of AR_FULL vs. AR_FULL. gcc/testsuite/ChangeLog: 2020-06-23 Thomas Koenig <tkoenig@gcc.gnu.org> PR fortran/95812 * gfortran.dg/dependency_59.f90: New test.
2020-06-23Fortran : ICE in gfc_validate_kind PR95586Mark Eggleston3-1/+21
Report syntax error for invalid letter-spec in IMPLICIT statements for derived types and not an ICE. Original patch by Steve Kargl. Added test cases based on those provided by G. Steinmetz in the PR. 2020-06-23 Steven G. Kargl <kargl@gcc.gnu.org> gcc/fortran/ PR fortran/95586 * decl.c (gfc_match_implicit): Only perform else branch if the type spect is not BT_DERIVED. 2020-06-23 Mark Eggleston <markeggleston@gcc.gnu.org> gcc/testsuite/ PR fortran/95586 * gfortran.dg/pr95586_1.f90: New test. * gfortran.dg/pr95586_2.f90: New test.
2020-06-23Daily bump.GCC Administrator9-1/+347
2020-06-22build: Use -include instead of conditional include.David Edelsohn8-24/+8
Automake and GNU Make both use the endif keyword, which conflicts and elicits an error for matching if/ifdef and endif. This patch changes the conditional include to use "-include" to prevent a warning about a possible empty tmake_file. libgomp/ChangeLog 2020-06-22 David Edelsohn <dje.gcc@gmail.com> * Makefile.am: Use -include. * Makefile.in: Regenerate. libatomic/ChangeLog 2020-06-22 David Edelsohn <dje.gcc@gmail.com> * Makefile.am: Use -include. * Makefile.in: Regenerate. libstdc++-v3/ChangeLog 2020-06-22 David Edelsohn <dje.gcc@gmail.com> * Makefile.am: Use -include. * Makefile.in: Regenerate. libgfortran/ChangeLog 2020-06-22 David Edelsohn <dje.gcc@gmail.com> * Makefile.am: Use -include. * Makefile.in: Regenerate.
2020-06-22rs6000: Testsuite changes to go with the previous commitSegher Boessenkool168-268/+268
The "sanity checker" thinks it knows better than maintainers, and there is no override. 2020-06-22 Segher Boessenkool <segher@kernel.crashing.org> gcc/testsuite/ChangeLog: * gcc.target/powerpc/cfuged-0.c: I protest. * gcc.target/powerpc/cfuged-1.c: I protest. * gcc.target/powerpc/clone3.c: I protest. * gcc.target/powerpc/cntlzdm-0.c: I protest. * gcc.target/powerpc/cntlzdm-1.c: I protest. * gcc.target/powerpc/cnttzdm-0.c: I protest. * gcc.target/powerpc/cnttzdm-1.c: I protest. * gcc.target/powerpc/cpu-future.c: I protest. * gcc.target/powerpc/dg-future-0.c: I protest. * gcc.target/powerpc/dg-future-1.c: I protest. * gcc.target/powerpc/localentry-1.c: I protest. * gcc.target/powerpc/localentry-detect-1.c: I protest. * gcc.target/powerpc/mma-builtin-1.c: I protest. * gcc.target/powerpc/mma-builtin-2.c: I protest. * gcc.target/powerpc/mma-builtin-3.c: I protest. * gcc.target/powerpc/mma-builtin-4.c: I protest. * gcc.target/powerpc/mma-builtin-5.c: I protest. * gcc.target/powerpc/mma-builtin-6.c: I protest. * gcc.target/powerpc/notoc-direct-1.c: I protest. * gcc.target/powerpc/pcrel-sibcall-1.c: I protest. * gcc.target/powerpc/pdep-0.c: I protest. * gcc.target/powerpc/pdep-1.c: I protest. * gcc.target/powerpc/pextd-0.c: I protest. * gcc.target/powerpc/pextd-1.c: I protest. * gcc.target/powerpc/pr93122.c: I protest. * gcc.target/powerpc/pr94740.c: I protest. * gcc.target/powerpc/setbceq.c: I protest. * gcc.target/powerpc/setbcge.c: I protest. * gcc.target/powerpc/setbcgt.c: I protest. * gcc.target/powerpc/setbcle.c: I protest. * gcc.target/powerpc/setbclt.c: I protest. * gcc.target/powerpc/setbcne.c: I protest. * gcc.target/powerpc/setnbceq.c: I protest. * gcc.target/powerpc/setnbcge.c: I protest. * gcc.target/powerpc/setnbcgt.c: I protest. * gcc.target/powerpc/setnbcle.c: I protest. * gcc.target/powerpc/setnbclt.c: I protest. * gcc.target/powerpc/setnbcne.c: I protest. * gcc.target/powerpc/vec-cfuged-0.c: I protest. * gcc.target/powerpc/vec-cfuged-1.c: I protest. * gcc.target/powerpc/vec-clrl-0.c: I protest. * gcc.target/powerpc/vec-clrl-1.c: I protest. * gcc.target/powerpc/vec-clrl-2.c: I protest. * gcc.target/powerpc/vec-clrl-3.c: I protest. * gcc.target/powerpc/vec-clrr-0.c: I protest. * gcc.target/powerpc/vec-clrr-1.c: I protest. * gcc.target/powerpc/vec-clrr-2.c: I protest. * gcc.target/powerpc/vec-clrr-3.c: I protest. * gcc.target/powerpc/vec-cntlzm-0.c: I protest. * gcc.target/powerpc/vec-cntlzm-1.c: I protest. * gcc.target/powerpc/vec-cnttzm-0.c: I protest. * gcc.target/powerpc/vec-cnttzm-1.c: I protest. * gcc.target/powerpc/vec-extracth-0.c: I protest. * gcc.target/powerpc/vec-extracth-1.c: I protest. * gcc.target/powerpc/vec-extracth-2.c: I protest. * gcc.target/powerpc/vec-extracth-3.c: I protest. * gcc.target/powerpc/vec-extracth-4.c: I protest. * gcc.target/powerpc/vec-extracth-5.c: I protest. * gcc.target/powerpc/vec-extracth-6.c: I protest. * gcc.target/powerpc/vec-extracth-7.c: I protest. * gcc.target/powerpc/vec-extracth-be-0.c: I protest. * gcc.target/powerpc/vec-extracth-be-1.c: I protest. * gcc.target/powerpc/vec-extracth-be-2.c: I protest. * gcc.target/powerpc/vec-extracth-be-3.c: I protest. * gcc.target/powerpc/vec-extractl-0.c: I protest. * gcc.target/powerpc/vec-extractl-1.c: I protest. * gcc.target/powerpc/vec-extractl-2.c: I protest. * gcc.target/powerpc/vec-extractl-3.c: I protest. * gcc.target/powerpc/vec-extractl-4.c: I protest. * gcc.target/powerpc/vec-extractl-5.c: I protest. * gcc.target/powerpc/vec-extractl-6.c: I protest. * gcc.target/powerpc/vec-extractl-7.c: I protest. * gcc.target/powerpc/vec-extractl-be-0.c: I protest. * gcc.target/powerpc/vec-extractl-be-1.c: I protest. * gcc.target/powerpc/vec-extractl-be-2.c: I protest. * gcc.target/powerpc/vec-extractl-be-3.c: I protest. * gcc.target/powerpc/vec-gnb-0.c: I protest. * gcc.target/powerpc/vec-gnb-1.c: I protest. * gcc.target/powerpc/vec-gnb-2.c: I protest. * gcc.target/powerpc/vec-pdep-0.c: I protest. * gcc.target/powerpc/vec-pdep-1.c: I protest. * gcc.target/powerpc/vec-pext-0.c: I protest. * gcc.target/powerpc/vec-pext-1.c: I protest. * gcc.target/powerpc/vec-stril-0.c: I protest. * gcc.target/powerpc/vec-stril-1.c: I protest. * gcc.target/powerpc/vec-stril-10.c: I protest. * gcc.target/powerpc/vec-stril-11.c: I protest. * gcc.target/powerpc/vec-stril-12.c: I protest. * gcc.target/powerpc/vec-stril-13.c: I protest. * gcc.target/powerpc/vec-stril-14.c: I protest. * gcc.target/powerpc/vec-stril-15.c: I protest. * gcc.target/powerpc/vec-stril-16.c: I protest. * gcc.target/powerpc/vec-stril-17.c: I protest. * gcc.target/powerpc/vec-stril-18.c: I protest. * gcc.target/powerpc/vec-stril-19.c: I protest. * gcc.target/powerpc/vec-stril-2.c: I protest. * gcc.target/powerpc/vec-stril-20.c: I protest. * gcc.target/powerpc/vec-stril-21.c: I protest. * gcc.target/powerpc/vec-stril-22.c: I protest. * gcc.target/powerpc/vec-stril-23.c: I protest. * gcc.target/powerpc/vec-stril-3.c: I protest. * gcc.target/powerpc/vec-stril-4.c: I protest. * gcc.target/powerpc/vec-stril-5.c: I protest. * gcc.target/powerpc/vec-stril-6.c: I protest. * gcc.target/powerpc/vec-stril-7.c: I protest. * gcc.target/powerpc/vec-stril-8.c: I protest. * gcc.target/powerpc/vec-stril-9.c: I protest. * gcc.target/powerpc/vec-stril_p-0.c: I protest. * gcc.target/powerpc/vec-stril_p-1.c: I protest. * gcc.target/powerpc/vec-stril_p-10.c: I protest. * gcc.target/powerpc/vec-stril_p-11.c: I protest. * gcc.target/powerpc/vec-stril_p-2.c: I protest. * gcc.target/powerpc/vec-stril_p-3.c: I protest. * gcc.target/powerpc/vec-stril_p-4.c: I protest. * gcc.target/powerpc/vec-stril_p-5.c: I protest. * gcc.target/powerpc/vec-stril_p-6.c: I protest. * gcc.target/powerpc/vec-stril_p-7.c: I protest. * gcc.target/powerpc/vec-stril_p-8.c: I protest. * gcc.target/powerpc/vec-stril_p-9.c: I protest. * gcc.target/powerpc/vec-strir-0.c: I protest. * gcc.target/powerpc/vec-strir-1.c: I protest. * gcc.target/powerpc/vec-strir-10.c: I protest. * gcc.target/powerpc/vec-strir-11.c: I protest. * gcc.target/powerpc/vec-strir-12.c: I protest. * gcc.target/powerpc/vec-strir-13.c: I protest. * gcc.target/powerpc/vec-strir-14.c: I protest. * gcc.target/powerpc/vec-strir-15.c: I protest. * gcc.target/powerpc/vec-strir-16.c: I protest. * gcc.target/powerpc/vec-strir-17.c: I protest. * gcc.target/powerpc/vec-strir-18.c: I protest. * gcc.target/powerpc/vec-strir-19.c: I protest. * gcc.target/powerpc/vec-strir-2.c: I protest. * gcc.target/powerpc/vec-strir-20.c: I protest. * gcc.target/powerpc/vec-strir-21.c: I protest. * gcc.target/powerpc/vec-strir-22.c: I protest. * gcc.target/powerpc/vec-strir-23.c: I protest. * gcc.target/powerpc/vec-strir-3.c: I protest. * gcc.target/powerpc/vec-strir-4.c: I protest. * gcc.target/powerpc/vec-strir-5.c: I protest. * gcc.target/powerpc/vec-strir-6.c: I protest. * gcc.target/powerpc/vec-strir-7.c: I protest. * gcc.target/powerpc/vec-strir-8.c: I protest. * gcc.target/powerpc/vec-strir-9.c: I protest. * gcc.target/powerpc/vec-strir_p-0.c: I protest. * gcc.target/powerpc/vec-strir_p-1.c: I protest. * gcc.target/powerpc/vec-strir_p-10.c: I protest. * gcc.target/powerpc/vec-strir_p-11.c: I protest. * gcc.target/powerpc/vec-strir_p-2.c: I protest. * gcc.target/powerpc/vec-strir_p-3.c: I protest. * gcc.target/powerpc/vec-strir_p-4.c: I protest. * gcc.target/powerpc/vec-strir_p-5.c: I protest. * gcc.target/powerpc/vec-strir_p-6.c: I protest. * gcc.target/powerpc/vec-strir_p-7.c: I protest. * gcc.target/powerpc/vec-strir_p-8.c: I protest. * gcc.target/powerpc/vec-strir_p-9.c: I protest. * gcc.target/powerpc/vec-ternarylogic-0.c: I protest. * gcc.target/powerpc/vec-ternarylogic-1.c: I protest. * gcc.target/powerpc/vec-ternarylogic-10.c: I protest. * gcc.target/powerpc/vec-ternarylogic-2.c: I protest. * gcc.target/powerpc/vec-ternarylogic-3.c: I protest. * gcc.target/powerpc/vec-ternarylogic-4.c: I protest. * gcc.target/powerpc/vec-ternarylogic-5.c: I protest. * gcc.target/powerpc/vec-ternarylogic-6.c: I protest. * gcc.target/powerpc/vec-ternarylogic-7.c: I protest. * gcc.target/powerpc/vec-ternarylogic-8.c: I protest. * gcc.target/powerpc/vec-ternarylogic-9.c: I protest. * gcc.target/powerpc/xxgenpc-runnable.c: I protest. * lib/target-supports.exp: Stuff.
2020-06-22rs6000: Rename future to power10Segher Boessenkool20-792/+787
This renames the command line options, the internal names, and mentions in the comments, from "future" to "power10". Also, the file "future.md" is renamed. The predefined user macro _ARCH_PWR_FUTURE is renamed to _ARCH_PWR10. "Future architecture" is renamed to "ISA 3.1". 2020-06-22 Segher Boessenkool <segher@kernel.crashing.org> gcc/ChangeLog: * config/rs6000/altivec.h: Use _ARCH_PWR10, not _ARCH_PWR_FUTURE. Update comment for ISA 3.1. * config/rs6000/altivec.md: Use TARGET_POWER10, not TARGET_FUTURE. * config/rs6000/driver-rs6000.c (asm_names): Use -mpwr10 for power10 on AIX, and -mpower10 elsewhere. * config/rs6000/future.md: Delete. * config/rs6000/linux64.h: Update comments. Use TARGET_POWER10, not TARGET_FUTURE. * config/rs6000/power10.md: New file. * config/rs6000/ppc-auxv.h: Use PPC_PLATFORM_POWER10, not PPC_PLATFORM_FUTURE. * config/rs6000/rs6000-builtin.def: Update comments. Use BU_P10V_* names instead of BU_FUTURE_V_* names. Use RS6000_BTM_P10 instead of RS6000_BTM_FUTURE. Use P10_BUILTIN_* instead of FUTURE_BUILTIN_*. Use BU_P10_* instead of BU_FUTURE_*. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define _ARCH_PWR10 instead of _ARCH_PWR_FUTURE. (altivec_resolve_overloaded_builtin): Use P10_BUILTIN_VEC_XXEVAL, not FUTURE_BUILTIN_VEC_XXEVAL. * config/rs6000/rs6000-call.c: Use P10_BUILTIN_*, not FUTURE_BUILTIN_*. Update compiler messages. * config/rs6000/rs6000-cpus.def: Update comments. Use ISA_3_1_*, not ISA_FUTURE_*. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. * config/rs6000/rs6000-opts.h: Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. * config/rs6000/rs6000-string.c: Ditto. * config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Use "power10" instead of "future", reorder it to right after "power9". * config/rs6000/rs6000.c: Update comments. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use TARGET_POWER10, not TARGET_FUTURE. Use RS6000_BTM_P10, not RS6000_BTM_FUTURE. Update compiler messages. Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. Use ISA_3_1_MASKS_SERVER, not ISA_FUTURE_MASKS_SERVER. (rs6000_opt_masks): Use "power10" instead of "future". (rs6000_builtin_mask_names): Ditto. (rs6000_disable_incompatible_switches): Ditto. * config/rs6000/rs6000.h: Use -mpower10, not -mfuture. Use -mcpu=power10, not -mcpu=future. Use MASK_POWER10, not MASK_FUTURE. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use RS6000_BTM_P10, not RS6000_BTM_FUTURE. * config/rs6000/rs6000.md: Use "power10", not "future". Use TARGET_POWER10, not TARGET_FUTURE. Include "power10.md", not "future.md". * config/rs6000/rs6000.opt (mfuture): Delete. (mpower10): New. * config/rs6000/t-rs6000: Use "power10.md", not "future.md". * config/rs6000/vsx.md: Use TARGET_POWER10, not TARGET_FUTURE.
2020-06-22Update gcc sv.po.Joseph Myers1-590/+388
* sv.po: Update.
2020-06-22recog: Restore builds with ClangRichard Sandiford2-5/+1
Using parameter packs with function typedefs tripped a Clang bug in which the packs were not being expanded correctly: https://bugs.llvm.org/show_bug.cgi?id=46377 Work around that by going back to the decltype approach, but adding a cast to void to suppress a warning about unused values. 2020-06-22 Richard Sandiford <richard.sandiford@arm.com> gcc/ * coretypes.h (first_type): Delete. * recog.h (insn_gen_fn::operator()): Go back to using a decltype.
2020-06-22arm: Fix the failing mve scalar shift execution tests.Srinath Parvathaneni6-4/+31
In GCC testsuite the MVE scalar shift execution tests (mve_scalar_shifts[1-4].c) are failings because of executing them on target hardware which doesn't support MVE instructions. This patch restricts those tests to execute only on target hardware that support MVE instructions. 2020-06-22 Srinath Parvathaneni <srinath.parvathaneni@arm.com> gcc/ * doc/sourcebuild.texi (arm_v8_1m_mve_fp_ok): Add item. (arm_mve_hw): Likewise. gcc/testsuite/ * gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: Modify. * gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise. * gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise. * lib/target-supports.exp (check_effective_target_arm_mve_hw): Define.
2020-06-22Fortran : ICE in resolve_fl_procedure PR95708Mark Eggleston3-3/+10
Now issues an error "Intrinsic procedure 'num_images' not allowed in PROCEDURE" instead of an ICE. 2020-06-22 Steven G. Kargl <kargl@gcc.gnu.org> gcc/fortran/ PR fortran/95708 * intrinsic.c (add_functions): Replace CLASS_INQUIRY with CLASS_TRANSFORMATIONAL for intrinsic num_images. (make_generic): Replace ACTUAL_NO with ACTUAL_YES for intrinsic team_number. * resolve.c (resolve_fl_procedure): Check pointer ts.u.derived exists before using it. 2020-06-22 Mark Eggleston <markeggleston@gcc.gnu.org> gcc/testsuite/ PR fortran/95708 * gfortran.dg/pr95708.f90: New test.
2020-06-22x86: Skip EXT_REX_SSE_REG_P for vzeroupper optimizationH.J. Lu2-1/+13
Skip EXT_REX_SSE_REG_P for vzeroupper optimization since upper 16 vector registers don't trigger SSE <-> AVX transition penalty. gcc/ PR target/95791 * config/i386/i386.c (ix86_dirflag_mode_needed): Skip EXT_REX_SSE_REG_P. gcc/testsuite/ PR target/95791 * gcc.target/i386/pr95791.c: New test.
2020-06-22Fortran : ICE in gfc_check_reshape PR95585Mark Eggleston2-1/+8
Issue an error where an array is used before its definition instead of an ICE. 2020-06-22 Steven G. Kargl <kargl@gcc.gnu.org> gcc/fortran/ PR fortran/95585 * check.c (gfc_check_reshape): Add check for a value when the symbol has an attribute flavor FL_PARAMETER. 2020-06-22 Mark Eggleston <markeggleston@gcc.gnu.org> gcc/testsuite/ PR fortran/95585 * gfortran.dg/pr95585.f90: New test.
2020-06-22Fortran : Missing gcc-internal-format PR42693Mark Eggleston1-10/+9
Messages in gfc_arith_error contain gcc internal format specifiers which should be enclosed in G_() in order to be correctly translated. 2020-06-22 Mark Eggleston <markeggleston@gcc.gnu.org> gcc/fortran/ PR fortran/42693 * arith.c (gfc_arith_error): Enclose strings in G_() instead of _().
2020-06-22tree-optimization/95770 - fix SLP vectorized stmt placement computeRichard Biener2-3/+24
This fixes the vectorized stmt placement compute for the case of external defs. 2020-06-22 Richard Biener <rguenther@suse.de> PR tree-optimization/95770 * tree-vect-slp.c (vect_schedule_slp_instance): Also consider external defs. * gcc.dg/pr95770.c: New testcase.
2020-06-22amdgcn: Pass vector parameters in memoryAndrew Stubbs1-0/+8
gcc/ChangeLog: * config/gcn/gcn.c (gcn_function_arg): Disallow vector arguments. (gcn_return_in_memory): Return vectors in memory.
2020-06-22openmp: Compute triangular loop number of iterations at compile timeJakub Jelinek1-25/+201
2020-06-22 Jakub Jelinek <jakub@redhat.com> * omp-general.c (omp_extract_for_data): For triangular loops with all loop invariant expressions constant where the innermost loop is executed at least once compute number of iterations at compile time.
2020-06-22RISC-V: Normalize arch string in driver timeKito Cheng1-1/+5
- Normalize arch string would help the multi-lib handling, e.g. rv64gc and rv64g_c are both valid and same arch, but latter one would confuse the detection of multi-lib, earlier normalize can resolve this issue. gcc/ChangeLog: * config/riscv/riscv.h (ASM_SPEC): Remove riscv_expand_arch call. (DRIVER_SELF_SPECS): New.
2020-06-22RISC-V: Fix compilation failed for frflags builtin in C++ modeKito Cheng3-2/+12
- g++ will complain too few arguments for frflags builtin like bellow message: error: too few arguments to function 'unsigned int __builtin_riscv_frflags(void)' - However it's no arguments needed, it because we declare the function type with VOID arguments, that seems like require a VOID argument in the c++ front-end when GCC tried to resolve the function. gcc/ChangeLog * config/riscv/riscv-builtins.c (RISCV_FTYPE_NAME0): New. (RISCV_FTYPE_ATYPES0): New. (riscv_builtins): Using RISCV_USI_FTYPE for frflags. * config/riscv/riscv-ftypes.def: Remove VOID argument. gcc/testsuite/ChangeLog * g++.target/riscv/frflags.C: New.
2020-06-22Daily bump.GCC Administrator8-1/+243
2020-06-21aix: Add GCC64 configuration and FAT target libraries.David Edelsohn31-75/+425
This patch adds the ability to configure GCC on AIX to build as a 64 bit application and to build target libraries "FAT" libraries in both 32 bit and 64 bit mode. The patch adds makefile fragment hooks to target libraries that allows them to include target-specific rules. The target specific rules for AIX place both 32 bit and 64 bit objects and shared objects in archives at the top-level, not multilib subdirectories. The multilibs are built in subdirectories, but must be combined during the last parts of the target library build process. Because of the way that GCC bootstrap works, the libraries must be combined during the multiple stages of GCC bootstrap, not solely when installed in the final destination, so the libraries are correct at the end of each target library build stage, not solely an install recipe. gcc/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * config.gcc: Use t-aix64, biarch64 and default64 for cpu_is_64bit. * config/rs6000/aix72.h (ASM_SPEC): Remove aix64 option. (ASM_SPEC32): New. (ASM_SPEC64): New. (ASM_CPU_SPEC): Remove vsx and altivec options. (CPP_SPEC_COMMON): Rename from CPP_SPEC. (CPP_SPEC32): New. (CPP_SPEC64): New. (CPLUSPLUS_CPP_SPEC): Rename to CPLUSPLUS_CPP_SPEC_COMMON.. (TARGET_DEFAULT): Only define if not BIARCH. (LIB_SPEC_COMMON): Rename from LIB_SPEC. (LIB_SPEC32): New. (LIB_SPEC64): New. (LINK_SPEC_COMMON): Rename from LINK_SPEC. (LINK_SPEC32): New. (LINK_SPEC64): New. (STARTFILE_SPEC): Add 64 bit version of crtcxa and crtdbase. (ASM_SPEC): Define 32 and 64 bit alternatives using DEFAULT_ARCH64_P. (CPP_SPEC): Same. (CPLUSPLUS_CPP_SPEC): Same. (LIB_SPEC): Same. (LINK_SPEC): Same. (SUBTARGET_EXTRA_SPECS): Add new 32/64 specs. * config/rs6000/defaultaix64.h: New file. * config/rs6000/t-aix64: New file. libgcc/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * config.host (extra_parts): Add crtcxa_64 and crtdbase_64. * config/rs6000/t-aix-cxa: Explicitly compile 32 bit with -maix32 and 64 bit with -maix64. * config/rs6000/t-slibgcc-aix: Remove extra @multilib_dir@ level. Build and install AIX-style FAT libraries. libgomp/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * Makefile.am (tmake_file): Build and install AIX-style FAT libraries. * Makefile.in: Regenerate * configure.ac (tmake_file): Substitute. * configure: Regenerate. * configure.tgt (powerpc-ibm-aix*): Define tmake_file. * config/t-aix: New file. libstdc++-v3/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * Makefile.am (tmake_file): Build and install AIX-style FAT libraries. * Makefile.in: Regenerate. * configure.ac (tmake_file): Substitute. * configure: Regenerate. * configure.host (aix*): Define tmake_file. * config/os/aix/t-aix: New file. libatomic/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * Makefile.am (tmake_file): Build and install AIX-style FAT libraries. * Makefile.in: Regenerate. * configure.ac (tmake_file): Substitute. * configure: Regenerate. * configure.tgt (powerpc-ibm-aix*): Define tmake_file. * config/t-aix: New file. libgfortran/ChangeLog 2020-06-21 David Edelsohn <dje.gcc@gmail.com> * Makefile.am (tmake_file): Build and install AIX-style FAT libraries. * Makefile.in: Regenerate. * configure.ac (tmake_file): Substitute. * configure: Regenerate. * configure.host: Add system configury stanza. Define tmake_file. * config/t-aix: New file.
2020-06-21rs6000: Add MMA built-in function definitions and test cases.Peter Bergner15-24/+1813
Add the Matrix-Multiply Assist (MMA) built-ins. The MMA accumulators are INOUT operands for most MMA instructions, but they are also very expensive to move around. For this reason, we have implemented a built-in API where the accumulators are passed using pass-by-reference/pointers, so the user won't use one accumulator as input and another as output, which wouldentail a lot of copies. However, using pointers gives us poor code generation when we expand the built-ins at normal expand time. We therefore expand the MMA built-ins early into gimple, converting the pass-by-reference calls to an internal built-in that uses pass-by-value calling convention, where we can enforce the input and output accumulators are the same. This gives us much better code generation. 2020-06-20 Peter Bergner <bergner@linux.ibm.com> gcc/ * config/rs6000/predicates.md (mma_assemble_input_operand): New. * config/rs6000/rs6000-builtin.def (BU_MMA_1, BU_MMA_V2, BU_MMA_3, BU_MMA_5, BU_MMA_6, BU_VSX_1): Add support macros for defining MMA built-in functions. (ASSEMBLE_ACC, ASSEMBLE_PAIR, DISASSEMBLE_ACC, DISASSEMBLE_PAIR, PMXVBF16GER2, PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVF16GER2, PMXVF16GER2NN, PMXVF16GER2NP, PMXVF16GER2PN, PMXVF16GER2PP, PMXVF32GER, PMXVF32GERNN, PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF64GER, PMXVF64GERNN, PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVI16GER2, PMXVI16GER2PP, PMXVI16GER2S, PMXVI16GER2SPP, PMXVI4GER8, PMXVI4GER8PP, PMXVI8GER4, PMXVI8GER4PP, PMXVI8GER4SPP, XVBF16GER2, XVBF16GER2NN, XVBF16GER2NP, XVBF16GER2PN, XVBF16GER2PP, XVCVBF16SP, XVCVSPBF16, XVF16GER2, XVF16GER2NN, XVF16GER2NP, XVF16GER2PN, XVF16GER2PP, XVF32GER, XVF32GERNN, XVF32GERNP, XVF32GERPN, XVF32GERPP, XVF64GER, XVF64GERNN, XVF64GERNP, XVF64GERPN, XVF64GERPP, XVI16GER2, XVI16GER2PP, XVI16GER2S, XVI16GER2SPP, XVI4GER8, XVI4GER8PP, XVI8GER4, XVI8GER4PP, XVI8GER4SPP, XXMFACC, XXMTACC, XXSETACCZ): Add MMA built-ins. * config/rs6000/rs6000.c (rs6000_emit_move): Use CONST_INT_P. Allow zero constants. (print_operand) <case 'A'>: New output modifier. (rs6000_split_multireg_move): Add support for inserting accumulator priming and depriming instructions. Add support for splitting an assemble accumulator pattern. * config/rs6000/rs6000-call.c (mma_init_builtins, mma_expand_builtin, rs6000_gimple_fold_mma_builtin): New functions. (RS6000_BUILTIN_M): New macro. (def_builtin): Handle RS6000_BTC_QUAD and RS6000_BTC_PAIR attributes. (bdesc_mma): Add new MMA built-in support. (htm_expand_builtin): Use RS6000_BTC_OPND_MASK. (rs6000_invalid_builtin): Add handling of RS6000_BTM_FUTURE and RS6000_BTM_MMA. (rs6000_builtin_valid_without_lhs): Handle RS6000_BTC_VOID attribute. (rs6000_gimple_fold_builtin): Call rs6000_builtin_is_supported_p and rs6000_gimple_fold_mma_builtin. (rs6000_expand_builtin): Call mma_expand_builtin. Use RS6000_BTC_OPND_MASK. (rs6000_init_builtins): Adjust comment. Call mma_init_builtins. (htm_init_builtins): Use RS6000_BTC_OPND_MASK. (builtin_function_type): Handle VSX_BUILTIN_XVCVSPBF16 and VSX_BUILTIN_XVCVBF16SP. * config/rs6000/rs6000.h (RS6000_BTC_QUINARY, RS6000_BTC_SENARY, RS6000_BTC_OPND_MASK, RS6000_BTC_QUAD, RS6000_BTC_PAIR, RS6000_BTC_QUADPAIR, RS6000_BTC_GIMPLE): New defines. (RS6000_BTC_PREDICATE, RS6000_BTC_ABS, RS6000_BTC_DST, RS6000_BTC_TYPE_MASK, RS6000_BTC_ATTR_MASK): Adjust values. * config/rs6000/mma.md (MAX_MMA_OPERANDS): New define_constant. (UNSPEC_MMA_ASSEMBLE_ACC, UNSPEC_MMA_PMXVBF16GER2, UNSPEC_MMA_PMXVBF16GER2NN, UNSPEC_MMA_PMXVBF16GER2NP, UNSPEC_MMA_PMXVBF16GER2PN, UNSPEC_MMA_PMXVBF16GER2PP, UNSPEC_MMA_PMXVF16GER2, UNSPEC_MMA_PMXVF16GER2NN, UNSPEC_MMA_PMXVF16GER2NP, UNSPEC_MMA_PMXVF16GER2PN, UNSPEC_MMA_PMXVF16GER2PP, UNSPEC_MMA_PMXVF32GER, UNSPEC_MMA_PMXVF32GERNN, UNSPEC_MMA_PMXVF32GERNP, UNSPEC_MMA_PMXVF32GERPN, UNSPEC_MMA_PMXVF32GERPP, UNSPEC_MMA_PMXVF64GER, UNSPEC_MMA_PMXVF64GERNN, UNSPEC_MMA_PMXVF64GERNP, UNSPEC_MMA_PMXVF64GERPN, UNSPEC_MMA_PMXVF64GERPP, UNSPEC_MMA_PMXVI16GER2, UNSPEC_MMA_PMXVI16GER2PP, UNSPEC_MMA_PMXVI16GER2S, UNSPEC_MMA_PMXVI16GER2SPP, UNSPEC_MMA_PMXVI4GER8, UNSPEC_MMA_PMXVI4GER8PP, UNSPEC_MMA_PMXVI8GER4, UNSPEC_MMA_PMXVI8GER4PP, UNSPEC_MMA_PMXVI8GER4SPP, UNSPEC_MMA_XVBF16GER2, UNSPEC_MMA_XVBF16GER2NN, UNSPEC_MMA_XVBF16GER2NP, UNSPEC_MMA_XVBF16GER2PN, UNSPEC_MMA_XVBF16GER2PP, UNSPEC_MMA_XVF16GER2, UNSPEC_MMA_XVF16GER2NN, UNSPEC_MMA_XVF16GER2NP, UNSPEC_MMA_XVF16GER2PN, UNSPEC_MMA_XVF16GER2PP, UNSPEC_MMA_XVF32GER, UNSPEC_MMA_XVF32GERNN, UNSPEC_MMA_XVF32GERNP, UNSPEC_MMA_XVF32GERPN, UNSPEC_MMA_XVF32GERPP, UNSPEC_MMA_XVF64GER, UNSPEC_MMA_XVF64GERNN, UNSPEC_MMA_XVF64GERNP, UNSPEC_MMA_XVF64GERPN, UNSPEC_MMA_XVF64GERPP, UNSPEC_MMA_XVI16GER2, UNSPEC_MMA_XVI16GER2PP, UNSPEC_MMA_XVI16GER2S, UNSPEC_MMA_XVI16GER2SPP, UNSPEC_MMA_XVI4GER8, UNSPEC_MMA_XVI4GER8PP, UNSPEC_MMA_XVI8GER4, UNSPEC_MMA_XVI8GER4PP, UNSPEC_MMA_XVI8GER4SPP, UNSPEC_MMA_XXMFACC, UNSPEC_MMA_XXMTACC): New. (MMA_ACC, MMA_VV, MMA_AVV, MMA_PV, MMA_APV, MMA_VVI4I4I8, MMA_AVVI4I4I8, MMA_VVI4I4I2, MMA_AVVI4I4I2, MMA_VVI4I4, MMA_AVVI4I4, MMA_PVI4I2, MMA_APVI4I2, MMA_VVI4I4I4, MMA_AVVI4I4I4): New define_int_iterator. (acc, vv, avv, pv, apv, vvi4i4i8, avvi4i4i8, vvi4i4i2, avvi4i4i2, vvi4i4, avvi4i4, pvi4i2, apvi4i2, vvi4i4i4, avvi4i4i4): New define_int_attr. (*movpxi): Add zero constant alternative. (mma_assemble_pair, mma_assemble_acc): New define_expand. (*mma_assemble_acc): New define_insn_and_split. (mma_<acc>, mma_xxsetaccz, mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>, mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>, mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>, mma_<vvi4i4i4>, mma_<avvi4i4i4>): New define_insn. * config/rs6000/rs6000.md (define_attr "type"): New type mma. * config/rs6000/vsx.md (UNSPEC_VSX_XVCVBF16SP): New. (UNSPEC_VSX_XVCVSPBF16): Likewise. (XVCVBF16): New define_int_iterator. (xvcvbf16): New define_int_attr. (vsx_<xvcvbf16>): New define_insn. * doc/extend.texi: Document the mma built-ins.
2020-06-21rs6000: Add base support and types for defining MMA built-ins.Peter Bergner11-32/+408
Add the new -mmma option as well as the initial MMA support, which includes the target specific __vector_pair and __vector_quad types, the POImode and PXImode partial integer modes they are mapped to, and their associated move patterns. Support for the restrictions on the registers these modes can be assigned to as also been added. 2020-06-20 Peter Bergner <bergner@linux.ibm.com> Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/mma.md: New file. * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define __MMA__ for mma. * config/rs6000/rs6000-call.c (rs6000_init_builtins): Add support for __vector_pair and __vector_quad types. * config/rs6000/rs6000-cpus.def (OTHER_FUTURE_MASKS): Add OPTION_MASK_MMA. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000-modes.def (OI, XI): New integer modes. (POI, PXI): New partial integer modes. * config/rs6000/rs6000.c (TARGET_INVALID_CONVERSION): Define. (rs6000_hard_regno_nregs_internal): Use VECTOR_ALIGNMENT_P. (rs6000_hard_regno_mode_ok_uncached): Likewise. Add support for POImode being allowed in VSX registers and PXImode being allowed in FP registers. (rs6000_modes_tieable_p): Adjust comment. Add support for POImode and PXImode. (rs6000_debug_reg_global) <print_tieable_modes>: Add OImode, POImode XImode, PXImode, V2SImode, V2SFmode and CCFPmode.. (rs6000_setup_reg_addr_masks): Use VECTOR_ALIGNMENT_P. Set up appropriate addr_masks for vector pair and vector quad addresses. (rs6000_init_hard_regno_mode_ok): Add support for vector pair and vector quad registers. Setup reload handlers for POImode and PXImode. (rs6000_builtin_mask_calculate): Add support for RS6000_BTM_MMA. (rs6000_option_override_internal): Error if -mmma is specified without -mcpu=future. (rs6000_slow_unaligned_access): Use VECTOR_ALIGNMENT_P. (quad_address_p): Change size test to less than 16 bytes. (reg_offset_addressing_ok_p): Add support for ISA 3.1 vector pair and vector quad instructions. (avoiding_indexed_address_p): Likewise. (rs6000_emit_move): Disallow POImode and PXImode moves involving constants. (rs6000_preferred_reload_class): Prefer VSX registers for POImode and FP registers for PXImode. (rs6000_split_multireg_move): Support splitting POImode and PXImode move instructions. (rs6000_mangle_type): Adjust comment. Add support for mangling __vector_pair and __vector_quad types. (rs6000_opt_masks): Add entry for mma. (rs6000_builtin_mask_names): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE. (rs6000_function_value): Use VECTOR_ALIGNMENT_P. (address_to_insn_form): Likewise. (reg_to_non_prefixed): Likewise. (rs6000_invalid_conversion): New function. * config/rs6000/rs6000.h (MASK_MMA): Define. (BIGGEST_ALIGNMENT): Set to 512 if MMA support is enabled. (VECTOR_ALIGNMENT_P): New helper macro. (ALTIVEC_VECTOR_MODE): Use VECTOR_ALIGNMENT_P. (RS6000_BTM_MMA): Define. (RS6000_BTM_COMMON): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE. (rs6000_builtin_type_index): Add RS6000_BTI_vector_pair and RS6000_BTI_vector_quad. (vector_pair_type_node): New. (vector_quad_type_node): New. * config/rs6000/rs6000.md: Include mma.md. (define_mode_iterator RELOAD): Add POI and PXI. * config/rs6000/t-rs6000 (MD_INCLUDES): Add mma.md. * config/rs6000/rs6000.opt (-mmma): New. * doc/invoke.texi: Document -mmma.
2020-06-21Daily bump.GCC Administrator6-1/+105
2020-06-20coroutines: Update handling and failure for g-r-o-o-a-f [PR95505]Iain Sandoe2-26/+51
The actual issue is that (in the testcase) std::nothrow is not available. So update the handling of the get-return-on-alloc-fail to include the possibility that std::nothrow might not be available. gcc/cp/ChangeLog: PR c++/95505 * coroutines.cc (morph_fn_to_coro): Update handling of get-return-object-on-allocation-fail and diagnose missing std::nothrow. gcc/testsuite/ChangeLog: PR c++/95505 * g++.dg/coroutines/pr95505.C: New test.
2020-06-20c++: Refinements to "more constrained".Jason Merrill7-48/+57
P2113 from the last C++ meeting clarified that we only compare constraints on functions or function templates that have equivalent template parameters and function parameters. I'm not currently implementing the complicated handling of reversed comparison operators here; thinking about it now, it seems like a lot of complexity to support a very weird usage. If I write two similar comparison operators to be distinguished by their constraints, why would I write one reversed? If they're two unrelated operators, they're very unlikely to be similar enough for the complexity to help. I've started a discussion on the committee reflector about changing these rules. This change breaks some greedy_ops tests in libstdc++ that were relying on comparing constraints on unrelated templates, which seems pretty clearly wrong, so I'm removing those tests for now. gcc/cp/ChangeLog: * call.c (joust): Only compare constraints for non-template candidates with matching parameters. * pt.c (tsubst_pack_expansion): Fix getting a type parameter pack. (more_specialized_fn): Only compare constraints for candidates with matching parameters. gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-return-req1.C: Expect error. * g++.dg/cpp2a/concepts-p2113a.C: New test. * g++.dg/cpp2a/concepts-p2113b.C: New test. libstdc++-v3/ChangeLog: * testsuite/24_iterators/move_iterator/rel_ops_c++20.cc: Remove greedy_ops tests. * testsuite/24_iterators/reverse_iterator/rel_ops_c++20.cc: Remove greedy_ops tests.
2020-06-20PR fortran/95707 - ICE in finish_equivalences, at fortran/trans-common.c:1319Harald Anlauf3-5/+23
With submodules and equivalence declarations, name mangling may result in long internal symbols overflowing internal buffers. We now check that we do not exceed the enlarged buffer sizes. gcc/fortran/ PR fortran/95707 * gfortran.h (gfc_common_head): Enlarge buffer. * trans-common.c (gfc_sym_mangled_common_id): Enlarge temporary buffers, and add check on length on mangled name to prevent overflow.
2020-06-20PR fortran/95688 - ICE in gfc_get_string, at fortran/iresolve.c:70Harald Anlauf2-2/+17
With submodules, name mangling of character pointer declarations produces long internal symbols that overflowed a static internal buffer. Adjust the buffer size. gcc/fortran/ PR fortran/95688 * iresolve.c (gfc_get_string): Enlarge static buffer size.
2020-06-20PR fortran/95687 - ICE in get_unique_hashed_string, at fortran/class.c:508Harald Anlauf2-14/+48
With submodules and PDTs, name mangling of interfaces may result in long internal symbols overflowing a previously static internal buffer. We now set the buffer size dynamically. gcc/fortran/ PR fortran/95687 * class.c (get_unique_type_string): Return a string with dynamic length. (get_unique_hashed_string, gfc_hash_value): Use dynamic result from get_unique_type_string instead of static buffer.
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