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2023-05-07Daily bump.GCC Administrator5-1/+220
2023-05-06Delete duplicated riscv definition.Jeff Law1-38/+0
gcc/ * config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): Delete.
2023-05-06RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2.Michael Collison1-2/+5
While working on autovectorizing for the RISCV port I encountered an issue where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode), where GET_MODE_NUNITS is equal to one. Tested on RISCV and x86_64-linux-gnu. Okay? gcc/ * tree-vect-slp.cc (can_duplicate_and_interleave_p): Check that GET_MODE_NUNITS is a multiple of 2.
2023-05-06RISC-V:autovec: Add target vectorization hooksMichael Collison1-0/+116
gcc/ * config/riscv/riscv.cc (riscv_estimated_poly_value): Implement TARGET_ESTIMATED_POLY_VALUE. (riscv_preferred_simd_mode): Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. (riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE. (riscv_empty_mask_is_expensive): Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. (riscv_vectorize_create_costs): Implement TARGET_VECTORIZE_CREATE_COSTS. (riscv_support_vector_misalignment): Implement TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT. (TARGET_ESTIMATED_POLY_VALUE): Register target macro. (TARGET_VECTORIZE_GET_MASK_MODE): Ditto. (TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto. (TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Ditto.
2023-05-06Remove duplicated definition in risc-v vector support.Jeff Law1-11/+0
gcc/ * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Remove duplicate definition.
2023-05-06RISC-V:autovec: Add auto-vectorization support functionsMichael Collison1-8/+93
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): New function. (riscv_vector_preferred_simd_mode): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto.
2023-05-06RISC-V: autovec: Export policy functions to global scopeMichael Collison2-2/+5
gcc/ * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred): Remove static declaration to to make externally visible. (get_mask_policy_for_pred): Ditto. * config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred): New external declaration. (get_mask_policy_for_pred): Ditto.
2023-05-06RISC-V: autovec: Add new predicates and function prototypesMichael Collison1-0/+4
gcc/ * config/riscv/riscv-protos.h (riscv_vector_mask_mode_p): New. (riscv_vector_get_mask_mode): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto.
2023-05-07LoongArch: Enable shrink wrappingXi Ruoyao3-3/+197
This commit implements the target macros for shrink wrapping of function prologues/epilogues shrink wrapping on LoongArch. Bootstrapped and regtested on loongarch64-linux-gnu. I don't have an access to SPEC CPU so I hope the reviewer can perform a benchmark to see if there is real benefit. gcc/ChangeLog: * config/loongarch/loongarch.h (struct machine_function): Add reg_is_wrapped_separately array for register wrapping information. * config/loongarch/loongarch.cc (loongarch_get_separate_components): New function. (loongarch_components_for_bb): Likewise. (loongarch_disqualify_components): Likewise. (loongarch_process_components): Likewise. (loongarch_emit_prologue_components): Likewise. (loongarch_emit_epilogue_components): Likewise. (loongarch_set_handled_components): Likewise. (TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS): Define. (TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB): Likewise. (TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS): Likewise. (TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS): Likewise. (TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS): Likewise. (TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS): Likewise. (loongarch_for_each_saved_reg): Skip registers that are wrapped separately. gcc/testsuite/ChangeLog: * gcc.target/loongarch/shrink-wrap.c: New test.
2023-05-07build: Use -nostdinc generating macro_list [PR109522]Xi Ruoyao1-1/+1
This prevents a spurious message building a cross-compiler when target libc is not installed yet: cc1: error: no include path in which to search for stdc-predef.h As stdc-predef.h was added to define __STDC_* macros by libc, it's unlikely the header will ever contain some bad definitions w/o "__" prefix so it should be safe. gcc/ChangeLog: PR other/109522 * Makefile.in (s-macro_list): Pass -nostdinc to $(GCC_FOR_TARGET).
2023-05-06RISC-V: Enable basic RVV auto-vectorization support.Juzhe-Zhong39-2/+559
gcc/ChangeLog: * config/riscv/riscv-protos.h (preferred_simd_mode): New function. * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto. (preferred_simd_mode): Ditto. * config/riscv/riscv.cc (riscv_get_arg_info): Handle RVV type in function arg. (riscv_convert_vector_bits): Adjust for RVV auto-vectorization. (riscv_preferred_simd_mode): New function. (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): New target hook support. * config/riscv/vector.md: Add autovec.md. * config/riscv/autovec.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add testcases for RVV auto-vectorization. * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: New test. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: New test. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h: New test. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: New test. * gcc.target/riscv/rvv/autovec/scalable-1.c: New test. * gcc.target/riscv/rvv/autovec/template-1.h: New test. * gcc.target/riscv/rvv/autovec/v-1.c: New test. * gcc.target/riscv/rvv/autovec/v-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32f-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32f-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32f-3.c: New test. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32x-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32x-2.c: New test. * gcc.target/riscv/rvv/autovec/zve32x-3.c: New test. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64d-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64d-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64d-3.c: New test. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64f-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64f-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64f-3.c: New test. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64x-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64x-2.c: New test. * gcc.target/riscv/rvv/autovec/zve64x-3.c: New test. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: New test. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: New test.
2023-05-06libffi: fix handling of homogeneous float128 structs (#689)Dan Horák1-1/+1
If there is a homogeneous struct with float128 members, they should be copied to vector register save area. The current code incorrectly copies only the value of the first member, not increasing the pointer with each iteration. Fix this. Merged from upstream libffi commit: 464b4b66e3cf3b5489e730c1466ee1bf825560e0 2023-05-03 Dan Horák <dan@danny.cz> libffi/ PR libffi/109447 * src/powerpc/ffi_linux64.c (ffi_prep_args64): Update arg.f128 pointer.
2023-05-06Fortran: Namelist read with invalid input accepted.Jerry DeLisle2-1/+20
PR fortran/109662 libgfortran/ChangeLog: * io/list_read.c: Add a check for a comma after a namelist name in read input. Issue a runtime error message. gcc/testsuite/ChangeLog: * gfortran.dg/pr109662.f90: New test.
2023-05-06gimple-range-op: Improve handling of sin/cos rangesJakub Jelinek4-17/+178
Similarly to the earlier sqrt patch, this patch attempts to improve sin/cos ranges. As the functions are periodic, for the reverse range there is not much we can do (but I've discovered I forgot to take into account the boundary ulps for the discovery of impossible result ranges). For fold_range, we can do something only if the range is narrow enough (narrower than 2*pi). The patch computes the value of the functions (taking ulps into account) and also computes the derivative to find out if the function is growing or declining on the boundaries and from that it figures out if the result range should be [min (fn (lb), fn (ub)), max (fn (lb), fn (ub))] or if it needs to be extended to 1 (actually using +Inf) and/or -1 (actually using -Inf) because there must be a local minimum and/or maximum in the range. 2023-05-06 Jakub Jelinek <jakub@redhat.com> * real.h (dconst_pi): Define. (dconst_e_ptr): Formatting fix. (dconst_pi_ptr): Declare. * real.cc (dconst_pi_ptr): New function. * gimple-range-op.cc (cfn_sincos::fold_range): Intersect the generic boundaries range with range computed from sin/cos of the particular bounds if the argument range is shorter than 2*pi. (cfn_sincos::op1_range): Take bulps into account when determining which result ranges are always invalid or behave like known NAN. * gcc.dg/tree-ssa/range-sincos-2.c: New test.
2023-05-06Remove type from vrange_storage::equal_p.Aldy Hernandez3-21/+15
The equal_p method in vrange_storage is only used to compare ranges that are the same type. No sense passing the type if it can be determined from the range being compared. gcc/ChangeLog: * gimple-range-cache.cc (sbr_sparse_bitmap::set_bb_range): Do not pass type to vrange_storage::equal_p. * value-range-storage.cc (vrange_storage::equal_p): Remove type. (irange_storage::equal_p): Same. (frange_storage::equal_p): Same. * value-range-storage.h (class frange_storage): Same.
2023-05-06RISC-V: Fix incorrect demand info merge in local vsetvli optimization [PR109748]Juzhe-Zhong2-45/+93
This patch is fixing my recent optimization patch: https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25260bbf In that patch, the new_info = parse_insn (i) is not correct. Since consider the following case: vsetvli a5,a4, e8,m1 .. vsetvli zero,a5, e32, m4 vle8.v vmacc.vv ... Since we have backward demand fusion in Phase 1, so the real demand of "vle8.v" is e32, m4. However, if we use parse_insn (vle8.v) = e8, m1 which is not correct. So this patch we change new_info = new_info.parse_insn (i) into: vector_insn_info new_info = m_vector_manager->vector_insn_infos[i->uid ()]; So that, we can correctly optimize codes into: vsetvli a5,a4, e32, m4 .. .. (vsetvli zero,a5, e32, m4 is removed) vle8.v vmacc.vv Since m_vector_manager->vector_insn_infos is the member variable of pass_vsetvl class. We remove static void function "local_eliminate_vsetvl_insn", and make it as the member function of pass_vsetvl class. PR target/109748 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): Remove it. (pass_vsetvl::local_eliminate_vsetvl_insn): New function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr109748.c: New test.
2023-05-06Canonicalize vec_merge when mask is constant.liuhongt2-0/+29
Use swap_communattive_operands_p for canonicalization. When both value has same operand precedence value, then first bit in the mask should select first operand. The canonicalization should help backends for pattern match. .i.e. x86 backend has lots of vec_merge patterns, combine will create any form of vec_merge(mask, or inverted mask), then backend need to add 2 patterns to match exact 1 instruction. The canonicalization can simplify 2 patterns to 1. gcc/ChangeLog: * combine.cc (maybe_swap_commutative_operands): Canonicalize vec_merge when mask is constant. * doc/md.texi: Document vec_merge canonicalization.
2023-05-06gimple-range-op: Improve handling of sqrt rangesJakub Jelinek4-16/+182
The previous patch just added basic intrinsic ranges for sqrt ([-0.0, +Inf] +-NAN being the general result range of the function and [-0.0, +Inf] the general operand range if result isn't NAN etc.), the following patch intersects those ranges with particular range computed from argument or result's exact range with the expected error in ulps taken into account and adds a function (frange_arithmetic variant) which can be used by other functions as well as helper. 2023-05-06 Jakub Jelinek <jakub@redhat.com> * value-range.h (frange_arithmetic): Declare. * range-op-float.cc (frange_arithmetic): No longer static. * gimple-range-op.cc (frange_mpfr_arg1): New function. (cfn_sqrt::fold_range): Intersect the generic boundaries range with range computed from sqrt of the particular bounds. (cfn_sqrt::op1_range): Intersect the generic boundaries range with range computed from squared particular bounds. * gcc.dg/tree-ssa/range-sqrt-2.c: New test.
2023-05-06build: Replace seq for portability with GNU Make variantJakub Jelinek1-10/+12
Some hosts like AIX don't have seq command, this patch replaces it with something that uses just GNU make features we've been using for this already before for the parallel make check. 2023-05-06 Jakub Jelinek <jakub@redhat.com> * Makefile.in (check_p_numbers): Rename to one_to_9999, move earlier with helper variables also renamed. (MATCH_SPLUT_SEQ): Use $(wordlist 1,$(NUM_MATCH_SPLITS),$(one_to_9999)) instead of $(shell seq 1 $(NUM_MATCH_SPLITS)). (check_p_subdirs): Use $(one_to_9999) instead of $(check_p_numbers).
2023-05-06Daily bump.GCC Administrator6-1/+1207
2023-05-06CRIS: peephole2 an add into two addq or subqHans-Peter Nilsson3-2/+81
Unfortunately, doesn't cause a performance improvement for coremark, but happens a few times in newlib, just enough to affect coremark 0.01% by size (or 4 bytes, and three cycles (__fwalk_sglue and __vfiprintf_r each two bytes). gcc: * config/cris/cris.md (splitop): Add PLUS. * config/cris/cris.cc (cris_split_constant): Also handle PLUS when a split into two insns may be useful. gcc/testsuite: * gcc.target/cris/peep2-addsplit1.c: New test.
2023-05-06CRIS: peephole2 a move of constant followed by and of same registerHans-Peter Nilsson2-0/+55
While moves of constants into registers are separately optimizable, a combination of a move with a subsequent "and" is slightly preferable even if the move can be generated with the same number (and timing) of insns, as moves of "just" registers are eliminated now and then in different passes, loosely speaking. This movandsplit1 pattern feeds into the opsplit1/AND peephole2, with matching occurrences observed in the floating point functions in libgcc. Also, a test-case to fit. Coremark improvements are unimpressive: less than 0.0003% speed, 0.1% size. But that was pre-LRA; after the switch to LRA this peephole2 doesn't match anymore (for any of coremark, local tests, libgcc and newlib libc) and the test-case passes with and without the patch. Still, there's no apparent reason why LRA prefers "move R1,R2" "and I,R2" to "move I,R1" "and R1,R2", or why that wouldn't "randomly" change (also seen with other operations than "and"). Thus committed. gcc: * config/cris/cris.md (movandsplit1): New define_peephole2. gcc/testsuite: * gcc.target/cris/peep2-movandsplit1.c: New test.
2023-05-06CRIS: peephole2 a lsrq into a lslq+lsrq pairHans-Peter Nilsson3-0/+91
Observed after opsplit1 with AND in libgcc floating-point functions, like the first spottings of opsplit1/AND opportunities. Two patterns are nominally needed, as the peephole2 optimizer continues from the *first replacement* insn, not from a minimum context for general matching; one that includes it as the last match. But, the "free-standing" opportunity (three shifts) didn't match by itself in a gcc build of libraries plus running the test-suite, and thus deemed uninteresting and left out. (As expected; if it had matched, that'd have indicated a previously missed optimization or other problem elsewhere.) Only the one that includes the previous define_peephole2 that may generate the sequence (i.e. opsplit1/AND), matches easily. Coremark results aren't impressive though: 0.003% improvement in speed and slightly less than 0.1% in size. A testcase is added to match and another one to cover a case of movulsr checking that it's used; it's preferable to lsrandsplit when both would match. gcc: * config/cris/cris.md (lsrandsplit1): New define_peephole2. gcc/testsuite: * gcc.target/cris/peep2-lsrandsplit1.c, gcc.target/cris/peep2-movulsr2.c: New tests.
2023-05-06doc: Document order of define_peephole2 scanningHans-Peter Nilsson1-0/+9
I was a bit surprised when my newly-added define_peephole2 didn't match, but it was because it was expected to partially match the generated output of a previous define_peephole2, which matched and modified the last insn of a sequence to be matched. I had assumed that the algorithm backed-up the size of the match-buffer, thereby exposing newly created opportunities *with sufficient context* to all define_peephole2's. While things can change in that direction, let's start with documenting the current state. * doc/md.texi (define_peephole2): Document order of scanning.
2023-05-05Fortran: overloading of intrinsic binary operators [PR109641]Harald Anlauf4-0/+162
Fortran allows overloading of intrinsic operators also for operands of numeric intrinsic types. The intrinsic operator versions are used according to the rules of F2018 table 10.2 and imply type conversion as long as the operand ranks are conformable. Otherwise no type conversion shall be performed to allow the resolution of a matching user-defined operator. gcc/fortran/ChangeLog: PR fortran/109641 * arith.cc (eval_intrinsic): Check conformability of ranks of operands for intrinsic binary operators before performing type conversions. * gfortran.h (gfc_op_rank_conformable): Add prototype. * resolve.cc (resolve_operator): Check conformability of ranks of operands for intrinsic binary operators before performing type conversions. (gfc_op_rank_conformable): New helper function to compare ranks of operands of binary operator. gcc/testsuite/ChangeLog: PR fortran/109641 * gfortran.dg/overload_5.f90: New test.
2023-05-05RISC-V: Legitimise the const0_rtx for RVV indexed load/storePan Li2-32/+33
This patch try to legitimise the const0_rtx (aka zero register) as the base register for the RVV indexed load/store instructions by allowing the const as the operand of the indexed RTL pattern. Then the underlying combine pass will try to perform the const propagation. For example: vint32m1_t test_vluxei32_v_i32m1_shortcut (vuint32m1_t bindex, size_t vl) { return __riscv_vluxei32_v_i32m1 ((int32_t *)0, bindex, vl); } Before this patch: li a5,0 <- can be eliminated. vl1re32.v v1,0(a1) vsetvli zero,a2,e32,m1,ta,ma vluxei32.v v1,(a5),v1 <- can propagate the const 0 to a5 here. vs1r.v v1,0(a0) ret After this patch: test_vluxei32_v_i32m1_shortcut: vl1re32.v v1,0(a1) vsetvli zero,a2,e32,m1,ta,ma vluxei32.v v1,(0),v1 vs1r.v v1,0(a0) ret As above, this patch allow you to propagaate the const 0 (aka zero register) to the base register of the RVV indexed load in the combine pass. This may benefit the underlying RVV auto-vectorization. gcc/ChangeLog: * config/riscv/vector.md: Allow const as the operand of RVV indexed load/store. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Adjust indexed load/store check condition. Signed-off-by: Pan Li <pan2.li@intel.com> Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
2023-05-05RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSETPan Li2-5/+6
When some RVV integer compare operators act on the same vector registers without mask. They can be simplified to VMSET. This PATCH allows the eq, le, leu, ge, geu to perform such kind of the simplification by adding one macro in riscv for simplify rtx. Given we have: vbool1_t test_shortcut_for_riscv_vmseq_case_0(vint8m8_t v1, size_t vl) { return __riscv_vmseq_vv_i8m8_b1(v1, v1, vl); } Before this patch: vsetvli zero,a2,e8,m8,ta,ma vl8re8.v v8,0(a1) vmseq.vv v8,v8,v8 vsetvli a5,zero,e8,m8,ta,ma vsm.v v8,0(a0) ret After this patch: vsetvli zero,a2,e8,m8,ta,ma vmset.m v1 <- optimized to vmset.m vsetvli a5,zero,e8,m8,ta,ma vsm.v v1,0(a0) ret As above, we may have one instruction eliminated and require less vector registers. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * config/riscv/riscv.h (VECTOR_STORE_FLAG_VALUE): Add new macro consumed by simplify_rtx. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Adjust test check condition.
2023-05-05arm: [MVE intrinsics] rework vshrq vrshrqChristophe Lyon4-628/+6
Implement vshrq and vrshrq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vrshrq, vshrq): New. * config/arm/arm-mve-builtins-base.def (vrshrq, vshrq): New. * config/arm/arm-mve-builtins-base.h (vrshrq, vshrq): New. * config/arm/arm_mve.h (vshrq): Remove. (vrshrq): Remove. (vrshrq_m): Remove. (vshrq_m): Remove. (vrshrq_x): Remove. (vshrq_x): Remove. (vshrq_n_s8): Remove. (vshrq_n_s16): Remove. (vshrq_n_s32): Remove. (vshrq_n_u8): Remove. (vshrq_n_u16): Remove. (vshrq_n_u32): Remove. (vrshrq_n_u8): Remove. (vrshrq_n_s8): Remove. (vrshrq_n_u16): Remove. (vrshrq_n_s16): Remove. (vrshrq_n_u32): Remove. (vrshrq_n_s32): Remove. (vrshrq_m_n_s8): Remove. (vrshrq_m_n_s32): Remove. (vrshrq_m_n_s16): Remove. (vrshrq_m_n_u8): Remove. (vrshrq_m_n_u32): Remove. (vrshrq_m_n_u16): Remove. (vshrq_m_n_s8): Remove. (vshrq_m_n_s32): Remove. (vshrq_m_n_s16): Remove. (vshrq_m_n_u8): Remove. (vshrq_m_n_u32): Remove. (vshrq_m_n_u16): Remove. (vrshrq_x_n_s8): Remove. (vrshrq_x_n_s16): Remove. (vrshrq_x_n_s32): Remove. (vrshrq_x_n_u8): Remove. (vrshrq_x_n_u16): Remove. (vrshrq_x_n_u32): Remove. (vshrq_x_n_s8): Remove. (vshrq_x_n_s16): Remove. (vshrq_x_n_s32): Remove. (vshrq_x_n_u8): Remove. (vshrq_x_n_u16): Remove. (vshrq_x_n_u32): Remove. (__arm_vshrq_n_s8): Remove. (__arm_vshrq_n_s16): Remove. (__arm_vshrq_n_s32): Remove. (__arm_vshrq_n_u8): Remove. (__arm_vshrq_n_u16): Remove. (__arm_vshrq_n_u32): Remove. (__arm_vrshrq_n_u8): Remove. (__arm_vrshrq_n_s8): Remove. (__arm_vrshrq_n_u16): Remove. (__arm_vrshrq_n_s16): Remove. (__arm_vrshrq_n_u32): Remove. (__arm_vrshrq_n_s32): Remove. (__arm_vrshrq_m_n_s8): Remove. (__arm_vrshrq_m_n_s32): Remove. (__arm_vrshrq_m_n_s16): Remove. (__arm_vrshrq_m_n_u8): Remove. (__arm_vrshrq_m_n_u32): Remove. (__arm_vrshrq_m_n_u16): Remove. (__arm_vshrq_m_n_s8): Remove. (__arm_vshrq_m_n_s32): Remove. (__arm_vshrq_m_n_s16): Remove. (__arm_vshrq_m_n_u8): Remove. (__arm_vshrq_m_n_u32): Remove. (__arm_vshrq_m_n_u16): Remove. (__arm_vrshrq_x_n_s8): Remove. (__arm_vrshrq_x_n_s16): Remove. (__arm_vrshrq_x_n_s32): Remove. (__arm_vrshrq_x_n_u8): Remove. (__arm_vrshrq_x_n_u16): Remove. (__arm_vrshrq_x_n_u32): Remove. (__arm_vshrq_x_n_s8): Remove. (__arm_vshrq_x_n_s16): Remove. (__arm_vshrq_x_n_s32): Remove. (__arm_vshrq_x_n_u8): Remove. (__arm_vshrq_x_n_u16): Remove. (__arm_vshrq_x_n_u32): Remove. (__arm_vshrq): Remove. (__arm_vrshrq): Remove. (__arm_vrshrq_m): Remove. (__arm_vshrq_m): Remove. (__arm_vrshrq_x): Remove. (__arm_vshrq_x): Remove.
2023-05-05arm: [MVE intrinsics] factorize vsrhrq vrshrqChristophe Lyon2-38/+22
Factorize vsrhrq vrshrq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VSHRQ_M_N, MVE_VSHRQ_N): New. (mve_insn): Add vrshr, vshr. * config/arm/mve.md (mve_vshrq_n_<supf><mode>) (mve_vrshrq_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vrshrq_m_n_<supf><mode>, mve_vshrq_m_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-05arm: [MVE intrinsics] add binary_rshift shapeChristophe Lyon2-0/+37
This patch adds the binary_rshift shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_rshift): New. * config/arm/arm-mve-builtins-shapes.h (binary_rshift): New.
2023-05-05arm: [MVE intrinsics] rework vqrshrunbq vqrshruntq vqshrunbq vqshruntqChristophe Lyon5-320/+25
Implement vqrshrunbq, vqrshruntq, vqshrunbq, vqshruntq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N_NO_U_F): New. (vqshrunbq, vqshruntq, vqrshrunbq, vqrshruntq): New. * config/arm/arm-mve-builtins-base.def (vqshrunbq, vqshruntq) (vqrshrunbq, vqrshruntq): New. * config/arm/arm-mve-builtins-base.h (vqshrunbq, vqshruntq) (vqrshrunbq, vqrshruntq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vqshrunbq, vqshruntq, vqrshrunbq, vqrshruntq. * config/arm/arm_mve.h (vqrshrunbq): Remove. (vqrshruntq): Remove. (vqrshrunbq_m): Remove. (vqrshruntq_m): Remove. (vqrshrunbq_n_s16): Remove. (vqrshrunbq_n_s32): Remove. (vqrshruntq_n_s16): Remove. (vqrshruntq_n_s32): Remove. (vqrshrunbq_m_n_s32): Remove. (vqrshrunbq_m_n_s16): Remove. (vqrshruntq_m_n_s32): Remove. (vqrshruntq_m_n_s16): Remove. (__arm_vqrshrunbq_n_s16): Remove. (__arm_vqrshrunbq_n_s32): Remove. (__arm_vqrshruntq_n_s16): Remove. (__arm_vqrshruntq_n_s32): Remove. (__arm_vqrshrunbq_m_n_s32): Remove. (__arm_vqrshrunbq_m_n_s16): Remove. (__arm_vqrshruntq_m_n_s32): Remove. (__arm_vqrshruntq_m_n_s16): Remove. (__arm_vqrshrunbq): Remove. (__arm_vqrshruntq): Remove. (__arm_vqrshrunbq_m): Remove. (__arm_vqrshruntq_m): Remove. (vqshrunbq): Remove. (vqshruntq): Remove. (vqshrunbq_m): Remove. (vqshruntq_m): Remove. (vqshrunbq_n_s16): Remove. (vqshruntq_n_s16): Remove. (vqshrunbq_n_s32): Remove. (vqshruntq_n_s32): Remove. (vqshrunbq_m_n_s32): Remove. (vqshrunbq_m_n_s16): Remove. (vqshruntq_m_n_s32): Remove. (vqshruntq_m_n_s16): Remove. (__arm_vqshrunbq_n_s16): Remove. (__arm_vqshruntq_n_s16): Remove. (__arm_vqshrunbq_n_s32): Remove. (__arm_vqshruntq_n_s32): Remove. (__arm_vqshrunbq_m_n_s32): Remove. (__arm_vqshrunbq_m_n_s16): Remove. (__arm_vqshruntq_m_n_s32): Remove. (__arm_vqshruntq_m_n_s16): Remove. (__arm_vqshrunbq): Remove. (__arm_vqshruntq): Remove. (__arm_vqshrunbq_m): Remove. (__arm_vqshruntq_m): Remove.
2023-05-05arm: [MVE intrinsics] factorize vqrshrunb vqrshrunt vqshrunb vqshruntChristophe Lyon2-132/+40
Factorize vqrshrunb, vqrshrunt, vqshrunb, vqshrunt so that they use existing patterns. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_SHRN_N): Add VQRSHRUNBQ, VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ. (MVE_SHRN_M_N): Likewise. (mve_insn): Add vqrshrunb, vqrshrunt, vqshrunb, vqshrunt. (isu): Add VQRSHRUNBQ, VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ. (supf): Likewise. * config/arm/mve.md (mve_vqrshrunbq_n_s<mode>): Remove. (mve_vqrshruntq_n_s<mode>): Remove. (mve_vqshrunbq_n_s<mode>): Remove. (mve_vqshruntq_n_s<mode>): Remove. (mve_vqrshrunbq_m_n_s<mode>): Remove. (mve_vqrshruntq_m_n_s<mode>): Remove. (mve_vqshrunbq_m_n_s<mode>): Remove. (mve_vqshruntq_m_n_s<mode>): Remove.
2023-05-05arm: [MVE intrinsics] add binary_rshift_narrow_unsigned shapeChristophe Lyon2-0/+49
This patch adds the binary_rshift_narrow_unsigned shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_rshift_narrow_unsigned): New. * config/arm/arm-mve-builtins-shapes.h (binary_rshift_narrow_unsigned): New.
2023-05-05arm: [MVE intrinsics] rework vshrnbq vshrntq vrshrnbq vrshrntq vqshrnbq ↵Christophe Lyon5-1153/+42
vqshrntq vqrshrnbq vqrshrntq Implement vshrnbq, vshrntq, vrshrnbq, vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N_NO_F): New. (vshrnbq, vshrntq, vrshrnbq, vrshrntq, vqshrnbq, vqshrntq) (vqrshrnbq, vqrshrntq): New. * config/arm/arm-mve-builtins-base.def (vshrnbq, vshrntq) (vrshrnbq, vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq): New. * config/arm/arm-mve-builtins-base.h (vshrnbq, vshrntq, vrshrnbq) (vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vshrnbq, vshrntq, vrshrnbq, vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq. * config/arm/arm_mve.h (vshrnbq): Remove. (vshrntq): Remove. (vshrnbq_m): Remove. (vshrntq_m): Remove. (vshrnbq_n_s16): Remove. (vshrntq_n_s16): Remove. (vshrnbq_n_u16): Remove. (vshrntq_n_u16): Remove. (vshrnbq_n_s32): Remove. (vshrntq_n_s32): Remove. (vshrnbq_n_u32): Remove. (vshrntq_n_u32): Remove. (vshrnbq_m_n_s32): Remove. (vshrnbq_m_n_s16): Remove. (vshrnbq_m_n_u32): Remove. (vshrnbq_m_n_u16): Remove. (vshrntq_m_n_s32): Remove. (vshrntq_m_n_s16): Remove. (vshrntq_m_n_u32): Remove. (vshrntq_m_n_u16): Remove. (__arm_vshrnbq_n_s16): Remove. (__arm_vshrntq_n_s16): Remove. (__arm_vshrnbq_n_u16): Remove. (__arm_vshrntq_n_u16): Remove. (__arm_vshrnbq_n_s32): Remove. (__arm_vshrntq_n_s32): Remove. (__arm_vshrnbq_n_u32): Remove. (__arm_vshrntq_n_u32): Remove. (__arm_vshrnbq_m_n_s32): Remove. (__arm_vshrnbq_m_n_s16): Remove. (__arm_vshrnbq_m_n_u32): Remove. (__arm_vshrnbq_m_n_u16): Remove. (__arm_vshrntq_m_n_s32): Remove. (__arm_vshrntq_m_n_s16): Remove. (__arm_vshrntq_m_n_u32): Remove. (__arm_vshrntq_m_n_u16): Remove. (__arm_vshrnbq): Remove. (__arm_vshrntq): Remove. (__arm_vshrnbq_m): Remove. (__arm_vshrntq_m): Remove. (vrshrnbq): Remove. (vrshrntq): Remove. (vrshrnbq_m): Remove. (vrshrntq_m): Remove. (vrshrnbq_n_s16): Remove. (vrshrntq_n_s16): Remove. (vrshrnbq_n_u16): Remove. (vrshrntq_n_u16): Remove. (vrshrnbq_n_s32): Remove. (vrshrntq_n_s32): Remove. (vrshrnbq_n_u32): Remove. (vrshrntq_n_u32): Remove. (vrshrnbq_m_n_s32): Remove. (vrshrnbq_m_n_s16): Remove. (vrshrnbq_m_n_u32): Remove. (vrshrnbq_m_n_u16): Remove. (vrshrntq_m_n_s32): Remove. (vrshrntq_m_n_s16): Remove. (vrshrntq_m_n_u32): Remove. (vrshrntq_m_n_u16): Remove. (__arm_vrshrnbq_n_s16): Remove. (__arm_vrshrntq_n_s16): Remove. (__arm_vrshrnbq_n_u16): Remove. (__arm_vrshrntq_n_u16): Remove. (__arm_vrshrnbq_n_s32): Remove. (__arm_vrshrntq_n_s32): Remove. (__arm_vrshrnbq_n_u32): Remove. (__arm_vrshrntq_n_u32): Remove. (__arm_vrshrnbq_m_n_s32): Remove. (__arm_vrshrnbq_m_n_s16): Remove. (__arm_vrshrnbq_m_n_u32): Remove. (__arm_vrshrnbq_m_n_u16): Remove. (__arm_vrshrntq_m_n_s32): Remove. (__arm_vrshrntq_m_n_s16): Remove. (__arm_vrshrntq_m_n_u32): Remove. (__arm_vrshrntq_m_n_u16): Remove. (__arm_vrshrnbq): Remove. (__arm_vrshrntq): Remove. (__arm_vrshrnbq_m): Remove. (__arm_vrshrntq_m): Remove. (vqshrnbq): Remove. (vqshrntq): Remove. (vqshrnbq_m): Remove. (vqshrntq_m): Remove. (vqshrnbq_n_s16): Remove. (vqshrntq_n_s16): Remove. (vqshrnbq_n_u16): Remove. (vqshrntq_n_u16): Remove. (vqshrnbq_n_s32): Remove. (vqshrntq_n_s32): Remove. (vqshrnbq_n_u32): Remove. (vqshrntq_n_u32): Remove. (vqshrnbq_m_n_s32): Remove. (vqshrnbq_m_n_s16): Remove. (vqshrnbq_m_n_u32): Remove. (vqshrnbq_m_n_u16): Remove. (vqshrntq_m_n_s32): Remove. (vqshrntq_m_n_s16): Remove. (vqshrntq_m_n_u32): Remove. (vqshrntq_m_n_u16): Remove. (__arm_vqshrnbq_n_s16): Remove. (__arm_vqshrntq_n_s16): Remove. (__arm_vqshrnbq_n_u16): Remove. (__arm_vqshrntq_n_u16): Remove. (__arm_vqshrnbq_n_s32): Remove. (__arm_vqshrntq_n_s32): Remove. (__arm_vqshrnbq_n_u32): Remove. (__arm_vqshrntq_n_u32): Remove. (__arm_vqshrnbq_m_n_s32): Remove. (__arm_vqshrnbq_m_n_s16): Remove. (__arm_vqshrnbq_m_n_u32): Remove. (__arm_vqshrnbq_m_n_u16): Remove. (__arm_vqshrntq_m_n_s32): Remove. (__arm_vqshrntq_m_n_s16): Remove. (__arm_vqshrntq_m_n_u32): Remove. (__arm_vqshrntq_m_n_u16): Remove. (__arm_vqshrnbq): Remove. (__arm_vqshrntq): Remove. (__arm_vqshrnbq_m): Remove. (__arm_vqshrntq_m): Remove. (vqrshrnbq): Remove. (vqrshrntq): Remove. (vqrshrnbq_m): Remove. (vqrshrntq_m): Remove. (vqrshrnbq_n_s16): Remove. (vqrshrnbq_n_u16): Remove. (vqrshrnbq_n_s32): Remove. (vqrshrnbq_n_u32): Remove. (vqrshrntq_n_s16): Remove. (vqrshrntq_n_u16): Remove. (vqrshrntq_n_s32): Remove. (vqrshrntq_n_u32): Remove. (vqrshrnbq_m_n_s32): Remove. (vqrshrnbq_m_n_s16): Remove. (vqrshrnbq_m_n_u32): Remove. (vqrshrnbq_m_n_u16): Remove. (vqrshrntq_m_n_s32): Remove. (vqrshrntq_m_n_s16): Remove. (vqrshrntq_m_n_u32): Remove. (vqrshrntq_m_n_u16): Remove. (__arm_vqrshrnbq_n_s16): Remove. (__arm_vqrshrnbq_n_u16): Remove. (__arm_vqrshrnbq_n_s32): Remove. (__arm_vqrshrnbq_n_u32): Remove. (__arm_vqrshrntq_n_s16): Remove. (__arm_vqrshrntq_n_u16): Remove. (__arm_vqrshrntq_n_s32): Remove. (__arm_vqrshrntq_n_u32): Remove. (__arm_vqrshrnbq_m_n_s32): Remove. (__arm_vqrshrnbq_m_n_s16): Remove. (__arm_vqrshrnbq_m_n_u32): Remove. (__arm_vqrshrnbq_m_n_u16): Remove. (__arm_vqrshrntq_m_n_s32): Remove. (__arm_vqrshrntq_m_n_s16): Remove. (__arm_vqrshrntq_m_n_u32): Remove. (__arm_vqrshrntq_m_n_u16): Remove. (__arm_vqrshrnbq): Remove. (__arm_vqrshrntq): Remove. (__arm_vqrshrnbq_m): Remove. (__arm_vqrshrntq_m): Remove.
2023-05-05arm: [MVE intrinsics] factorize vshrntq vshrnbq vrshrnbq vrshrntq vqshrnbq ↵Christophe Lyon2-242/+85
vqshrntq vqrshrnbq vqrshrntq Factorize vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq, vshrntq, vshrnbq, vrshrnbq and vrshrntq so that they use the same pattern. Introduce <isu> iterator for *shrn* so that we can use the same pattern despite the different "s", "u" and "i" suffixes. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_SHRN_N, MVE_SHRN_M_N): New. (mve_insn): Add vqrshrnb, vqrshrnt, vqshrnb, vqshrnt, vrshrnb, vrshrnt, vshrnb, vshrnt. (isu): New. * config/arm/mve.md (mve_vqrshrnbq_n_<supf><mode>) (mve_vqrshrntq_n_<supf><mode>, mve_vqshrnbq_n_<supf><mode>) (mve_vqshrntq_n_<supf><mode>, mve_vrshrnbq_n_<supf><mode>) (mve_vrshrntq_n_<supf><mode>, mve_vshrnbq_n_<supf><mode>) (mve_vshrntq_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vqrshrnbq_m_n_<supf><mode>, mve_vqrshrntq_m_n_<supf><mode>) (mve_vqshrnbq_m_n_<supf><mode>, mve_vqshrntq_m_n_<supf><mode>) (mve_vrshrnbq_m_n_<supf><mode>, mve_vrshrntq_m_n_<supf><mode>) (mve_vshrnbq_m_n_<supf><mode>, mve_vshrntq_m_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-05arm: [MVE intrinsics] add binary_rshift_narrow shapeChristophe Lyon2-0/+48
This patch adds the binary_rshift_narrow shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_rshift_narrow): New. * config/arm/arm-mve-builtins-shapes.h (binary_rshift_narrow): New.
2023-05-05arm: [MVE intrinsics] rework vmaxq vminqChristophe Lyon4-628/+15
Implement vmaxq and vminq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_NO_F): New. (vmaxq, vminq): New. * config/arm/arm-mve-builtins-base.def (vmaxq, vminq): New. * config/arm/arm-mve-builtins-base.h (vmaxq, vminq): New. * config/arm/arm_mve.h (vminq): Remove. (vmaxq): Remove. (vmaxq_m): Remove. (vminq_m): Remove. (vminq_x): Remove. (vmaxq_x): Remove. (vminq_u8): Remove. (vmaxq_u8): Remove. (vminq_s8): Remove. (vmaxq_s8): Remove. (vminq_u16): Remove. (vmaxq_u16): Remove. (vminq_s16): Remove. (vmaxq_s16): Remove. (vminq_u32): Remove. (vmaxq_u32): Remove. (vminq_s32): Remove. (vmaxq_s32): Remove. (vmaxq_m_s8): Remove. (vmaxq_m_s32): Remove. (vmaxq_m_s16): Remove. (vmaxq_m_u8): Remove. (vmaxq_m_u32): Remove. (vmaxq_m_u16): Remove. (vminq_m_s8): Remove. (vminq_m_s32): Remove. (vminq_m_s16): Remove. (vminq_m_u8): Remove. (vminq_m_u32): Remove. (vminq_m_u16): Remove. (vminq_x_s8): Remove. (vminq_x_s16): Remove. (vminq_x_s32): Remove. (vminq_x_u8): Remove. (vminq_x_u16): Remove. (vminq_x_u32): Remove. (vmaxq_x_s8): Remove. (vmaxq_x_s16): Remove. (vmaxq_x_s32): Remove. (vmaxq_x_u8): Remove. (vmaxq_x_u16): Remove. (vmaxq_x_u32): Remove. (__arm_vminq_u8): Remove. (__arm_vmaxq_u8): Remove. (__arm_vminq_s8): Remove. (__arm_vmaxq_s8): Remove. (__arm_vminq_u16): Remove. (__arm_vmaxq_u16): Remove. (__arm_vminq_s16): Remove. (__arm_vmaxq_s16): Remove. (__arm_vminq_u32): Remove. (__arm_vmaxq_u32): Remove. (__arm_vminq_s32): Remove. (__arm_vmaxq_s32): Remove. (__arm_vmaxq_m_s8): Remove. (__arm_vmaxq_m_s32): Remove. (__arm_vmaxq_m_s16): Remove. (__arm_vmaxq_m_u8): Remove. (__arm_vmaxq_m_u32): Remove. (__arm_vmaxq_m_u16): Remove. (__arm_vminq_m_s8): Remove. (__arm_vminq_m_s32): Remove. (__arm_vminq_m_s16): Remove. (__arm_vminq_m_u8): Remove. (__arm_vminq_m_u32): Remove. (__arm_vminq_m_u16): Remove. (__arm_vminq_x_s8): Remove. (__arm_vminq_x_s16): Remove. (__arm_vminq_x_s32): Remove. (__arm_vminq_x_u8): Remove. (__arm_vminq_x_u16): Remove. (__arm_vminq_x_u32): Remove. (__arm_vmaxq_x_s8): Remove. (__arm_vmaxq_x_s16): Remove. (__arm_vmaxq_x_s32): Remove. (__arm_vmaxq_x_u8): Remove. (__arm_vmaxq_x_u16): Remove. (__arm_vmaxq_x_u32): Remove. (__arm_vminq): Remove. (__arm_vmaxq): Remove. (__arm_vmaxq_m): Remove. (__arm_vminq_m): Remove. (__arm_vminq_x): Remove. (__arm_vmaxq_x): Remove.
2023-05-05arm: [MVE intrinsics] factorize vmaxq vminqChristophe Lyon2-39/+16
Factorize vmaxq and vminq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MAX_MIN_SU): New. (max_min_su_str): New. (max_min_supf): New. * config/arm/mve.md (mve_vmaxq_s<mode>, mve_vmaxq_u<mode>) (mve_vminq_s<mode>, mve_vminq_u<mode>): Merge into ... (mve_<max_min_su_str>q_<max_min_supf><mode>): ... this.
2023-05-05arm: [MVE intrinsics] rework vqshlq vshlqChristophe Lyon4-1492/+19
Implement vqshlq, vshlq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_M_N_R): New. (vqshlq, vshlq): New. * config/arm/arm-mve-builtins-base.def (vqshlq, vshlq): New. * config/arm/arm-mve-builtins-base.h (vqshlq, vshlq): New. * config/arm/arm_mve.h (vshlq): Remove. (vshlq_r): Remove. (vshlq_n): Remove. (vshlq_m_r): Remove. (vshlq_m): Remove. (vshlq_m_n): Remove. (vshlq_x): Remove. (vshlq_x_n): Remove. (vshlq_s8): Remove. (vshlq_s16): Remove. (vshlq_s32): Remove. (vshlq_u8): Remove. (vshlq_u16): Remove. (vshlq_u32): Remove. (vshlq_r_u8): Remove. (vshlq_n_u8): Remove. (vshlq_r_s8): Remove. (vshlq_n_s8): Remove. (vshlq_r_u16): Remove. (vshlq_n_u16): Remove. (vshlq_r_s16): Remove. (vshlq_n_s16): Remove. (vshlq_r_u32): Remove. (vshlq_n_u32): Remove. (vshlq_r_s32): Remove. (vshlq_n_s32): Remove. (vshlq_m_r_u8): Remove. (vshlq_m_r_s8): Remove. (vshlq_m_r_u16): Remove. (vshlq_m_r_s16): Remove. (vshlq_m_r_u32): Remove. (vshlq_m_r_s32): Remove. (vshlq_m_u8): Remove. (vshlq_m_s8): Remove. (vshlq_m_u16): Remove. (vshlq_m_s16): Remove. (vshlq_m_u32): Remove. (vshlq_m_s32): Remove. (vshlq_m_n_s8): Remove. (vshlq_m_n_s32): Remove. (vshlq_m_n_s16): Remove. (vshlq_m_n_u8): Remove. (vshlq_m_n_u32): Remove. (vshlq_m_n_u16): Remove. (vshlq_x_s8): Remove. (vshlq_x_s16): Remove. (vshlq_x_s32): Remove. (vshlq_x_u8): Remove. (vshlq_x_u16): Remove. (vshlq_x_u32): Remove. (vshlq_x_n_s8): Remove. (vshlq_x_n_s16): Remove. (vshlq_x_n_s32): Remove. (vshlq_x_n_u8): Remove. (vshlq_x_n_u16): Remove. (vshlq_x_n_u32): Remove. (__arm_vshlq_s8): Remove. (__arm_vshlq_s16): Remove. (__arm_vshlq_s32): Remove. (__arm_vshlq_u8): Remove. (__arm_vshlq_u16): Remove. (__arm_vshlq_u32): Remove. (__arm_vshlq_r_u8): Remove. (__arm_vshlq_n_u8): Remove. (__arm_vshlq_r_s8): Remove. (__arm_vshlq_n_s8): Remove. (__arm_vshlq_r_u16): Remove. (__arm_vshlq_n_u16): Remove. (__arm_vshlq_r_s16): Remove. (__arm_vshlq_n_s16): Remove. (__arm_vshlq_r_u32): Remove. (__arm_vshlq_n_u32): Remove. (__arm_vshlq_r_s32): Remove. (__arm_vshlq_n_s32): Remove. (__arm_vshlq_m_r_u8): Remove. (__arm_vshlq_m_r_s8): Remove. (__arm_vshlq_m_r_u16): Remove. (__arm_vshlq_m_r_s16): Remove. (__arm_vshlq_m_r_u32): Remove. (__arm_vshlq_m_r_s32): Remove. (__arm_vshlq_m_u8): Remove. (__arm_vshlq_m_s8): Remove. (__arm_vshlq_m_u16): Remove. (__arm_vshlq_m_s16): Remove. (__arm_vshlq_m_u32): Remove. (__arm_vshlq_m_s32): Remove. (__arm_vshlq_m_n_s8): Remove. (__arm_vshlq_m_n_s32): Remove. (__arm_vshlq_m_n_s16): Remove. (__arm_vshlq_m_n_u8): Remove. (__arm_vshlq_m_n_u32): Remove. (__arm_vshlq_m_n_u16): Remove. (__arm_vshlq_x_s8): Remove. (__arm_vshlq_x_s16): Remove. (__arm_vshlq_x_s32): Remove. (__arm_vshlq_x_u8): Remove. (__arm_vshlq_x_u16): Remove. (__arm_vshlq_x_u32): Remove. (__arm_vshlq_x_n_s8): Remove. (__arm_vshlq_x_n_s16): Remove. (__arm_vshlq_x_n_s32): Remove. (__arm_vshlq_x_n_u8): Remove. (__arm_vshlq_x_n_u16): Remove. (__arm_vshlq_x_n_u32): Remove. (__arm_vshlq): Remove. (__arm_vshlq_r): Remove. (__arm_vshlq_n): Remove. (__arm_vshlq_m_r): Remove. (__arm_vshlq_m): Remove. (__arm_vshlq_m_n): Remove. (__arm_vshlq_x): Remove. (__arm_vshlq_x_n): Remove. (vqshlq): Remove. (vqshlq_r): Remove. (vqshlq_n): Remove. (vqshlq_m_r): Remove. (vqshlq_m_n): Remove. (vqshlq_m): Remove. (vqshlq_u8): Remove. (vqshlq_r_u8): Remove. (vqshlq_n_u8): Remove. (vqshlq_s8): Remove. (vqshlq_r_s8): Remove. (vqshlq_n_s8): Remove. (vqshlq_u16): Remove. (vqshlq_r_u16): Remove. (vqshlq_n_u16): Remove. (vqshlq_s16): Remove. (vqshlq_r_s16): Remove. (vqshlq_n_s16): Remove. (vqshlq_u32): Remove. (vqshlq_r_u32): Remove. (vqshlq_n_u32): Remove. (vqshlq_s32): Remove. (vqshlq_r_s32): Remove. (vqshlq_n_s32): Remove. (vqshlq_m_r_u8): Remove. (vqshlq_m_r_s8): Remove. (vqshlq_m_r_u16): Remove. (vqshlq_m_r_s16): Remove. (vqshlq_m_r_u32): Remove. (vqshlq_m_r_s32): Remove. (vqshlq_m_n_s8): Remove. (vqshlq_m_n_s32): Remove. (vqshlq_m_n_s16): Remove. (vqshlq_m_n_u8): Remove. (vqshlq_m_n_u32): Remove. (vqshlq_m_n_u16): Remove. (vqshlq_m_s8): Remove. (vqshlq_m_s32): Remove. (vqshlq_m_s16): Remove. (vqshlq_m_u8): Remove. (vqshlq_m_u32): Remove. (vqshlq_m_u16): Remove. (__arm_vqshlq_u8): Remove. (__arm_vqshlq_r_u8): Remove. (__arm_vqshlq_n_u8): Remove. (__arm_vqshlq_s8): Remove. (__arm_vqshlq_r_s8): Remove. (__arm_vqshlq_n_s8): Remove. (__arm_vqshlq_u16): Remove. (__arm_vqshlq_r_u16): Remove. (__arm_vqshlq_n_u16): Remove. (__arm_vqshlq_s16): Remove. (__arm_vqshlq_r_s16): Remove. (__arm_vqshlq_n_s16): Remove. (__arm_vqshlq_u32): Remove. (__arm_vqshlq_r_u32): Remove. (__arm_vqshlq_n_u32): Remove. (__arm_vqshlq_s32): Remove. (__arm_vqshlq_r_s32): Remove. (__arm_vqshlq_n_s32): Remove. (__arm_vqshlq_m_r_u8): Remove. (__arm_vqshlq_m_r_s8): Remove. (__arm_vqshlq_m_r_u16): Remove. (__arm_vqshlq_m_r_s16): Remove. (__arm_vqshlq_m_r_u32): Remove. (__arm_vqshlq_m_r_s32): Remove. (__arm_vqshlq_m_n_s8): Remove. (__arm_vqshlq_m_n_s32): Remove. (__arm_vqshlq_m_n_s16): Remove. (__arm_vqshlq_m_n_u8): Remove. (__arm_vqshlq_m_n_u32): Remove. (__arm_vqshlq_m_n_u16): Remove. (__arm_vqshlq_m_s8): Remove. (__arm_vqshlq_m_s32): Remove. (__arm_vqshlq_m_s16): Remove. (__arm_vqshlq_m_u8): Remove. (__arm_vqshlq_m_u32): Remove. (__arm_vqshlq_m_u16): Remove. (__arm_vqshlq): Remove. (__arm_vqshlq_r): Remove. (__arm_vqshlq_n): Remove. (__arm_vqshlq_m_r): Remove. (__arm_vqshlq_m_n): Remove. (__arm_vqshlq_m): Remove.
2023-05-05arm: [MVE intrinsics] add unspec_mve_function_exact_insn_vshlChristophe Lyon1-0/+150
Introduce a function that will be used to build vshl intrinsics. They are special because they have to handle MODE_r. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-functions.h (class unspec_mve_function_exact_insn_vshl): New.
2023-05-05arm: [MVE intrinsics] add binary_lshift_r shapeChristophe Lyon2-0/+42
This patch adds the binary_lshift_r shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_lshift_r): New. * config/arm/arm-mve-builtins-shapes.h (binary_lshift_r): New.
2023-05-05arm: [MVE intrinsics] add support for MODE_rChristophe Lyon2-2/+7
A few intrinsics have an additional mode (MODE_r), which does not always support the same set of predicates as MODE_none and MODE_n. For vqshlq they are the same, but for vshlq they are not. Indeed we have: vqshlq vqshlq_m vqshlq_n vqshlq_m_n vqshlq_r vqshlq_m_r vshlq vshlq_m vshlq_x vshlq_n vshlq_m_n vshlq_x_n vshlq_r vshlq_m_r This patch adds support for it. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins.cc (has_inactive_argument) (finish_opt_n_resolution): Handle MODE_r. * config/arm/arm-mve-builtins.def (r): New mode.
2023-05-05arm: [MVE intrinsics] add binary_lshift shapeChristophe Lyon2-0/+58
This patch adds the binary_lshift shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_lshift): New. * config/arm/arm-mve-builtins-shapes.h (binary_lshift): New.
2023-05-05arm: [MVE intrinsics] rework vabdqChristophe Lyon4-431/+13
Implement vabdq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_N): New. (vabdq): New. * config/arm/arm-mve-builtins-base.def (vabdq): New. * config/arm/arm-mve-builtins-base.h (vabdq): New. * config/arm/arm_mve.h (vabdq): Remove. (vabdq_m): Remove. (vabdq_x): Remove. (vabdq_u8): Remove. (vabdq_s8): Remove. (vabdq_u16): Remove. (vabdq_s16): Remove. (vabdq_u32): Remove. (vabdq_s32): Remove. (vabdq_f16): Remove. (vabdq_f32): Remove. (vabdq_m_s8): Remove. (vabdq_m_s32): Remove. (vabdq_m_s16): Remove. (vabdq_m_u8): Remove. (vabdq_m_u32): Remove. (vabdq_m_u16): Remove. (vabdq_m_f32): Remove. (vabdq_m_f16): Remove. (vabdq_x_s8): Remove. (vabdq_x_s16): Remove. (vabdq_x_s32): Remove. (vabdq_x_u8): Remove. (vabdq_x_u16): Remove. (vabdq_x_u32): Remove. (vabdq_x_f16): Remove. (vabdq_x_f32): Remove. (__arm_vabdq_u8): Remove. (__arm_vabdq_s8): Remove. (__arm_vabdq_u16): Remove. (__arm_vabdq_s16): Remove. (__arm_vabdq_u32): Remove. (__arm_vabdq_s32): Remove. (__arm_vabdq_m_s8): Remove. (__arm_vabdq_m_s32): Remove. (__arm_vabdq_m_s16): Remove. (__arm_vabdq_m_u8): Remove. (__arm_vabdq_m_u32): Remove. (__arm_vabdq_m_u16): Remove. (__arm_vabdq_x_s8): Remove. (__arm_vabdq_x_s16): Remove. (__arm_vabdq_x_s32): Remove. (__arm_vabdq_x_u8): Remove. (__arm_vabdq_x_u16): Remove. (__arm_vabdq_x_u32): Remove. (__arm_vabdq_f16): Remove. (__arm_vabdq_f32): Remove. (__arm_vabdq_m_f32): Remove. (__arm_vabdq_m_f16): Remove. (__arm_vabdq_x_f16): Remove. (__arm_vabdq_x_f32): Remove. (__arm_vabdq): Remove. (__arm_vabdq_m): Remove. (__arm_vabdq_x): Remove.
2023-05-05arm: [MVE intrinsics] factorize vabdqChristophe Lyon2-22/+12
2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_FP_M_BINARY): Add vabdq. (MVE_FP_VABDQ_ONLY): New. (mve_insn): Add vabd. * config/arm/mve.md (mve_vabdq_f<mode>): Move into ... (@mve_<mve_insn>q_f<mode>): ... this. (mve_vabdq_m_f<mode>): Remove.
2023-05-05arm: [MVE intrinsics] rework vqrdmulhqChristophe Lyon4-213/+3
Implement vqrdmulhq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vqrdmulhq): New. * config/arm/arm-mve-builtins-base.def (vqrdmulhq): New. * config/arm/arm-mve-builtins-base.h (vqrdmulhq): New. * config/arm/arm_mve.h (vqrdmulhq): Remove. (vqrdmulhq_m): Remove. (vqrdmulhq_s8): Remove. (vqrdmulhq_n_s8): Remove. (vqrdmulhq_s16): Remove. (vqrdmulhq_n_s16): Remove. (vqrdmulhq_s32): Remove. (vqrdmulhq_n_s32): Remove. (vqrdmulhq_m_n_s8): Remove. (vqrdmulhq_m_n_s32): Remove. (vqrdmulhq_m_n_s16): Remove. (vqrdmulhq_m_s8): Remove. (vqrdmulhq_m_s32): Remove. (vqrdmulhq_m_s16): Remove. (__arm_vqrdmulhq_s8): Remove. (__arm_vqrdmulhq_n_s8): Remove. (__arm_vqrdmulhq_s16): Remove. (__arm_vqrdmulhq_n_s16): Remove. (__arm_vqrdmulhq_s32): Remove. (__arm_vqrdmulhq_n_s32): Remove. (__arm_vqrdmulhq_m_n_s8): Remove. (__arm_vqrdmulhq_m_n_s32): Remove. (__arm_vqrdmulhq_m_n_s16): Remove. (__arm_vqrdmulhq_m_s8): Remove. (__arm_vqrdmulhq_m_s32): Remove. (__arm_vqrdmulhq_m_s16): Remove. (__arm_vqrdmulhq): Remove. (__arm_vqrdmulhq_m): Remove.
2023-05-05arm: [MVE intrinsics] factorize vqshlq vshlqChristophe Lyon3-81/+51
Factorize vqshlq and vshlq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_SHIFT_M_R, MVE_SHIFT_M_N) (MVE_SHIFT_N, MVE_SHIFT_R): New. (mve_insn): Add vqshl, vshl. * config/arm/mve.md (mve_vqshlq_n_<supf><mode>) (mve_vshlq_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vqshlq_r_<supf><mode>, mve_vshlq_r_<supf><mode>): Merge into ... (@mve_<mve_insn>q_r_<supf><mode>): ... this. (mve_vqshlq_m_r_<supf><mode>, mve_vshlq_m_r_<supf><mode>): Merge into ... (@mve_<mve_insn>q_m_r_<supf><mode>): ... this. (mve_vqshlq_m_n_<supf><mode>, mve_vshlq_m_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this. * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Transform into ... (@mve_<mve_insn>q_<supf><mode>): ... this.
2023-05-05arm: [MVE intrinsics] rework vrshlq vqrshlqChristophe Lyon5-952/+9
Implement vrshlq, vqrshlq using the new MVE builtins framework. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vqrshlq, vrshlq): New. * config/arm/arm-mve-builtins-base.def (vqrshlq, vrshlq): New. * config/arm/arm-mve-builtins-base.h (vqrshlq, vrshlq): New. * config/arm/arm-mve-builtins.cc (has_inactive_argument): Handle vqrshlq, vrshlq. * config/arm/arm_mve.h (vrshlq): Remove. (vrshlq_m_n): Remove. (vrshlq_m): Remove. (vrshlq_x): Remove. (vrshlq_u8): Remove. (vrshlq_n_u8): Remove. (vrshlq_s8): Remove. (vrshlq_n_s8): Remove. (vrshlq_u16): Remove. (vrshlq_n_u16): Remove. (vrshlq_s16): Remove. (vrshlq_n_s16): Remove. (vrshlq_u32): Remove. (vrshlq_n_u32): Remove. (vrshlq_s32): Remove. (vrshlq_n_s32): Remove. (vrshlq_m_n_u8): Remove. (vrshlq_m_n_s8): Remove. (vrshlq_m_n_u16): Remove. (vrshlq_m_n_s16): Remove. (vrshlq_m_n_u32): Remove. (vrshlq_m_n_s32): Remove. (vrshlq_m_s8): Remove. (vrshlq_m_s32): Remove. (vrshlq_m_s16): Remove. (vrshlq_m_u8): Remove. (vrshlq_m_u32): Remove. (vrshlq_m_u16): Remove. (vrshlq_x_s8): Remove. (vrshlq_x_s16): Remove. (vrshlq_x_s32): Remove. (vrshlq_x_u8): Remove. (vrshlq_x_u16): Remove. (vrshlq_x_u32): Remove. (__arm_vrshlq_u8): Remove. (__arm_vrshlq_n_u8): Remove. (__arm_vrshlq_s8): Remove. (__arm_vrshlq_n_s8): Remove. (__arm_vrshlq_u16): Remove. (__arm_vrshlq_n_u16): Remove. (__arm_vrshlq_s16): Remove. (__arm_vrshlq_n_s16): Remove. (__arm_vrshlq_u32): Remove. (__arm_vrshlq_n_u32): Remove. (__arm_vrshlq_s32): Remove. (__arm_vrshlq_n_s32): Remove. (__arm_vrshlq_m_n_u8): Remove. (__arm_vrshlq_m_n_s8): Remove. (__arm_vrshlq_m_n_u16): Remove. (__arm_vrshlq_m_n_s16): Remove. (__arm_vrshlq_m_n_u32): Remove. (__arm_vrshlq_m_n_s32): Remove. (__arm_vrshlq_m_s8): Remove. (__arm_vrshlq_m_s32): Remove. (__arm_vrshlq_m_s16): Remove. (__arm_vrshlq_m_u8): Remove. (__arm_vrshlq_m_u32): Remove. (__arm_vrshlq_m_u16): Remove. (__arm_vrshlq_x_s8): Remove. (__arm_vrshlq_x_s16): Remove. (__arm_vrshlq_x_s32): Remove. (__arm_vrshlq_x_u8): Remove. (__arm_vrshlq_x_u16): Remove. (__arm_vrshlq_x_u32): Remove. (__arm_vrshlq): Remove. (__arm_vrshlq_m_n): Remove. (__arm_vrshlq_m): Remove. (__arm_vrshlq_x): Remove. (vqrshlq): Remove. (vqrshlq_m_n): Remove. (vqrshlq_m): Remove. (vqrshlq_u8): Remove. (vqrshlq_n_u8): Remove. (vqrshlq_s8): Remove. (vqrshlq_n_s8): Remove. (vqrshlq_u16): Remove. (vqrshlq_n_u16): Remove. (vqrshlq_s16): Remove. (vqrshlq_n_s16): Remove. (vqrshlq_u32): Remove. (vqrshlq_n_u32): Remove. (vqrshlq_s32): Remove. (vqrshlq_n_s32): Remove. (vqrshlq_m_n_u8): Remove. (vqrshlq_m_n_s8): Remove. (vqrshlq_m_n_u16): Remove. (vqrshlq_m_n_s16): Remove. (vqrshlq_m_n_u32): Remove. (vqrshlq_m_n_s32): Remove. (vqrshlq_m_s8): Remove. (vqrshlq_m_s32): Remove. (vqrshlq_m_s16): Remove. (vqrshlq_m_u8): Remove. (vqrshlq_m_u32): Remove. (vqrshlq_m_u16): Remove. (__arm_vqrshlq_u8): Remove. (__arm_vqrshlq_n_u8): Remove. (__arm_vqrshlq_s8): Remove. (__arm_vqrshlq_n_s8): Remove. (__arm_vqrshlq_u16): Remove. (__arm_vqrshlq_n_u16): Remove. (__arm_vqrshlq_s16): Remove. (__arm_vqrshlq_n_s16): Remove. (__arm_vqrshlq_u32): Remove. (__arm_vqrshlq_n_u32): Remove. (__arm_vqrshlq_s32): Remove. (__arm_vqrshlq_n_s32): Remove. (__arm_vqrshlq_m_n_u8): Remove. (__arm_vqrshlq_m_n_s8): Remove. (__arm_vqrshlq_m_n_u16): Remove. (__arm_vqrshlq_m_n_s16): Remove. (__arm_vqrshlq_m_n_u32): Remove. (__arm_vqrshlq_m_n_s32): Remove. (__arm_vqrshlq_m_s8): Remove. (__arm_vqrshlq_m_s32): Remove. (__arm_vqrshlq_m_s16): Remove. (__arm_vqrshlq_m_u8): Remove. (__arm_vqrshlq_m_u32): Remove. (__arm_vqrshlq_m_u16): Remove. (__arm_vqrshlq): Remove. (__arm_vqrshlq_m_n): Remove. (__arm_vqrshlq_m): Remove.
2023-05-05arm: [MVE intrinsics] factorize vqrshlq vrshlqChristophe Lyon2-39/+24
Factorize vqrshlq, vrshlq so that they use the same pattern. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_RSHIFT_M_N, MVE_RSHIFT_N): New. (mve_insn): Add vqrshl, vrshl. * config/arm/mve.md (mve_vqrshlq_n_<supf><mode>) (mve_vrshlq_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vqrshlq_m_n_<supf><mode>, mve_vrshlq_m_n_<supf><mode>): Merge into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-05arm: [MVE intrinsics] add binary_round_lshift shapeChristophe Lyon2-0/+62
This patch adds the binary_round_lshift shape description. 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_round_lshift): New. * config/arm/arm-mve-builtins-shapes.h (binary_round_lshift): New.
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