| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2017-10-23 | Convert STARTING_FRAME_OFFSET to a hook | Richard Sandiford | 84 | -302/+370 | |
| I took the documentation of the FRAME_GROWS_DOWNWARD behaviour from the version that was in most header files, since the one in the manual seemed less clear. The patch deliberately keeps FIRST_PARM_OFFSET(FNDECL) in microblaze_starting_frame_offset; this seems to be a port-local convention and takes advantage of the fact that FIRST_PARM_OFFSET doesn't read FNDECL. 2017-10-23 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * target.def (starting_frame_offset): New hook. * doc/tm.texi (STARTING_FRAME_OFFSET): Remove in favor of... (TARGET_STARTING_FRAME_OFFSET): ...this new hook. * doc/tm.texi.in: Regenerate. * hooks.h (hook_hwi_void_0): Declare. * hooks.c (hook_hwi_void_0): New function. * doc/rtl.texi: Refer to TARGET_STARTING_FRAME_OFFSET instead of STARTING_FRAME_OFFSET. * builtins.c (expand_builtin_setjmp_receiver): Likewise. * reload1.c (reload): Likewise. * cfgexpand.c (expand_used_vars): Use targetm.starting_frame_offset instead of STARTING_FRAME_OFFSET. * function.c (try_fit_stack_local): Likewise. (assign_stack_local_1): Likewise (instantiate_virtual_regs): Likewise. * rtlanal.c (rtx_addr_can_trap_p_1): Likewise. * config/avr/avr.md (nonlocal_goto_receiver): Likewise. * config/aarch64/aarch64.h (STARTING_FRAME_OFFSET): Delete. * config/alpha/alpha.h (STARTING_FRAME_OFFSET): Likewise. * config/arc/arc.h (STARTING_FRAME_OFFSET): Likewise. * config/arm/arm.h (STARTING_FRAME_OFFSET): Likewise. * config/bfin/bfin.h (STARTING_FRAME_OFFSET): Likewise. * config/c6x/c6x.h (STARTING_FRAME_OFFSET): Likewise. * config/cr16/cr16.h (STARTING_FRAME_OFFSET): Likewise. * config/cris/cris.h (STARTING_FRAME_OFFSET): Likewise. * config/fr30/fr30.h (STARTING_FRAME_OFFSET): Likewise. * config/frv/frv.h (STARTING_FRAME_OFFSET): Likewise. * config/ft32/ft32.h (STARTING_FRAME_OFFSET): Likewise. * config/h8300/h8300.h (STARTING_FRAME_OFFSET): Likewise. * config/i386/i386.h (STARTING_FRAME_OFFSET): Likewise. * config/ia64/ia64.h (STARTING_FRAME_OFFSET): Likewise. * config/m32c/m32c.h (STARTING_FRAME_OFFSET): Likewise. * config/m68k/m68k.h (STARTING_FRAME_OFFSET): Likewise. * config/mcore/mcore.h (STARTING_FRAME_OFFSET): Likewise. * config/mn10300/mn10300.h (STARTING_FRAME_OFFSET): Likewise. * config/moxie/moxie.h (STARTING_FRAME_OFFSET): Likewise. * config/msp430/msp430.h (STARTING_FRAME_OFFSET): Likewise. * config/nds32/nds32.h (STARTING_FRAME_OFFSET): Likewise. * config/nios2/nios2.h (STARTING_FRAME_OFFSET): Likewise. * config/nvptx/nvptx.h (STARTING_FRAME_OFFSET): Likewise. * config/pdp11/pdp11.h (STARTING_FRAME_OFFSET): Likewise. * config/riscv/riscv.h (STARTING_FRAME_OFFSET): Likewise. * config/rl78/rl78.h (STARTING_FRAME_OFFSET): Likewise. * config/rx/rx.h (STARTING_FRAME_OFFSET): Likewise. * config/s390/s390.h (STARTING_FRAME_OFFSET): Likewise. * config/sh/sh.h (STARTING_FRAME_OFFSET): Likewise. * config/sparc/sparc.c (sparc_compute_frame_size): Likewise. * config/sparc/sparc.h (STARTING_FRAME_OFFSET): Likewise. * config/spu/spu.h (STARTING_FRAME_OFFSET): Likewise. * config/stormy16/stormy16.h (STARTING_FRAME_OFFSET): Likewise. * config/tilegx/tilegx.h (STARTING_FRAME_OFFSET): Likewise. * config/tilepro/tilepro.h (STARTING_FRAME_OFFSET): Likewise. * config/v850/v850.h (STARTING_FRAME_OFFSET): Likewise. * config/visium/visium.h (STARTING_FRAME_OFFSET): Likewise. * config/avr/avr.h (STARTING_FRAME_OFFSET): Likewise. * config/avr/avr-protos.h (avr_starting_frame_offset): Likewise. * config/avr/avr.c (avr_starting_frame_offset): Make static and return a HOST_WIDE_INT. (avr_builtin_setjmp_frame_value): Use it instead of STARTING_FRAME_OFFSET. (TARGET_STARTING_FRAME_OFFSET): Redefine. * config/epiphany/epiphany.h (STARTING_FRAME_OFFSET): Delete. * config/epiphany/epiphany.c (epiphany_starting_frame_offset): New function. (TARGET_STARTING_FRAME_OFFSET): Redefine. * config/iq2000/iq2000.h (STARTING_FRAME_OFFSET): Delete. * config/iq2000/iq2000.c (iq2000_starting_frame_offset): New function. (TARGET_CONSTANT_ALIGNMENT): Redefine. * config/lm32/lm32.h (STARTING_FRAME_OFFSET): Delete. * config/lm32/lm32.c (lm32_starting_frame_offset): New function. (TARGET_STARTING_FRAME_OFFSET): Redefine. * config/m32r/m32r.h (STARTING_FRAME_OFFSET): Delete. * config/m32r/m32r.c (m32r_starting_frame_offset): New function. (TARGET_STARTING_FRAME_OFFSET): Redefine. * config/microblaze/microblaze.h (STARTING_FRAME_OFFSET): Delete. * config/microblaze/microblaze.c (microblaze_starting_frame_offset): New function. (TARGET_STARTING_FRAME_OFFSET): Redefine. * config/mips/mips.h (STARTING_FRAME_OFFSET): Delete. * config/mips/mips.c (mips_compute_frame_info): Refer to TARGET_STARTING_FRAME_OFFSET instead of STARTING_FRAME_OFFSET. (mips_starting_frame_offset): New function. (TARGET_STARTING_FRAME_OFFSET): Redefine. * config/mmix/mmix.h (STARTING_FRAME_OFFSET): Delete. * config/mmix/mmix-protos.h (mmix_starting_frame_offset): Delete. * config/mmix/mmix.c (mmix_starting_frame_offset): Make static and return a HOST_WIDE_INT. (TARGET_STARTING_FRAME_OFFSET): Redefine. (mmix_initial_elimination_offset): Refer to TARGET_STARTING_FRAME_OFFSET instead of STARTING_FRAME_OFFSET. * config/pa/pa.h (STARTING_FRAME_OFFSET): Delete. * config/pa/pa.c (pa_starting_frame_offset): New function. (pa_compute_frame_size): Use it instead of STARTING_FRAME_OFFSET. (pa_expand_prologue): Likewise. (TARGET_STARTING_FRAME_OFFSET): Redefine. * config/powerpcspe/aix.h (STARTING_FRAME_OFFSET): Split out !FRAME_GROWS_DOWNWARD handling to... (RS6000_STARTING_FRAME_OFFSET): ...this new macro. * config/powerpcspe/darwin.h (STARTING_FRAME_OFFSET): Split out !FRAME_GROWS_DOWNWARD handling to... (RS6000_STARTING_FRAME_OFFSET): ...this new macro. * config/powerpcspe/powerpcspe.h (STARTING_FRAME_OFFSET): Split out !FRAME_GROWS_DOWNWARD handling to... (RS6000_STARTING_FRAME_OFFSET): ...this new macro. * config/powerpcspe/powerpcspe.c (TARGET_STARTING_FRAME_OFFSET): Redefine. (rs6000_starting_frame_offset): New function. * config/rs6000/aix.h (STARTING_FRAME_OFFSET): Split out !FRAME_GROWS_DOWNWARD handling to... (RS6000_STARTING_FRAME_OFFSET): ...this new macro. * config/rs6000/darwin.h (STARTING_FRAME_OFFSET): Split out !FRAME_GROWS_DOWNWARD handling to... (RS6000_STARTING_FRAME_OFFSET): ...this new macro. * config/rs6000/rs6000.h (STARTING_FRAME_OFFSET): Split out !FRAME_GROWS_DOWNWARD handling to... (RS6000_STARTING_FRAME_OFFSET): ...this new macro. * config/rs6000/rs6000.c (TARGET_STARTING_FRAME_OFFSET): Refine. (rs6000_starting_frame_offset): New function. * config/vax/elf.h (STARTING_FRAME_OFFSET): Delete. * config/vax/vax.h (STARTING_FRAME_OFFSET): Delete. * config/vax/vax.c (vax_starting_frame_offset): New function. (vax_expand_prologue): Use it instead of STARTING_FRAME_OFFSET. (TARGET_STARTING_FRAME_OFFSET): Redefine. * config/xtensa/xtensa.h (STARTING_FRAME_OFFSET): Delete. * config/xtensa/xtensa.c (xtensa_starting_frame_offset): New function. (TARGET_STARTING_FRAME_OFFSET): Redefine. * system.h (STARTING_FRAME_OFFSET): Poison. From-SVN: r254003 | |||||
| 2017-10-23 | Use SCALAR_TYPE_MODE in vect_create_epilog_for_reduction | Richard Sandiford | 2 | -1/+6 | |
| This follows on from similar changes a couple of months ago and is needed when general modes have variable size. 2017-10-23 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * tree-vect-loop.c (vect_create_epilog_for_reduction): Use SCALAR_TYPE_MODE instead of TYPE_MODE. From-SVN: r254002 | |||||
| 2017-10-23 | Use SCALAR_INT_TYPE_MODE in loc_list_from_tree_1 | Richard Sandiford | 2 | -1/+7 | |
| This follows on from similar changes a couple of months ago and is needed when general modes have variable size. 2017-10-23 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * dwarf2out.c (loc_list_from_tree_1): Use SCALAR_INT_TYPE_MODE Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r254001 | |||||
| 2017-10-23 | Use scalar_int/float_mode in brig_langhook_type_for_mode | Richard Sandiford | 2 | -6/+12 | |
| This follows on from similar changes a couple of months ago and is needed when general modes have variable size. 2017-10-23 Richard Sandiford <richard.sandiford@linaro.org> gcc/brig/ * brig-lang.c (brig_langhook_type_for_mode): Use scalar_int_mode and scalar_float_mode. From-SVN: r254000 | |||||
| 2017-10-23 | Use scalar_mode in expand_shift_1 | Richard Sandiford | 2 | -3/+7 | |
| Since this function handles scalar and vector shifts: machine_mode scalar_mode = mode; if (VECTOR_MODE_P (mode)) scalar_mode = GET_MODE_INNER (mode); is equivalent to: scalar_mode = GET_MODE_INNER (mode); 2017-10-23 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * expmed.c (expand_shift_1): Use scalar_mode for scalar_mode. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r253999 | |||||
| 2017-10-23 | re PR tree-optimization/82129 (ICE in compute_antic, at tree-ssa-pre.c:2447) | Richard Biener | 4 | -33/+104 | |
| 2017-10-23 Richard Biener <rguenther@suse.de> PR tree-optimization/82129 * tree-ssa-pre.c (bitmap_set_and): Remove. (compute_antic_aux): Compute ANTIC_OUT intersection in a way canonicalizing expressions in the set to those with lowest ID rather than taking that from the first edge. * gcc.dg/torture/pr82129.c: New testcase. From-SVN: r253998 | |||||
| 2017-10-23 | Fix HWI + -unsigned in combine.c | Richard Sandiford | 2 | -7/+8 | |
| rtx_equal_for_field_assignment_p had: x = adjust_address_nv (x, GET_MODE (y), -subreg_lowpart_offset (GET_MODE (x), GET_MODE (y))); But subreg_lowpart_offset returns an unsigned int and adjust_address_nv takes a HWI, so a subreg offset of 4 would give a memory offset of 0x00000000fffffffffc. 2017-10-23 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * combine.c (rtx_equal_for_field_assignment_p): Use byte_lowpart_offset. From-SVN: r253997 | |||||
| 2017-10-23 | Daily bump. | GCC Administrator | 1 | -1/+1 | |
| From-SVN: r253996 | |||||
| 2017-10-22 | i386.c (ix86_builtin_vectorization_cost): Use existing rtx_cost latencies ↵ | Jan Hubicka | 1 | -0/+13 | |
| instead of having separate table... * i386.c (ix86_builtin_vectorization_cost): Use existing rtx_cost latencies instead of having separate table; make difference between integer and float costs. * i386.h (processor_costs): Remove scalar_stmt_cost, scalar_load_cost, scalar_store_cost, vec_stmt_cost, vec_to_scalar_cost, scalar_to_vec_cost, vec_align_load_cost, vec_unalign_load_cost, vec_store_cost. * x86-tune-costs.h: Remove entries which has been removed in procesor_costs from all tables; make cond_taken_branch_cost and cond_not_taken_branch_cost COST_N_INSNS based. From-SVN: r253993 | |||||
| 2017-10-22 | SUBREG_PROMOTED_VAR_P handling in expand_direct_optab_fn | Richard Sandiford | 2 | -1/+16 | |
| This is needed by the later SVE LAST reductions, where an 8-bit or 16-bit result is zero- rather than sign-extended to 32 bits. I think it could occur in other situations too. 2017-09-19 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * internal-fn.c (expand_direct_optab_fn): Don't assign directly to a SUBREG_PROMOTED_VAR. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r253992 | |||||
| 2017-10-22 | Make more use of GET_MODE_UNIT_PRECISION | Richard Sandiford | 6 | -31/+54 | |
| This patch is like the earlier GET_MODE_UNIT_SIZE one, but for precisions rather than sizes. There is one behavioural change in expand_debug_expr: we shouldn't use lowpart subregs for non-scalar truncations, since that would just reinterpret some of the scalars and drop the rest. (This probably doesn't trigger in practice.) Using TRUNCATE is fine for scalars, since simplify_gen_unary knows when a subreg can be used. 2017-10-22 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * cfgexpand.c (expand_debug_expr): Use GET_MODE_UNIT_PRECISION. (expand_debug_source_expr): Likewise. * combine.c (combine_simplify_rtx): Likewise. * cse.c (fold_rtx): Likewise. * optabs.c (expand_float): Likewise. * simplify-rtx.c (simplify_unary_operation_1): Likewise. (simplify_binary_operation_1): Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r253991 | |||||
| 2017-10-22 | Make more use of HWI_COMPUTABLE_MODE_P | Richard Sandiford | 6 | -12/+25 | |
| This patch uses HWI_COMPUTABLE_MODE_P (X) instead of GET_MODE_PRECISION (X) <= HOST_BITS_PER_WIDE_INT in cases where X also needs to be a scalar integer. 2017-10-22 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * combine.c (simplify_comparison): Use HWI_COMPUTABLE_MODE_P. (record_promoted_value): Likewise. * expr.c (expand_expr_real_2): Likewise. * ree.c (update_reg_equal_equiv_notes): Likewise. (combine_set_extension): Likewise. * rtlanal.c (low_bitmask_len): Likewise. * simplify-rtx.c (neg_const_int): Likewise. (simplify_binary_operation_1): Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r253990 | |||||
| 2017-10-22 | Make more use of subreg_size_lowpart_offset | Richard Sandiford | 4 | -12/+13 | |
| This patch uses subreg_size_lowpart_offset in places that open-coded the calculation. The reload use (and the LRA one that was based on it) seemed to ignore the BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN case; it's not obvious whether that was deliberate or an oversight. 2017-10-22 Richard Sandiford <richard.sandiford@linaro.org> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> gcc/ * lra-spills.c (assign_mem_slot): Use subreg_size_lowpart_offset. * regcprop.c (maybe_mode_change): Likewise. * reload1.c (alter_reg): Likewise. Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com> From-SVN: r253989 | |||||
| 2017-10-22 | Add wide_int version of inchash::hash::add_wide_int | Richard Sandiford | 3 | -7/+15 | |
| This patch adds an inchash hasher for wide_int-based types. It means that hash_tree no longer hashes TREE_INT_CST_EXT_NUNITS, but that was redundant with hashing the type. 2017-10-22 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * inchash.h (inchash::hash::add_wide_int): New function. * lto-streamer-out.c (hash_tree): Use it. From-SVN: r253988 | |||||
| 2017-10-22 | Rename inchash::hash::add_wide_int | Richard Sandiford | 7 | -32/+45 | |
| The name inchash::add_wide_int is a bit misleading, since it sounds like it's hashing a wide_int. This patch renames it to add_hwi instead. 2017-10-22 Richard Sandiford <richard.sandiford@linaro.org> gcc/ * inchash.h (inchash::hash::add_wide_int): Rename to... (inchash::hash::add_hwi): ...this. * ipa-devirt.c (hash_odr_vtable): Update accordingly. (polymorphic_call_target_hasher::hash): Likewise. * ipa-icf.c (sem_function::get_hash, sem_function::init): Likewise. (sem_item::add_expr, sem_item::add_type, sem_variable::get_hash) (sem_item_optimizer::update_hash_by_addr_refs): Likewise. * lto-streamer-out.c (hash_tree): Likewise. * optc-save-gen.awk: Likewise. * tree.c (add_expr): Likewise. From-SVN: r253987 | |||||
| 2017-10-22 | re PR target/52451 (gcc w/i387 float generates fucom rather than fcom for ↵ | Uros Bizjak | 4 | -10/+103 | |
| floating point comparsons) PR target/52451 * config/i386/i386.c (ix86_fp_compare_mode): Return CCFPmode for ordered inequality comparisons even with TARGET_IEEE_FP. testsuite/ChangeLog: PR target/52451 * gcc.dg/torture/pr52451.c: New test. From-SVN: r253986 | |||||
| 2017-10-22 | re PR rtl-optimization/82628 (wrong code at -Os on x86_64-linux-gnu in the ↵ | Uros Bizjak | 4 | -18/+70 | |
| 32-bit mode) PR target/82628 * config/i386/i386.md (cmp<dwi>_doubleword): New pattern. * config/i386/i386.c (ix86_expand_branch) <case E_TImode>: Expand with cmp<dwi>_doubleword. testsuite/ChangeLog: PR target/82628 * gcc.dg/torture/pr82628.c: New test. Co-Authored-By: Jakub Jelinek <jakub@redhat.com> From-SVN: r253985 | |||||
| 2017-10-22 | Move 2 tests from c-c++-common/ to gcc.target/i386/ directory. | Igor Tsimbalist | 3 | -0/+7 | |
| * c-c++-common/attr-nocf-check-1a.c: Remove test. * c-c++-common/attr-nocf-check-3a.c: Likewise. * gcc.target/i386/attr-nocf-check-1a.c: Add test. * gcc.target/i386/attr-nocf-check-3a.c: Likewise. From-SVN: r253984 | |||||
| 2017-10-22 | Daily bump. | GCC Administrator | 1 | -1/+1 | |
| From-SVN: r253982 | |||||
| 2017-10-21 | Add x86 tests for Intel CET implementation. | Igor Tsimbalist | 44 | -11/+828 | |
| gcc/testsuite/ * c-c++-common/attr-nocf-check-1.c: Shorten a cheking message. * c-c++-common/attr-nocf-check-3.c: Likewise. * c-c++-common/fcf-protection-1.c: Add x86 specific message. * c-c++-common/fcf-protection-2.c: Likewise. * c-c++-common/fcf-protection-3.c: Likewise. * c-c++-common/fcf-protection-5.c: Likewise. * c-c++-common/attr-nocf-check-1a.c: New test. * c-c++-common/attr-nocf-check-3a.c: Likewise. * g++.dg/cet-notrack-1.C: Likewise. * gcc.target/i386/cet-intrin-1.c: Likewise. * gcc.target/i386/cet-intrin-10.c: Likewise. * gcc.target/i386/cet-intrin-2.c: Likewise. * gcc.target/i386/cet-intrin-3.c: Likewise. * gcc.target/i386/cet-intrin-4.c: Likewise. * gcc.target/i386/cet-intrin-5.c: Likewise. * gcc.target/i386/cet-intrin-6.c: Likewise. * gcc.target/i386/cet-intrin-7.c: Likewise. * gcc.target/i386/cet-intrin-8.c: Likewise. * gcc.target/i386/cet-intrin-9.c: Likewise. * gcc.target/i386/cet-label.c: Likewise. * gcc.target/i386/cet-notrack-1a.c: Likewise. * gcc.target/i386/cet-notrack-1b.c: Likewise. * gcc.target/i386/cet-notrack-2a.c: Likewise. * gcc.target/i386/cet-notrack-2b.c: Likewise. * gcc.target/i386/cet-notrack-3.c: Likewise. * gcc.target/i386/cet-notrack-4a.c: Likewise. * gcc.target/i386/cet-notrack-4b.c: Likewise. * gcc.target/i386/cet-notrack-5a.c: Likewise. * gcc.target/i386/cet-notrack-5b.c: Likewise. * gcc.target/i386/cet-notrack-6a.c: Likewise. * gcc.target/i386/cet-notrack-6b.c: Likewise. * gcc.target/i386/cet-notrack-7.c: Likewise. * gcc.target/i386/cet-property-1.c: Likewise. * gcc.target/i386/cet-property-2.c: Likewise. * gcc.target/i386/cet-rdssp-1.c: Likewise. * gcc.target/i386/cet-sjlj-1.c: Likewise. * gcc.target/i386/cet-sjlj-2.c: Likewise. * gcc.target/i386/cet-sjlj-3.c: Likewise. * gcc.target/i386/cet-switch-1.c: Likewise. * gcc.target/i386/cet-switch-2.c: Likewise. * lib/target-supports.exp (check_effective_target_cet): New proc. From-SVN: r253979 | |||||
| 2017-10-21 | Add x86 CET documentation. | Igor Tsimbalist | 3 | -3/+64 | |
| gcc/doc/ * extend.texi: Add x86 specific to 'nocf_check' attribute. List CET intrinsics. * invoke.texi: Add -mcet, -mibt, -mshstk options. Add x86 specific to -fcf-protection option. From-SVN: r253978 | |||||
| 2017-10-21 | Update x86 backend to enable Intel CET. | Igor Tsimbalist | 19 | -8/+927 | |
| All platforms except i386 will report the error and do no instrumentation with -finstrument-control-flow option. i386 will provide the implementation based on a specification published by Intel for a new technology called Control-flow Enforcement Technology (CET). The spec is available at https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf The implementation in this patch: 1) enables Control-flow Enforcement Technology (CET), published by Intel. This part introduces i386 specific options -mcet, -mibt and -mshstk, new instructions and intrinsics; 2) provides support for -fcf-protection option and 'nocf_check' attribute by doing needed code instrumentation, which is based on CET features. gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_IBT_SET): New. (OPTION_MASK_ISA_SHSTK_SET): Likewise. (OPTION_MASK_ISA_IBT_UNSET): Likewise. (OPTION_MASK_ISA_SHSTK_UNSET): Likewise. (ix86_handle_option): Add -mibt, -mshstk, -mcet handling. * config.gcc (extra_headers): Add cetintrin.h for x86 targets. (extra_objs): Add cet.o for Linux/x86 targets. (tmake_file): Add i386/t-cet for Linux/x86 targets. * config/i386/cet.c: New file. * config/i386/cetintrin.h: Likewise. * config/i386/t-cet: Likewise. * config/i386/cpuid.h (bit_SHSTK): New. (bit_IBT): Likewise. * config/i386/driver-i386.c (host_detect_local_cpu): Detect and pass IBT and SHSTK bits. * config/i386/i386-builtin-types.def (VOID_FTYPE_UNSIGNED_PVOID): New. (VOID_FTYPE_UINT64_PVOID): Likewise. * config/i386/i386-builtin.def: Add CET intrinsics. * config/i386/i386-c.c (ix86_target_macros_internal): Add OPTION_MASK_ISA_IBT, OPTION_MASK_ISA_SHSTK handling. * config/i386/i386-passes.def: Add pass_insert_endbranch pass. * config/i386/i386-protos.h (make_pass_insert_endbranch): New prototype. * config/i386/i386.c (rest_of_insert_endbranch): New. (pass_data_insert_endbranch): Likewise. (pass_insert_endbranch): Likewise. (make_pass_insert_endbranch): Likewise. (ix86_notrack_prefixed_insn_p): Likewise. (ix86_target_string): Add -mibt, -mshstk flags. (ix86_option_override_internal): Add flag_cf_protection processing. (ix86_valid_target_attribute_inner_p): Set OPT_mibt, OPT_mshstk. (ix86_print_operand): Add 'notrack' prefix output. (ix86_init_mmx_sse_builtins): Add CET intrinsics. (ix86_expand_builtin): Expand CET intrinsics. (x86_output_mi_thunk): Add 'endbranch' instruction. * config/i386/i386.h (TARGET_IBT): New. (TARGET_IBT_P): Likewise. (TARGET_SHSTK): Likewise. (TARGET_SHSTK_P): Likewise. * config/i386/i386.md (unspecv): Add UNSPECV_NOP_RDSSP, UNSPECV_INCSSP, UNSPECV_SAVEPREVSSP, UNSPECV_RSTORSSP, UNSPECV_WRSS, UNSPECV_WRUSS, UNSPECV_SETSSBSY, UNSPECV_CLRSSBSY. (builtin_setjmp_setup): New pattern. (builtin_longjmp): Likewise. (rdssp<mode>): Likewise. (incssp<mode>): Likewise. (saveprevssp): Likewise. (rstorssp): Likewise. (wrss<mode>): Likewise. (wruss<mode>): Likewise. (setssbsy): Likewise. (clrssbsy): Likewise. (nop_endbr): Likewise. * config/i386/i386.opt: Add -mcet, -mibt, -mshstk and -mcet-switch options. * config/i386/immintrin.h: Include <cetintrin.h>. * config/i386/linux-common.h (file_end_indicate_exec_stack_and_cet): New prototype. (TARGET_ASM_FILE_END): New. From-SVN: r253977 | |||||
| 2017-10-21 | pr79683.c: Disable costmodel. | Jan Hubicka | 5 | -301/+93 | |
| * gcc.target/i386/pr79683.c: Disable costmodel. * i386.c (ix86_builtin_vectorization_cost): Use existing rtx_cost latencies instead of having separate table; make difference between integer and float costs. * i386.h (processor_costs): Remove scalar_stmt_cost, scalar_load_cost, scalar_store_cost, vec_stmt_cost, vec_to_scalar_cost, scalar_to_vec_cost, vec_align_load_cost, vec_unalign_load_cost, vec_store_cost. * x86-tune-costs.h: Remove entries which has been removed in procesor_costs from all tables; make cond_taken_branch_cost and cond_not_taken_branch_cost COST_N_INSNS based. Index: testsuite/gcc.target/i386/pr79683.c =================================================================== --- testsuite/gcc.target/i386/pr79683.c (revision 253957) +++ testsuite/gcc.target/i386/pr79683.c (working copy) @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -msse2" } */ +/* { dg-options "-O3 -msse2 -fvect-cost-model=unlimited" } */ struct s { __INT64_TYPE__ a; Index: config/i386/i386.c =================================================================== --- config/i386/i386.c (revision 253957) +++ config/i386/i386.c (working copy) @@ -44051,37 +44051,61 @@ static int ix86_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, tree vectype, int) { + bool fp = false; + machine_mode mode = TImode; + if (vectype != NULL) + { + fp = FLOAT_TYPE_P (vectype); + mode = TYPE_MODE (vectype); + } + switch (type_of_cost) { case scalar_stmt: - return ix86_cost->scalar_stmt_cost; + return fp ? ix86_cost->addss : COSTS_N_INSNS (1); case scalar_load: - return ix86_cost->scalar_load_cost; + /* load/store costs are relative to register move which is 2. Recompute + it to COSTS_N_INSNS so everything have same base. */ + return COSTS_N_INSNS (fp ? ix86_cost->sse_load[0] + : ix86_cost->int_load [2]) / 2; case scalar_store: - return ix86_cost->scalar_store_cost; + return COSTS_N_INSNS (fp ? ix86_cost->sse_store[0] + : ix86_cost->int_store [2]) / 2; case vector_stmt: - return ix86_cost->vec_stmt_cost; + return ix86_vec_cost (mode, + fp ? ix86_cost->addss : ix86_cost->sse_op, + true); case vector_load: - return ix86_cost->vec_align_load_cost; + return ix86_vec_cost (mode, + COSTS_N_INSNS (ix86_cost->sse_load[2]) / 2, + true); case vector_store: - return ix86_cost->vec_store_cost; + return ix86_vec_cost (mode, + COSTS_N_INSNS (ix86_cost->sse_store[2]) / 2, + true); case vec_to_scalar: - return ix86_cost->vec_to_scalar_cost; - case scalar_to_vec: - return ix86_cost->scalar_to_vec_cost; + return ix86_vec_cost (mode, ix86_cost->sse_op, true); + /* We should have separate costs for unaligned loads and gather/scatter. + Do that incrementally. */ case unaligned_load: - case unaligned_store: case vector_gather_load: + return ix86_vec_cost (mode, + COSTS_N_INSNS (ix86_cost->sse_load[2]), + true); + + case unaligned_store: case vector_scatter_store: - return ix86_cost->vec_unalign_load_cost; + return ix86_vec_cost (mode, + COSTS_N_INSNS (ix86_cost->sse_store[2]), + true); case cond_branch_taken: return ix86_cost->cond_taken_branch_cost; @@ -44091,10 +44115,11 @@ ix86_builtin_vectorization_cost (enum ve case vec_perm: case vec_promote_demote: - return ix86_cost->vec_stmt_cost; + return ix86_vec_cost (mode, + ix86_cost->sse_op, true); case vec_construct: - return ix86_cost->vec_stmt_cost * (TYPE_VECTOR_SUBPARTS (vectype) - 1); + return ix86_vec_cost (mode, ix86_cost->sse_op, false); default: gcc_unreachable (); Index: config/i386/i386.h =================================================================== --- config/i386/i386.h (revision 253957) +++ config/i386/i386.h (working copy) @@ -277,18 +277,6 @@ struct processor_costs { parallel. See also ix86_reassociation_width. */ struct stringop_algs *memcpy, *memset; - const int scalar_stmt_cost; /* Cost of any scalar operation, excluding - load and store. */ - const int scalar_load_cost; /* Cost of scalar load. */ - const int scalar_store_cost; /* Cost of scalar store. */ - const int vec_stmt_cost; /* Cost of any vector operation, excluding - load, store, vector-to-scalar and - scalar-to-vector operation. */ - const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ - const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ - const int vec_align_load_cost; /* Cost of aligned vector load. */ - const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ - const int vec_store_cost; /* Cost of vector store. */ const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer cost model. */ const int cond_not_taken_branch_cost;/* Cost of not taken branch for Index: config/i386/x86-tune-costs.h =================================================================== --- config/i386/x86-tune-costs.h (revision 253958) +++ config/i386/x86-tune-costs.h (working copy) @@ -79,17 +79,8 @@ struct processor_costs ix86_size_cost = 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ ix86_size_memcpy, ix86_size_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 1, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 1, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_BYTES (1), /* cond_taken_branch_cost. */ + COSTS_N_BYTES (1), /* cond_not_taken_branch_cost. */ }; /* Processor costs (relative to an add) */ @@ -167,17 +158,8 @@ struct processor_costs i386_cost = { /* 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ i386_memcpy, i386_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs i486_memcpy[2] = { @@ -256,17 +238,8 @@ struct processor_costs i486_cost = { /* 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ i486_memcpy, i486_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs pentium_memcpy[2] = { @@ -343,17 +316,8 @@ struct processor_costs pentium_cost = { 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ pentium_memcpy, pentium_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static const @@ -423,17 +387,8 @@ struct processor_costs lakemont_cost = { 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ pentium_memcpy, pentium_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes @@ -518,17 +473,8 @@ struct processor_costs pentiumpro_cost = 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ pentiumpro_memcpy, pentiumpro_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs geode_memcpy[2] = { @@ -605,17 +551,8 @@ struct processor_costs geode_cost = { 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ geode_memcpy, geode_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs k6_memcpy[2] = { @@ -694,17 +631,8 @@ struct processor_costs k6_cost = { 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ k6_memcpy, k6_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; /* For some reason, Athlon deals better with REP prefix (relative to loops) @@ -784,17 +712,8 @@ struct processor_costs athlon_cost = { 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ athlon_memcpy, athlon_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; /* K8 has optimized REP instruction for medium sized blocks, but for very @@ -883,17 +802,8 @@ struct processor_costs k8_cost = { 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ k8_memcpy, k8_memset, - 4, /* scalar_stmt_cost. */ - 2, /* scalar load_cost. */ - 2, /* scalar_store_cost. */ - 5, /* vec_stmt_cost. */ - 0, /* vec_to_scalar_cost. */ - 2, /* scalar_to_vec_cost. */ - 2, /* vec_align_load_cost. */ - 3, /* vec_unalign_load_cost. */ - 3, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 2, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */ }; /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for @@ -989,17 +899,8 @@ struct processor_costs amdfam10_cost = { 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ amdfam10_memcpy, amdfam10_memset, - 4, /* scalar_stmt_cost. */ - 2, /* scalar load_cost. */ - 2, /* scalar_store_cost. */ - 6, /* vec_stmt_cost. */ - 0, /* vec_to_scalar_cost. */ - 2, /* scalar_to_vec_cost. */ - 2, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 2, /* vec_store_cost. */ - 2, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (2), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; /* BDVER1 has optimized REP instruction for medium sized blocks, but for @@ -1097,17 +998,8 @@ const struct processor_costs bdver1_cost 1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ bdver1_memcpy, bdver1_memset, - 6, /* scalar_stmt_cost. */ - 4, /* scalar load_cost. */ - 4, /* scalar_store_cost. */ - 6, /* vec_stmt_cost. */ - 0, /* vec_to_scalar_cost. */ - 2, /* scalar_to_vec_cost. */ - 4, /* vec_align_load_cost. */ - 4, /* vec_unalign_load_cost. */ - 4, /* vec_store_cost. */ - 4, /* cond_taken_branch_cost. */ - 2, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (4), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */ }; /* BDVER2 has optimized REP instruction for medium sized blocks, but for @@ -1206,17 +1098,8 @@ const struct processor_costs bdver2_cost 1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ bdver2_memcpy, bdver2_memset, - 6, /* scalar_stmt_cost. */ - 4, /* scalar load_cost. */ - 4, /* scalar_store_cost. */ - 6, /* vec_stmt_cost. */ - 0, /* vec_to_scalar_cost. */ - 2, /* scalar_to_vec_cost. */ - 4, /* vec_align_load_cost. */ - 4, /* vec_unalign_load_cost. */ - 4, /* vec_store_cost. */ - 4, /* cond_taken_branch_cost. */ - 2, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (4), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */ }; @@ -1306,17 +1189,8 @@ struct processor_costs bdver3_cost = { 1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ bdver3_memcpy, bdver3_memset, - 6, /* scalar_stmt_cost. */ - 4, /* scalar load_cost. */ - 4, /* scalar_store_cost. */ - 6, /* vec_stmt_cost. */ - 0, /* vec_to_scalar_cost. */ - 2, /* scalar_to_vec_cost. */ - 4, /* vec_align_load_cost. */ - 4, /* vec_unalign_load_cost. */ - 4, /* vec_store_cost. */ - 4, /* cond_taken_branch_cost. */ - 2, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (4), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */ }; /* BDVER4 has optimized REP instruction for medium sized blocks, but for @@ -1405,17 +1279,8 @@ struct processor_costs bdver4_cost = { 1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ bdver4_memcpy, bdver4_memset, - 6, /* scalar_stmt_cost. */ - 4, /* scalar load_cost. */ - 4, /* scalar_store_cost. */ - 6, /* vec_stmt_cost. */ - 0, /* vec_to_scalar_cost. */ - 2, /* scalar_to_vec_cost. */ - 4, /* vec_align_load_cost. */ - 4, /* vec_unalign_load_cost. */ - 4, /* vec_store_cost. */ - 4, /* cond_taken_branch_cost. */ - 2, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (4), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */ }; @@ -1524,17 +1389,8 @@ struct processor_costs znver1_cost = { 4, 4, 3, 6, /* reassoc int, fp, vec_int, vec_fp. */ znver1_memcpy, znver1_memset, - 6, /* scalar_stmt_cost. */ - 4, /* scalar load_cost. */ - 4, /* scalar_store_cost. */ - 6, /* vec_stmt_cost. */ - 0, /* vec_to_scalar_cost. */ - 2, /* scalar_to_vec_cost. */ - 4, /* vec_align_load_cost. */ - 4, /* vec_unalign_load_cost. */ - 4, /* vec_store_cost. */ - 4, /* cond_taken_branch_cost. */ - 2, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (4), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */ }; /* BTVER1 has optimized REP instruction for medium sized blocks, but for @@ -1624,17 +1480,8 @@ const struct processor_costs btver1_cost 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ btver1_memcpy, btver1_memset, - 4, /* scalar_stmt_cost. */ - 2, /* scalar load_cost. */ - 2, /* scalar_store_cost. */ - 6, /* vec_stmt_cost. */ - 0, /* vec_to_scalar_cost. */ - 2, /* scalar_to_vec_cost. */ - 2, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 2, /* vec_store_cost. */ - 2, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (2), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs btver2_memcpy[2] = { @@ -1721,17 +1568,8 @@ const struct processor_costs btver2_cost 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ btver2_memcpy, btver2_memset, - 4, /* scalar_stmt_cost. */ - 2, /* scalar load_cost. */ - 2, /* scalar_store_cost. */ - 6, /* vec_stmt_cost. */ - 0, /* vec_to_scalar_cost. */ - 2, /* scalar_to_vec_cost. */ - 2, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 2, /* vec_store_cost. */ - 2, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (2), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs pentium4_memcpy[2] = { @@ -1809,17 +1647,8 @@ struct processor_costs pentium4_cost = { 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ pentium4_memcpy, pentium4_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs nocona_memcpy[2] = { @@ -1900,17 +1729,8 @@ struct processor_costs nocona_cost = { 1, 1, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ nocona_memcpy, nocona_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs atom_memcpy[2] = { @@ -1989,17 +1809,8 @@ struct processor_costs atom_cost = { 2, 2, 2, 2, /* reassoc int, fp, vec_int, vec_fp. */ atom_memcpy, atom_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs slm_memcpy[2] = { @@ -2078,17 +1889,8 @@ struct processor_costs slm_cost = { 1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ slm_memcpy, slm_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 4, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; static stringop_algs intel_memcpy[2] = { @@ -2167,17 +1969,8 @@ struct processor_costs intel_cost = { 1, 4, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ intel_memcpy, intel_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 4, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; /* Generic should produce code tuned for Core-i7 (and newer chips) @@ -2265,17 +2058,8 @@ struct processor_costs generic_cost = { 1, 2, 1, 1, /* reassoc int, fp, vec_int, vec_fp. */ generic_memcpy, generic_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; /* core_cost should produce code tuned for Core familly of CPUs. */ @@ -2366,16 +2150,7 @@ struct processor_costs core_cost = { 1, 4, 2, 2, /* reassoc int, fp, vec_int, vec_fp. */ core_memcpy, core_memset, - 1, /* scalar_stmt_cost. */ - 1, /* scalar load_cost. */ - 1, /* scalar_store_cost. */ - 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ - 1, /* scalar_to_vec_cost. */ - 1, /* vec_align_load_cost. */ - 2, /* vec_unalign_load_cost. */ - 1, /* vec_store_cost. */ - 3, /* cond_taken_branch_cost. */ - 1, /* cond_not_taken_branch_cost. */ + COSTS_N_INSNS (3), /* cond_taken_branch_cost. */ + COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */ }; From-SVN: r253975 | |||||
| 2017-10-21 | * gcc-interface/Makefile.in: Remove bogus settings for VxWorks. | Eric Botcazou | 2 | -9/+9 | |
| From-SVN: r253973 | |||||
| 2017-10-21 | Fix typos | Eric Botcazou | 2 | -5/+5 | |
| From-SVN: r253972 | |||||
| 2017-10-21 | utils.c (pad_type_hash): Use hashval_t for hash value. | Eric Botcazou | 7 | -10/+79 | |
| * gcc-interface/utils.c (pad_type_hash): Use hashval_t for hash value. (convert): Do not use an unchecked conversion for converting from a type to another type padding it. From-SVN: r253971 | |||||
| 2017-10-21 | re PR fortran/82586 ([PDT] ICE: write_symbol(): bad module symbol) | Paul Thomas | 10 | -17/+146 | |
| 2017-10-21 Paul Thomas <pault@gcc.gnu.org> PR fortran/82586 * decl.c (gfc_get_pdt_instance): Remove the error message that the parameter does not have a corresponding component since this is now taken care of when the derived type is resolved. Go straight to error return instead. (gfc_match_formal_arglist): Make the PDT relevant errors immediate so that parsing of the derived type can continue. (gfc_match_derived_decl): Do not check the match status on return from gfc_match_formal_arglist for the same reason. * resolve.c (resolve_fl_derived0): Check that each type parameter has a corresponding component. PR fortran/82587 * resolve.c (resolve_generic_f): Check that the derived type can be used before resolving the struture constructor. PR fortran/82589 * symbol.c (check_conflict): Add the conflicts involving PDT KIND and LEN attributes. 2017-10-21 Paul Thomas <pault@gcc.gnu.org> PR fortran/82586 * gfortran.dg/pdt_16.f03 : New test. * gfortran.dg/pdt_4.f03 : Catch the changed messages. * gfortran.dg/pdt_8.f03 : Ditto. PR fortran/82587 * gfortran.dg/pdt_17.f03 : New test. PR fortran/82589 * gfortran.dg/pdt_18.f03 : New test. From-SVN: r253970 | |||||
| 2017-10-21 | Fix wording | Eric Botcazou | 1 | -1/+1 | |
| From-SVN: r253969 | |||||
| 2017-10-21 | Fix invalid path::iterator test | Jonathan Wakely | 2 | -3/+7 | |
| * testsuite/experimental/filesystem/path/itr/traversal.cc: Do not increment past-the-end iterators. From-SVN: r253967 | |||||
| 2017-10-21 | Daily bump. | GCC Administrator | 1 | -1/+1 | |
| From-SVN: r253966 | |||||
| 2017-10-20 | Update value of __cpp_lib_chrono feature-test macro | Jonathan Wakely | 3 | -2/+14 | |
| * include/std/chrono (__cpp_lib_chrono): Update macro value to indicate support for P0505R0. * testsuite/20_util/duration/arithmetic/constexpr_c++17.cc: Check for updated macro. From-SVN: r253959 | |||||
| 2017-10-20 | * x86-tune-costs.h (intel_cost, generic_cost): Fix move costs. | Jan Hubicka | 2 | -19/+23 | |
| From-SVN: r253958 | |||||
| 2017-10-20 | debug/dwarf: support 64-bit DWARF in byte order check | Ian Lance Taylor | 6 | -17/+88 | |
| Also fix 64-bit DWARF to read a 64-bit abbrev offset in the compilation unit. This is a backport of https://golang.org/cl/71171, which will be in the Go 1.10 release, to the gofrontend copy. Doing it now because AIX is pretty much the only system that uses 64-bit DWARF. Reviewed-on: https://go-review.googlesource.com/72250 From-SVN: r253955 | |||||
| 2017-10-20 | [C++ PATCH] AS_BASETYPE | Nathan Sidwell | 2 | -17/+18 | |
| https://gcc.gnu.org/ml/gcc-patches/2017-10/msg01376.html * class.c (layout_class_type): Cleanup as-base creation, determine mode here. (finish_struct_1): ... not here. From-SVN: r253954 | |||||
| 2017-10-20 | Define __cpp_lib_byte feature-test macro | Jonathan Wakely | 3 | -1/+14 | |
| * include/c_global/cstddef: Define __cpp_lib_byte feature-test macro. * testsuite/18_support/byte/requirements.cc: Check macro. From-SVN: r253952 | |||||
| 2017-10-20 | Add tests for -fcf-protection option and nocf_check attribute. | Igor Tsimbalist | 9 | -0/+93 | |
| * c-c++-common/fcf-protection-1.c: New test. * c-c++-common/fcf-protection-2.c: Likewise. * c-c++-common/fcf-protection-3.c: Likewise. * c-c++-common/fcf-protection-4.c: Likewise. * c-c++-common/fcf-protection-5.c: Likewise. * c-c++-common/attr-nocf-check-1.c: Likewise. * c-c++-common/attr-nocf-check-2.c: Likewise. * c-c++-common/attr-nocf-check-3.c: Likewise. From-SVN: r253949 | |||||
| 2017-10-20 | s-osinte__linux.ads (Relative_Timed_Wait): Add variable needed for using ↵ | Pierre-Marie de Rodat | 13 | -454/+515 | |
| monotonic clock. gcc/ada/ 2017-10-20 Doug Rupp <rupp@adacore.com> * libgnarl/s-osinte__linux.ads (Relative_Timed_Wait): Add variable needed for using monotonic clock. * libgnarl/s-taprop__linux.adb: Revert previous monotonic clock changes. * libgnarl/s-taprop__linux.adb, s-taprop__posix.adb: Unify and factor out monotonic clock related functions body. (Timed_Sleep, Timed_Delay, Montonic_Clock, RT_Resolution, Compute_Deadline): Move to... * libgnarl/s-tpopmo.adb: ... here. New separate package body. 2017-10-20 Ed Schonberg <schonberg@adacore.com> * sem_util.adb (Is_Controlling_Limited_Procedure): Handle properly the case where the controlling formal is an anonymous access to interface type. * exp_ch9.adb (Extract_Dispatching_Call): If controlling actual is an access type, handle properly the the constructed dereference that designates the object used in the rewritten synchronized call. (Parameter_Block_Pack): If the type of the actual is by-copy, its generated declaration in the parameter block does not need an initialization even if the type is a null-excluding access type, because it will be initialized with the value of the actual later on. (Parameter_Block_Pack): Do not add controlling actual to parameter block when its type is by-copy. 2017-10-20 Justin Squirek <squirek@adacore.com> * sem_ch8.adb (Update_Use_Clause_Chain): Add sanity check to verify scope stack traversal into the context clause. gcc/testsuite/ 2017-10-20 Ed Schonberg <schonberg@adacore.com> * gnat.dg/sync_iface_call.adb, gnat.dg/sync_iface_call_pkg.ads, gnat.dg/sync_iface_call_pkg2.adb, gnat.dg/sync_iface_call_pkg2.ads: New testcase. From-SVN: r253948 | |||||
| 2017-10-20 | [multiple changes] | Pierre-Marie de Rodat | 10 | -41/+41 | |
| 2017-10-20 Bob Duff <duff@adacore.com> * sinfo.ads: Fix a comment typo. 2017-10-20 Eric Botcazou <ebotcazou@adacore.com> * doc/gnat_ugn/building_executable_programs_with_gnat.rst (-flto): Add warning against usage in conjunction with -gnatn. (-fdump-xref): Delete entry. * doc/gnat_ugn/gnat_utility_programs.rst (--ext): Remove mention of -fdump-xref switch. * gnat_ugn.texi: Regenerate. 2017-10-20 Hristian Kirtchev <kirtchev@adacore.com> * sem_type.adb, exp_util.adb, sem_util.adb, sem_dim.adb, sem_elab.adb: Minor reformatting. From-SVN: r253947 | |||||
| 2017-10-20 | Add ChangeLog entries, missing from last commit | Pierre-Marie de Rodat | 1 | -0/+90 | |
| From-SVN: r253946 | |||||
| 2017-10-20 | sem_dim.adb (Analyze_Dimension_Binary_Op): Accept with a warning to compare ↵ | Pierre-Marie de Rodat | 22 | -111/+259 | |
| a dimensioned expression with a literal. gcc/ada/ 2017-10-20 Yannick Moy <moy@adacore.com> * sem_dim.adb (Analyze_Dimension_Binary_Op): Accept with a warning to compare a dimensioned expression with a literal. (Dim_Warning_For_Numeric_Literal): Do not issue a warning for the special value zero. * doc/gnat_ugn/gnat_and_program_execution.rst: Update description of dimensionality system in GNAT. * gnat_ugn.texi: Regenerate. 2017-10-20 Yannick Moy <moy@adacore.com> * sem_ch6.adb (Analyze_Expression_Function.Freeze_Expr_Types): Remove inadequate silencing of errors. * sem_util.adb (Check_Part_Of_Reference): Do not issue an error when checking the subprogram body generated from an expression function, when this is done as part of the preanalysis done on expression functions, as the subprogram body may not yet be attached in the AST. The error if any will be issued later during the analysis of the body. (Is_Aliased_View): Trivial rewrite with Is_Formal_Object. 2017-10-20 Arnaud Charlet <charlet@adacore.com> * sem_ch8.adb (Update_Chain_In_Scope): Add missing [-gnatwu] marker for warning on ineffective use clause. 2017-10-20 Eric Botcazou <ebotcazou@adacore.com> * exp_ch11.ads (Warn_If_No_Local_Raise): Declare. * exp_ch11.adb (Expand_Exception_Handlers): Use Warn_If_No_Local_Raise to issue the warning on the absence of local raise. (Possible_Local_Raise): Do not issue the warning for Call_Markers. (Warn_If_No_Local_Raise): New procedure to issue the warning on the absence of local raise. * sem_elab.adb: Add with and use clauses for Exp_Ch11. (Record_Elaboration_Scenario): Call Possible_Local_Raise in the cases where a scenario could give rise to raising Program_Error. * sem_elab.adb: Typo fixes. * fe.h (Warn_If_No_Local_Raise): Declare. * gcc-interface/gigi.h (get_exception_label): Change return type. * gcc-interface/trans.c (gnu_constraint_error_label_stack): Change to simple vector of Entity_Id. (gnu_storage_error_label_stack): Likewise. (gnu_program_error_label_stack): Likewise. (gigi): Adjust to above changes. (Raise_Error_to_gnu): Likewise. (gnat_to_gnu) <N_Goto_Statement>: Set TREE_USED on the label. (N_Push_Constraint_Error_Label): Push the label onto the stack. (N_Push_Storage_Error_Label): Likewise. (N_Push_Program_Error_Label): Likewise. (N_Pop_Constraint_Error_Label): Pop the label from the stack and issue a warning on the absence of local raise. (N_Pop_Storage_Error_Label): Likewise. (N_Pop_Program_Error_Label): Likewise. (push_exception_label_stack): Delete. (get_exception_label): Change return type to Entity_Id and adjust. * gcc-interface/utils2.c (build_goto_raise): Change type of first parameter to Entity_Id and adjust. Set TREE_USED on the label. (build_call_raise): Adjust calls to get_exception_label and also build_goto_raise. (build_call_raise_column): Likewise. (build_call_raise_range): Likewise. * doc/gnat_ugn/building_executable_programs_with_gnat.rst (-gnatw.x): Document actual default behavior. 2017-10-20 Piotr Trojanek <trojanek@adacore.com> * einfo.ads: Minor consistent punctuation in comment. All numbered items in the comment of Is_Internal are now terminated with a period. 2017-10-20 Piotr Trojanek <trojanek@adacore.com> * exp_util.adb (Build_Temporary): Mark created temporary entity as internal. 2017-10-20 Piotr Trojanek <trojanek@adacore.com> * sem_type.adb (In_Generic_Actual): Simplified. 2017-10-20 Justin Squirek <squirek@adacore.com> * sem_ch12.adb (Check_Formal_Package_Instance): Add sanity check to verify a renaming exists for a generic formal before comparing it to the actual as defaulted formals will not have a renamed_object. 2017-10-20 Javier Miranda <miranda@adacore.com> * exp_ch6.adb (Replace_Returns): Fix wrong management of N_Block_Statement nodes. gcc/testsuite/ 2017-10-20 Justin Squirek <squirek@adacore.com> * gnat.dg/default_pkg_actual.adb, gnat.dg/default_pkg_actual2.adb: New testcases. From-SVN: r253945 | |||||
| 2017-10-20 | exp_aggr.adb (Initialize_Array_Component): Avoid adjusting a component of an ↵ | Pierre-Marie de Rodat | 22 | -97/+195 | |
| array aggregate if... gcc/ada/ 2017-10-20 Bob Duff <duff@adacore.com> * exp_aggr.adb (Initialize_Array_Component): Avoid adjusting a component of an array aggregate if it is initialized by a build-in-place function call. * exp_ch6.adb (Is_Build_In_Place_Result_Type): Use -gnatd.9 to disable bip for nonlimited types. * debug.adb: Document -gnatd.9. 2017-10-20 Bob Duff <duff@adacore.com> * sem_ch12.adb: Remove redundant setting of Parent. 2017-10-20 Eric Botcazou <ebotcazou@adacore.com> * sem_ch4.adb (Find_Concatenation_Types): Filter out operators if one of the operands is a string literal. 2017-10-20 Bob Duff <duff@adacore.com> * einfo.ads: Comment fix. 2017-10-20 Clement Fumex <fumex@adacore.com> * switch-c.adb: Remove -gnatwm from the switches triggered by -gnateC. 2017-10-20 Ed Schonberg <schonberg@adacore.com> * sem_dim.adb (Extract_Power): Accept dimension values that are not non-negative integers when the dimensioned base type is an Integer type. gcc/testsuite/ 2017-10-20 Ed Schonberg <schonberg@adacore.com> * gnat.dg/dimensions.adb, gnat.dg/dimensions.ads: New testcase. From-SVN: r253941 | |||||
| 2017-10-20 | sinfo.ads, sinfo.adb (Alloc_For_BIP_Return): New flag to indicate that an ↵ | Bob Duff | 7 | -16/+67 | |
| allocator came from a b-i-p return statement. 2017-10-20 Bob Duff <duff@adacore.com> * sinfo.ads, sinfo.adb (Alloc_For_BIP_Return): New flag to indicate that an allocator came from a b-i-p return statement. * exp_ch4.adb (Expand_Allocator_Expression): Avoid adjusting the return object of a nonlimited build-in-place function call. * exp_ch6.adb (Expand_N_Extended_Return_Statement): Set the Alloc_For_BIP_Return flag on generated allocators. * sem_ch5.adb (Analyze_Assignment): Move Assert to where it can't fail. If the N_Assignment_Statement has been transformed into something else, then Should_Transform_BIP_Assignment won't work. * exp_ch3.adb (Expand_N_Object_Declaration): A previous revision said, "Remove Adjust if we're building the return object of an extended return statement in place." Back out that part of the change, because the Alloc_For_BIP_Return flag is now used for that. From-SVN: r253940 | |||||
| 2017-10-20 | i386.md (isa): Remove fma_avx512f. | Jakub Jelinek | 3 | -33/+35 | |
| * config/i386/i386.md (isa): Remove fma_avx512f. * config/i386/sse.md (<avx512>_fmadd_<mode>_mask<round_name>, <avx512>_fmadd_<mode>_mask3<round_name>, <avx512>_fmsub_<mode>_mask<round_name>, <avx512>_fmsub_<mode>_mask3<round_name>, <avx512>_fnmadd_<mode>_mask<round_name>, <avx512>_fnmadd_<mode>_mask3<round_name>, <avx512>_fnmsub_<mode>_mask<round_name>, <avx512>_fnmsub_<mode>_mask3<round_name>, <avx512>_fmaddsub_<mode>_mask<round_name>, <avx512>_fmaddsub_<mode>_mask3<round_name>, <avx512>_fmsubadd_<mode>_mask<round_name>, <avx512>_fmsubadd_<mode>_mask3<round_name>): Remove isa attribute. (*vec_widen_umult_even_v16si<mask_name>, *vec_widen_smult_even_v16si<mask_name>): Likewise. (<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>): Likewise. From-SVN: r253939 | |||||
| 2017-10-20 | Add documentation for fcf-protection option and nocf_check attribute | Igor Tsimbalist | 5 | -5/+106 | |
| gcc/doc/ * extend.texi: Add 'nocf_check' documentation. * gimple.texi: Add second parameter to gimple_build_call_from_tree. * invoke.texi: Add -fcf-protection documentation. * rtl.texi: Add REG_CALL_NOTRACK documenation. From-SVN: r253938 | |||||
| 2017-10-20 | re PR tree-optimization/82473 (ICE in vect_get_vec_def_for_stmt_copy, at ↵ | Richard Biener | 4 | -2/+38 | |
| tree-vect-stmts.c:1524) 2017-10-20 Richard Biener <rguenther@suse.de> PR tree-optimization/82473 * tree-vect-loop.c (vectorizable_reduction): Properly get at the largest input type. * gcc.dg/torture/pr82473.c: New testcase. From-SVN: r253937 | |||||
| 2017-10-20 | Add generic part for Intel CET enabling. The spec is available at | Igor Tsimbalist | 16 | -8/+188 | |
| https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf A proposal is to introduce a target independent flag -fcf-protection=[none|branch|return|full] with a semantic to instrument a code to control validness or integrity of control-flow transfers using jump and call instructions. The main goal is to detect and block a possible malware execution through transfer the execution to unknown target address. Implementation could be either software or target based. Any target platforms can provide their implementation for instrumentation under this option. The compiler should instrument any control-flow transfer points in a program (ex. call/jmp/ret) as well as any landing pads, which are targets of control-flow transfers. A new 'nocf_check' attribute is introduced to provide hand tuning support. The attribute directs the compiler to skip a call to a function and a function's landing pad from instrumentation. The attribute can be used for function and pointer to function types, otherwise it will be ignored. Currently all platforms except i386 will report the error and do no instrumentation. i386 will provide the implementation based on a specification published by Intel for a new technology called Control-flow Enforcement Technology (CET). gcc/c-family/ * c-attribs.c (handle_nocf_check_attribute): New function. (c_common_attribute_table): Add 'nocf_check' handling. gcc/c/ * gimple-parser.c: Add second argument NULL to gimple_build_call_from_tree. gcc/ * attrib.c (comp_type_attributes): Check nocf_check attribute. * cfgexpand.c (expand_call_stmt): Set REG_CALL_NOCF_CHECK for call insn. * combine.c (distribute_notes): Add REG_CALL_NOCF_CHECK handling. * common.opt: Add fcf-protection flag. * emit-rtl.c (try_split): Add REG_CALL_NOCF_CHECK handling. * flag-types.h: Add enum cf_protection_level. * gimple.c (gimple_build_call_from_tree): Add second parameter. Add 'nocf_check' attribute propagation to gimple call. * gimple.h (gf_mask): Add GF_CALL_NOCF_CHECK. (gimple_build_call_from_tree): Update prototype. (gimple_call_nocf_check_p): New function. (gimple_call_set_nocf_check): Likewise. * gimplify.c: Add second argument to gimple_build_call_from_tree. * ipa-icf.c: Add nocf_check attribute in statement hash. * recog.c (peep2_attempt): Add REG_CALL_NOCF_CHECK handling. * reg-notes.def: Add REG_NOTE (CALL_NOCF_CHECK). * toplev.c (process_options): Add flag_cf_protection handling. From-SVN: r253936 | |||||
| 2017-10-20 | [arm] Fix architecture selection when building libatomic with automatic FPU ↵ | Richard Earnshaw | 3 | -2/+8 | |
| selection Libatomic builds a few functions for Arm with an explicit -march option. This option does not specify an FPU, which can lead to problems when targeting a hard-float or softfp environment since the architecture appears to be incompatible with the selected ABI. The fix is simple enough, just add +fp (the minimum floating point option) to the architecture. We don't use anything from the FP architecture, so it shouldn't really change anything; and if we are building for -mfloat-abi=soft the canonicalization process will remove the unnecessary fp attributes anyway. * Makefile.am: (IFUNC_OPTIONS): Set the architecture to -march=armv7-a+fp on Linux/Arm. * Makefile.in: Regenerated. From-SVN: r253935 | |||||
| 2017-10-20 | * x86-tune-costs.h (core_cost): Fix div, move and sqrt latencies. | Jan Hubicka | 2 | -17/+24 | |
| From-SVN: r253934 | |||||
| 2017-10-20 | re PR tree-optimization/82603 (ICE in ifcvt_local_dce w/ -O2 ↵ | Richard Biener | 4 | -1/+37 | |
| -ftree-loop-vectorize) 2017-10-20 Richard Biener <rguenther@suse.de> PR tree-optimization/82603 * tree-if-conv.c (predicate_mem_writes): Make sure to only remove false predicated stores. * gcc.dg/torture/pr82603.c: New testcase. From-SVN: r253933 | |||||
| 2017-10-20 | 2017-10-20 Richard Biener <rguenther@suse.de> | Richard Biener | 3 | -32/+39 | |
| * graphite-isl-ast-to-gimple.c (translate_isl_ast_to_gimple::graphite_copy_stmts_from_block): Remove return value and simplify, dump copied stmt after lhs adjustment. (translate_isl_ast_to_gimple::translate_isl_ast_node_user): Reduce dump verbosity. (gsi_insert_earliest): Likewise. (translate_isl_ast_to_gimple::copy_bb_and_scalar_dependences): Adjust. * graphite.c (print_global_statistics): Adjust dumping. (print_graphite_scop_statistics): Likewise. (print_graphite_statistics): Do not dump loops here. (graphite_transform_loops): But here. From-SVN: r253930 | |||||
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