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In --enable-default-pie mode compiler should switch from
using crtend.o to crtendS.o. On sparc it is especially important
because crtend.o contains PIC-unfriendly code.
We use GNU_USER_TARGET_ENDFILE_SPEC as a baseline spec to get
crtendS.o instead of crtend.o in !no-pie mode.
gcc:
2020-07-14 Sergei Trofimovich <siarheit@google.com>
PR target/96190
* config/sparc/linux.h (ENDFILE_SPEC): Use GNU_USER_TARGET_ENDFILE_SPEC
to get crtendS.o for !no-pie mode.
* config/sparc/linux64.h (ENDFILE_SPEC): Ditto.
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Similar to the recent changes to basic_istream::ignore, this change
ensures that _M_gcount doesn't overflow when extracting characters and
inserting them into another streambuf.
The solution used here is to use unsigned long long for the count. We
assume that the number of characters extracted won't exceed the maximum
value for that type, but even if it does we avoid any undefined
behaviour.
libstdc++-v3/ChangeLog:
* include/bits/istream.tcc
(basic_istream::get(__streambuf_type&, char_type): Use unsigned
long long for counter and check if it would overflow _M_gcount.
* testsuite/27_io/basic_istream/get/char/lwg3464.cc: New test.
* testsuite/27_io/basic_istream/get/wchar_t/lwg3464.cc: New test.
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In vectorizable_simd_clone_call, type compatibility is handled based on
the number of elements and the type compatibility of elements, which is
not enough. This patch add VIEW_CONVERT_EXPRs if the arguments types
and return type of simd clone function are distinct with the vectype of
stmt.
2020-07-20 Yang Yang <yangyang305@huawei.com>
gcc/ChangeLog:
* tree-vect-stmts.c (vectorizable_simd_clone_call): Add
VIEW_CONVERT_EXPRs if the arguments types and return type
of simd clone function are distinct with the vectype of stmt.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/pr96195.c: New test.
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Currently, __atomic_thread_fence(seq_cst) on x86 and x86-64 generates
mfence instruction. A dummy atomic instruction (a lock-prefixed instruction
or xchg with a memory operand) would provide the same sequential consistency
guarantees while being more efficient on most current CPUs. The mfence
instruction additionally orders non-temporal stores, which is not relevant
for atomic operations and are not ordered by seq_cst atomic operations anyway.
2020-07-20 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/95750
* config/i386/i386.h (TARGET_AVOID_MFENCE):
Rename from TARGET_USE_XCHG_FOR_ATOMIC_STORE.
* config/i386/sync.md (mfence_sse2): Disable for TARGET_AVOID_MFENCE.
(mfence_nosse): Enable also for TARGET_AVOID_MFENCE. Emit stack
referred memory in word_mode.
(mem_thread_fence): Do not generate mfence_sse2 pattern when
TARGET_AVOID_MFENCE is true.
(atomic_store<mode>): Update for rename.
* config/i386/x86-tune.def (X86_TUNE_AVOID_MFENCE):
Rename from X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE.
gcc/testsuite/ChangeLog:
PR target/95750
* gcc.target/i386/pr95750.c: New test.
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Resolves:
PR middle-end/95189 - memcmp being wrongly stripped like strcm
PR middle-end/95886 - suboptimal memcpy with embedded zero bytes
gcc/ChangeLog:
PR middle-end/95189
PR middle-end/95886
* builtins.c (inline_expand_builtin_string_cmp): Rename...
(inline_expand_builtin_bytecmp): ...to this.
(builtin_memcpy_read_str): Don't expect data to be nul-terminated.
(expand_builtin_memory_copy_args): Handle object representations
with embedded nul bytes.
(expand_builtin_memcmp): Same.
(expand_builtin_strcmp): Adjust call to naming change.
(expand_builtin_strncmp): Same.
* expr.c (string_constant): Create empty strings with nonzero size.
* fold-const.c (c_getstr): Rename locals and update comments.
* tree.c (build_string): Accept null pointer argument.
(build_string_literal): Same.
* tree.h (build_string): Provide a default.
(build_string_literal): Same.
gcc/testsuite/ChangeLog:
PR middle-end/95189
PR middle-end/95886
* gcc.dg/memcmp-pr95189.c: New test.
* gcc.dg/strncmp-3.c: New test.
* gcc.target/i386/memcpy-pr95886.c: New test.
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gcc/po/
* gcc.pot: Regenerate.
libcpp/po/
* cpplib.pot: Regenerate.
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gcc/c-family/ChangeLog:
PR c/96249
* c.opt: Remove stray text.
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This fixes a bug in jit.exp which causes the DejaGnu output of the
libgccjit testsuite to be nondeterministically truncated. This bug was
copied from DejaGnu's own implementation of the host_execute function.
See the upstream bug report [0] where the maintainers point out that the
regex patterns in host_execute should (but don't currently) explicitly
match newlines to avoid relying on DejaGnu not reading more than one
line of the output (which is not guaranteed).
This should make it easier to test jit patches in the future, since it
makes it possible to reliably compare the output of two jit.sum files
(as with the other tests in GCC).
[0] : https://debbugs.gnu.org/cgi/bugreport.cgi?bug=42399
gcc/testsuite/
PR jit/69435
* jit.dg/jit.exp (fixed_host_execute): Fix regex patterns to
always explicitly match newlines.
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This removes a write-only array in
rev_post_order_and_mark_dfs_back_seme.
2020-07-20 Richard Biener <rguenther@suse.de>
* cfganal.c (rev_post_order_and_mark_dfs_back_seme): Remove
write-only post array.
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I found the linemap logic dealing with running out of column numbers
confusing. There's no need for completely separate code blocks there,
as we can rely on the masking operations working all the way down to
zero bits. The two binary searches for linemap lookups could do with
modernization of placing the var decls at their initialization point.
(These two searches work in opposite directions, and while lower_bound
would work there, the caching got in the way and I decided to be
conservative.)
libcpp/
* line-map.c (linemap_add): Simplify column overflow calculation.
Add comment about range and column bit init.
(linemap_ordinary_map_lookup): Refactor for RAII
(linemap_macro_map_lookup): Likewise.
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When working on __builtin_bit_cast that needs to handle bitfields too,
I've made the following change to handle at least some bitfields in
fold_const_aggregate_ref_1 (those that have integral representative).
It already handles some, but only those that start and end at byte
boundaries.
2020-07-20 Jakub Jelinek <jakub@redhat.com>
PR libstdc++/93121
* gimple-fold.c (fold_const_aggregate_ref_1): For COMPONENT_REF
of a bitfield not aligned on byte boundaries try to
fold_ctor_reference DECL_BIT_FIELD_REPRESENTATIVE if any and
adjust it depending on endianity.
* gcc.dg/tree-ssa/pr93121-2.c: New test.
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When working on __builtin_bit_cast that needs to handle bitfields too,
I've made the following change to handle at least some bitfields in
native_encode_initializer (those that have integral representative).
2020-07-20 Jakub Jelinek <jakub@redhat.com>
PR libstdc++/93121
* fold-const.c (native_encode_initializer): Handle bit-fields.
* gcc.dg/tree-ssa/pr93121-1.c: New test.
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Apparently local labels end up in the gimple dumps. For mmix,
local labels that for other targets look like ".LC0" or "LC.0"
instead look like "LC:0". Committed as obvious.
gcc/testsuite:
* gcc.dg/const-uniq-1.c: Adjust scanned pattern for mmix.
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The test is gated on effective-target hard_float but what it
really requires is a sqrtf insn (SFmode, not DFmode). (It
indeed passes for mmix-knuth-mmixware if the sqrtf is changed to
sqrt and float to double; there is a DFmode sqrt insn.)
Committed.
gcc/testsuite:
* gcc.dg/cdce3.c: Skip for mmix.
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Power9 supports vector load/store instruction lxvl/stxvl which allow
us to operate partial vectors with one specific length. This patch
extends some of current mask-based partial vectors support code for
length-based approach, also adds some length specific support code.
So far it assumes that we can only have one partial vectors approach
at the same time, it will disable to use partial vectors if both
approaches co-exist.
Like the description of optab len_load/len_store, the length-based
approach can have two flavors, one is length in bytes, the other is
length in lanes. This patch is mainly implemented and tested for
length in bytes, but as Richard S. suggested, most of code has
considered both flavors.
This also introduces one parameter vect-partial-vector-usage allow
users to control when the loop vectorizer considers using partial
vectors as an alternative to falling back to scalar code.
gcc/ChangeLog:
* config/rs6000/rs6000.c (rs6000_option_override_internal):
Set param_vect_partial_vector_usage to 0 explicitly.
* doc/invoke.texi (vect-partial-vector-usage): Document new option.
* optabs-query.c (get_len_load_store_mode): New function.
* optabs-query.h (get_len_load_store_mode): New declare.
* params.opt (vect-partial-vector-usage): New.
* tree-vect-loop-manip.c (vect_set_loop_controls_directly): Add the
handlings for vectorization using length-based partial vectors, call
vect_gen_len for length generation, and rename some variables with
items instead of scalars.
(vect_set_loop_condition_partial_vectors): Add the handlings for
vectorization using length-based partial vectors.
(vect_do_peeling): Allow remaining eiters less than epilogue vf for
LOOP_VINFO_USING_PARTIAL_VECTORS_P.
* tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Init
epil_using_partial_vectors_p.
(_loop_vec_info::~_loop_vec_info): Call release_vec_loop_controls
for lengths destruction.
(vect_verify_loop_lens): New function.
(vect_analyze_loop): Add handlings for epilogue of loop when it's
marked to use vectorization using partial vectors.
(vect_analyze_loop_2): Add the check to allow only one vectorization
approach using partial vectorization at the same time. Check param
vect-partial-vector-usage for partial vectors decision. Mark
LOOP_VINFO_EPIL_USING_PARTIAL_VECTORS_P if the epilogue is
considerable to use partial vectors. Call release_vec_loop_controls
for lengths destruction.
(vect_estimate_min_profitable_iters): Adjust for loop vectorization
using length-based partial vectors.
(vect_record_loop_mask): Init factor to 1 for vectorization using
mask-based partial vectors.
(vect_record_loop_len): New function.
(vect_get_loop_len): Likewise.
* tree-vect-stmts.c (check_load_store_for_partial_vectors): Add
checks for vectorization using length-based partial vectors. Factor
some code to lambda function get_valid_nvectors.
(vectorizable_store): Add handlings when using length-based partial
vectors.
(vectorizable_load): Likewise.
(vect_gen_len): New function.
* tree-vectorizer.h (struct rgroup_controls): Add field factor
mainly for length-based partial vectors.
(vec_loop_lens): New typedef.
(_loop_vec_info): Add lens and epil_using_partial_vectors_p.
(LOOP_VINFO_EPIL_USING_PARTIAL_VECTORS_P): New macro.
(LOOP_VINFO_LENS): Likewise.
(LOOP_VINFO_FULLY_WITH_LENGTH_P): Likewise.
(vect_record_loop_len): New declare.
(vect_get_loop_len): Likewise.
(vect_gen_len): Likewise.
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Committed as obvious, fixing one failure for mmix-knuth-mmixware.
gcc/testsuite:
* gcc.dg/pr87485.c: Require scheduling.
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The sole purpose of not providing pseudos and forcing use of
TARGET_ASM_INTEGER is to arrange for assembly output that people can,
instead of using gas, usefullt feed to mmixal (Knuth's assembler). It
uses pseudos with slightly different semantics (BYTE, WYDE, TETRA,
OCTA). Nice when it works, but that only happens for limited
use-cases and debug-information is excluded.
The dwarf2out.c shortcuts, looking up the pseudo-strings and doing the
output on its own, has the result that in absence of such
integer-emitting pseudos, the target TARGET_ASM_INTEGER hook is
called, which by definition outputs a newline, and then the
dwarf2out.c code redundantly adds another. That uglifies output and
breaks the expectations of the dwarf2 parts of the test-suite.
The wart by which an extra newline is emitted is ripe for a cleanup,
and I started out thinking I'd add a default argument for emitting a
newline to the assemble_integer family of functions, but then
reconsidered. I also can't bring myself to use different pseudos
with/without -g so instead I check for options for the more detailed
dumps, as used by the test-suite to get those DW_* strings in detailed
assembly output.
This eliminates all FAILs in the dwarf2-specific parts of the gcc
test-suite for mmix-knuth-mmixware, with no regressions. Committed.
gcc:
* config/mmix/mmix.c (mmix_option_override): Reinstate default
integer-emitting targetm.asm_out pseudos when dumping detailed
assembly-code.
(mmix_assemble_integer): Update comment.
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When a user specified a KIND that was a parameter taking the value
of an iso_c_binding KIND, the code used the name of that parameter
to look up the type name. Corrected by always looking it up in
the table of C interop kinds (which was previously done for
non-C-interop types, anyway).
gcc/fortran/ChangeLog:
PR fortran/96220
* dump-parse-tree.c (get_c_type_name): Always use the entries from
c_interop_kinds_table to find the correct C type.
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Add
void __cpuidex (int __cpuid_info[4], int __leaf, int __subleaf);
as well as include guard to <cpuid.h>.
gcc/
PR target/95973
PR target/96238
* config/i386/cpuid.h: Add include guard.
(__cpuidex): New.
gcc/testsuite/
PR target/95973
PR target/96238
* gcc.target/i386/pr95973.c: New test.
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Procedures are marked as implicit_pure if they fulfill the criteria of
pure procedures. In this case, a procedure was not marked as not being
implicit_pure which called another procedure, which had not yet been
marked as not being implicit_impure.
Fixed by iterating over all procedures, setting callers of procedures
which are non-pure and non-implicit_pure as non-implicit_pure and
doing this until no more procedure has been changed.
gcc/fortran/ChangeLog:
2020-07-19 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/96018
* frontend-passes.c (gfc_check_externals): Adjust formatting.
(implicit_pure_call): New function.
(implicit_pure_expr): New function.
(gfc_fix_implicit_pure): New function.
* gfortran.h (gfc_fix_implicit_pure): New prototype.
* parse.c (translate_all_program_units): Call gfc_fix_implicit_pure.
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Another trivial one.
gcc/testsuite:
* gcc.dg/attr-copy-6.c: Require visibility.
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Long-standing FAIL remedied; committed. Maybe better to list
the targets that *do* support arbitrary frame access?
gcc/testsuite:
* gcc.dg/Wno-frame-address.c: Skip for cris and mmix.
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2020-07-18 Jakub Jelinek <jakub@redhat.com>
* c-c++-common/cpp/pragma-eof.c: Use .+3 instead of 6 in
dg-error.
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This patch restore translation for the variable hint. The translation
tag conflicted with the previous declaration of hint as char[] and
broke bootstrap, so the translation tags were removed. The
declaration was changed to char *. This patch restores the translation
tags to the string.
gcc/fortran/ChangeLog
2020-07-18 David Edelsohn <dje.gcc@gmail.com>
* check.c (gfc_invalid_boz): Mark hint for translation using _().
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The "bias" portion of the regex for "original" expects
bias: (integer(kind=<N>) parm.0.data - (integer(kind=<N>)) del_f_p.data
(or cpo_f_p.data)
on 32 bit platforms, the dump file can show (signed int) instead of
(integer(kind=8)... . This patch adjusts the regex to allow any content
containing the word int between the parentheses.
2020-07-18 David Edelsohn <dje.gcc@gmail.com>
gcc/testsuite/ChangeLog
* gfortran.dg/goacc/finalize-1.f: Adjust regex for 32 bits.
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Define ASM_OUTPUT_ALIGNED_DECL_LOCAL for large local common symbol.
gcc/
PR target/95620
* config/i386/x86-64.h (ASM_OUTPUT_ALIGNED_DECL_LOCAL): New.
libgomp/
PR target/95620
* testsuite/libgomp.c/pr95620.c: New test.
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Committed as obvious. Gets rid of a spurious failure for mmix.
gcc/testsuite:
* c-c++-common/cpp/pragma-eof.c: Require fopenmp.
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We do not currently generate hardware conversion instructions when
converting from _Decimal128 to _Decimal32. There is no one instruction
that does the conversion, so we currently call the __dpd_trunctdsd2
lib function to do the conversion for us. However, there is a short
sequence of dfp hardware instructions that will do the conversion
correctly.
2020-07-17 Peter Bergner <bergner@linux.ibm.com>
gcc/
PR target/92488
* config/rs6000/dfp.md (trunctdsd2): New define_insn.
* config/rs6000/rs6000.md (define_attr "isa"): Add p9.
(define_attr "enabled"): Handle p9.
gcc/testsuite/
PR target/92488
* gcc.target/powerpc/convert-fp-128.c (bl, drsp, drdpq): Update counts.
(__dpd_trunctdsd2): Make conditional on !hard_dfp.
(__dpd_extendsddd2, __dpd_extendsdtd2, __dpd_truncddsd2,
__dpd_extendddtd2, __dpd_trunctddd2): Use !hard_dfp.
* gcc.target/powerpc/pr92488.c: New test.
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Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/243317
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The methods of the trivial awaitables are intended to
be constexpr.
libstdc++-v3/ChangeLog:
* include/std/coroutine: Mark the methods of the
trivial awaitables as constexpr.
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"If the placeholder is the decltype(auto) type-specifier, T shall be the
placeholder alone." but we weren't detecting "const decltype(auto)".
I've just expanded the existing diagnostic detecting "decltype(auto) &"
and similar.
gcc/cp/ChangeLog:
PR c++/79815
* decl.c (grokdeclarator): Detect cv-qual decltype(auto).
* pt.c (do_auto_deduction): Likewise.
gcc/testsuite/ChangeLog:
PR c++/79815
* g++.dg/cpp1y/auto-fn59.C: New test.
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2020-07-16 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* function.c (assign_parm_setup_block): Use the macro
TRULY_NOOP_TRUNCATION_MODES_P instead of calling
targetm.truly_noop_truncation directly.
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Since ix86_emit_swsqrtsf shouldn't be called with DF vector modes, rename
VF_AVX512VL_VF1_128_256 to VF1_AVX512ER_128_256 and drop DF vector modes.
gcc/
PR target/96186
PR target/88713
* config/i386/sse.md (VF_AVX512VL_VF1_128_256): Renamed to ...
(VF1_AVX512ER_128_256): This. Drop DF vector modes.
(rsqrt<mode>2): Replace VF_AVX512VL_VF1_128_256 with
VF1_AVX512ER_128_256.
gcc/testsuite/
PR target/96186
PR target/88713
* gcc.target/i386/pr88713-3.c: New test.
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This adds some tests to the GCC testsuite for testing the
-mcpu=native code.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/cpunative/aarch64-cpunative.exp: New test.
* gcc.target/aarch64/cpunative/info_0: New test.
* gcc.target/aarch64/cpunative/info_1: New test.
* gcc.target/aarch64/cpunative/info_10: New test.
* gcc.target/aarch64/cpunative/info_11: New test.
* gcc.target/aarch64/cpunative/info_12: New test.
* gcc.target/aarch64/cpunative/info_13: New test.
* gcc.target/aarch64/cpunative/info_14: New test.
* gcc.target/aarch64/cpunative/info_15: New test.
* gcc.target/aarch64/cpunative/info_2: New test.
* gcc.target/aarch64/cpunative/info_3: New test.
* gcc.target/aarch64/cpunative/info_4: New test.
* gcc.target/aarch64/cpunative/info_5: New test.
* gcc.target/aarch64/cpunative/info_6: New test.
* gcc.target/aarch64/cpunative/info_7: New test.
* gcc.target/aarch64/cpunative/info_8: New test.
* gcc.target/aarch64/cpunative/info_9: New test.
* gcc.target/aarch64/cpunative/native_cpu_0.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_1.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_10.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_11.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_12.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_13.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_14.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_15.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_2.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_3.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_4.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_5.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_6.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_7.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_8.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_9.c: New test.
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This document some of the existing DejaGnu directives to modify
environment variables before test or compiler invocations.
gcc/ChangeLog:
* doc/sourcebuild.texi (dg-set-compiler-env-var,
dg-set-target-env-var): Document.
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This adds verbose output to dg-set-compiler-env-var and dg-set-target-env-var
so you can actually see what they're setting when you add -v -v.
gcc/testsuite/ChangeLog:
* lib/gcc-dg.exp (dg-set-compiler-env-var, dg-set-target-env-var): Add
verbose output.
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This adds an in intentionally undocumented environment variable
GCC_CPUINFO which can be used to test -mcpu=native.
Tests using these are added later on.
gcc/ChangeLog:
* config/arm/driver-arm.c (host_detect_local_cpu): Add GCC_CPUINFO.
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This adds an in intentionally undocumented environment variable
GCC_CPUINFO which can be used to test -mcpu=native.
Tests using this are added later on.
gcc/ChangeLog:
* config/aarch64/driver-aarch64.c (host_detect_local_cpu):
Add GCC_CPUINFO.
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This patch fixes a couple of issues in AArch64's -mcpu=native processing:
The buffer used to read the lines from /proc/cpuinfo is 128 bytes long. While
this was enough in the past with the increase in architecture extensions it is
no longer enough. It results in two bugs:
1) No option string longer than 127 characters is correctly parsed. Features
that are supported are silently ignored.
2) It incorrectly enables features that are not present on the machine:
a) It checks for substring matching instead of full word matching. This makes
it incorrectly detect sb support when ssbs is provided instead.
b) Due to the truncation at the 127 char border it also incorrectly enables
features due to the full feature being cut off and the part that is left
accidentally enables something else.
This breaks -mcpu=native detection on some of our newer system.
The patch fixes these issues by reading full lines up to the \n in a string.
This gives us the full feature line. Secondly it creates a set from this string
to:
1) Reduce matching complexity from O(n*m) to O(n*logm).
2) Perform whole word matching instead of substring matching.
To make this code somewhat cleaner I also changed from using char* to using
std::string and std::set.
Note that I have intentionally avoided the use of ifstream and stringstream
to make it easier to backport. I have also not change the substring matching
for the initial line classification as I cannot find a documented cpuinfo format
which leads me to believe there may be kernels out there that require this which
may be why the original code does this.
I also do not want this to break if the kernel adds a new line that is long and
indents the file by two tabs to keep everything aligned. In short I think an
imprecise match is the right thing here.
Test for this is added as the last thing in this series as it requires some
changes to be made to be able to test this.
gcc/ChangeLog:
* config/aarch64/driver-aarch64.c (INCLUDE_SET): New.
(parse_field): Use std::string.
(split_words, readline, find_field): New.
(host_detect_local_cpu): Fix truncation issues.
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Allow building on systems with elf.h that includes AMDGPU definitions,
partially or completely.
gcc/ChangeLog:
* config/gcn/mkoffload.c (EM_AMDGPU): Undefine before defining.
(ELFOSABI_AMDGPU_HSA): Likewise.
(ELFABIVERSION_AMDGPU_HSA): Likewise.
(EF_AMDGPU_MACH_AMDGCN_GFX803): Likewise.
(EF_AMDGPU_MACH_AMDGCN_GFX900): Likewise.
(EF_AMDGPU_MACH_AMDGCN_GFX906): Likewise.
(reserved): Delete.
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(PR 93720)
The following patch enables vector permutations optimization by trying
to use ins instruction instead of slow and generic tbl.
example:
vector float f0(vector float a, vector float b)
{
return __builtin_shuffle (a, a, (vector int){3, 1, 2, 3});
}
was compiled into:
...
adrp x0, .LC0
ldr q1, [x0, #:lo12:.LC0]
tbl v0.16b, {v0.16b}, v1.16b
...
and after patch:
...
ins v0.s[0], v0.s[3]
...
bootstrapped and tested on aarch64-linux-gnu with no regressions
gcc/ChangeLog:
2020-07-17 Andrew Pinski <apinksi@marvell.com>
PR target/93720
* config/aarch64/aarch64.c (aarch64_evpc_ins): New function.
(aarch64_expand_vec_perm_const_1): Call it.
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_copy_lane): Make
public, and add a "@" prefix.
gcc/testsuite/ChangeLog:
2020-07-17 Andrew Pinski <apinksi@marvell.com>
PR target/93720
* gcc.target/aarch64/vins-1.c: New test.
* gcc.target/aarch64/vins-2.c: New test.
* gcc.target/aarch64/vins-3.c: New test.
Co-Authored-By: Dmitrij Pochepko <dmitrij.pochepko@bell-sw.com>
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The following patch enables vector permutations optimization by using
another vector element size when applicable. It allows usage of simpler
instructions in applicable cases.
example:
vector float f(vector float a, vector float b)
{
return __builtin_shuffle (a, b, (vector int){0, 1, 4,5});
}
was compiled into:
...
adrp x0, .LC0
ldr q2, [x0, #:lo12:.LC0]
tbl v0.16b, {v0.16b - v1.16b}, v2.16b
...
and after patch:
...
zip1 v0.2d, v0.2d, v1.2d
...
bootstrapped and tested on aarch64-linux-gnu with no regressions
gcc/ChangeLog:
2020-07-17 Andrew Pinski <apinksi@marvell.com>
PR target/82199
* config/aarch64/aarch64.c (aarch64_evpc_reencode): New function.
(aarch64_expand_vec_perm_const_1): Call it.
gcc/testsuite/ChangeLog:
2020-07-17 Andrew Pinski <apinksi@marvell.com>
PR target/82199
* gcc.target/aarch64/vdup_n_3.c: New test.
* gcc.target/aarch64/vzip_1.c: New test.
* gcc.target/aarch64/vzip_2.c: New test.
* gcc.target/aarch64/vzip_3.c: New test.
* gcc.target/aarch64/vzip_4.c: New test.
Co-Authored-By: Dmitrij Pochepko <dmitrij.pochepko@bell-sw.com>
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2020-07-17 Zhiheng Xie <xiezhiheng@huawei.com>
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
Add new field flags.
(VAR1): Add new field FLAG in macro.
(VAR2): Likewise.
(VAR3): Likewise.
(VAR4): Likewise.
(VAR5): Likewise.
(VAR6): Likewise.
(VAR7): Likewise.
(VAR8): Likewise.
(VAR9): Likewise.
(VAR10): Likewise.
(VAR11): Likewise.
(VAR12): Likewise.
(VAR13): Likewise.
(VAR14): Likewise.
(VAR15): Likewise.
(VAR16): Likewise.
(aarch64_general_fold_builtin): Likewise.
(aarch64_general_gimple_fold_builtin): Likewise.
* config/aarch64/aarch64-simd-builtins.def: Add default flag for
each built-in function.
* config/aarch64/geniterators.sh: Add new field in BUILTIN macro.
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contrib/ChangeLog:
* gcc-changelog/git_update_version.py: Fix typo.
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In s390_expand_insv the movstrict patterns are always generated with a
CC clobber although only movstricthi actually needs one. The patch
invokes the expanders instead of constructing the pattern by hand.
Bootstrapped and regression tested on s390x.
gcc/ChangeLog:
PR target/96127
* config/s390/s390.c (s390_expand_insv): Invoke the movstrict
expanders to generate the pattern.
* config/s390/s390.md ("*movstricthi", "*movstrictqi"): Remove the
'*' to have callable expanders.
gcc/testsuite/ChangeLog:
PR target/96127
* gcc.target/s390/pr96127.c: New test.
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In my testing with cost tweaking for vector with length, I found
two cases below didn't get the expected output. Since the expected
instructions reply on the vectorization occurrence, we don't expect
vectorization gets disabled by cost model.
To make it not fragile, the fix is to force it without vect cost model.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/conv-vectorize-1.c: Add option
-fno-vect-cost-model.
* gcc.target/powerpc/conv-vectorize-2.c: Likewise.
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