| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
We're currently running into:
...
FAIL: libgomp.oacc-fortran/declare-5.f90 -DACC_DEVICE_TYPE_nvidia=1 \
-DACC_MEM_SHARED=0 -foffload=nvptx-none -O0 execution test
FAIL: libgomp.oacc-fortran/declare-5.f90 -DACC_DEVICE_TYPE_nvidia=1 \
-DACC_MEM_SHARED=0 -foffload=nvptx-none -O1 execution test
FAIL: libgomp.oacc-fortran/declare-5.f90 -DACC_DEVICE_TYPE_nvidia=1 \
-DACC_MEM_SHARED=0 -foffload=nvptx-none -O2 execution test
FAIL: libgomp.oacc-fortran/declare-5.f90 -DACC_DEVICE_TYPE_nvidia=1 \
-DACC_MEM_SHARED=0 -foffload=nvptx-none -O3 -fomit-frame-pointer \
-funroll-loops -fpeel-loops -ftracer -finline-functions execution test
FAIL: libgomp.oacc-fortran/declare-5.f90 -DACC_DEVICE_TYPE_nvidia=1 \
-DACC_MEM_SHARED=0 -foffload=nvptx-none -O3 -g execution test
FAIL: libgomp.oacc-fortran/declare-5.f90 -DACC_DEVICE_TYPE_nvidia=1 \
-DACC_MEM_SHARED=0 -foffload=nvptx-none -Os execution test
...
A PR was filed for this: PR92790 - "[OpenACC] declare device_resident -
Fortran common blocks not handled / libgomp.oacc-fortran/declare-5.f90 fails"
Xfail the fails.
Tested on x86_64-linux with nvptx accelerator.
libgomp/ChangeLog:
2020-10-06 Tom de Vries <tdevries@suse.de>
* testsuite/libgomp.oacc-fortran/declare-5.f90: Add xfail for PR92790.
|
|
This inlines most members of std::exception_ptr so that all operations
on a null exception_ptr can be optimized away. This benefits code like
std::future and coroutines where an exception_ptr object is present to
cope with exceptional cases, but is usually not used and remains null.
Since those functions were previously non-inline we have to continue to
export them from the library, for objects that were compiled against the
old headers and expect to find definitions in the library.
In order to inline the copy constructor and destructor we need to export
the _M_addref() and _M_release() members that increment/decrement the
reference count when copying/destroying a non-null exception_ptr. The
copy ctor and dtor check for null and don't call _M_addref and
_M_release unless they need to. The checks for null pointers in
_M_addref and _M_release are still needed because old code might call
them without checking for null first. But we can use __builtin_expect to
predict that they are usually called for the non-null case.
libstdc++-v3/ChangeLog:
PR libstdc++/90295
* config/abi/pre/gnu.ver (CXXABI_1.3.13): New symbol version.
(exception_ptr::_M_addref(), exception_ptr::_M_release()):
Export symbols.
* libsupc++/eh_ptr.cc (exception_ptr::exception_ptr()):
Remove out-of-line definition.
(exception_ptr::exception_ptr(const exception_ptr&)):
Likewise.
(exception_ptr::~exception_ptr()): Likewise.
(exception_ptr::operator=(const exception_ptr&)):
Likewise.
(exception_ptr::swap(exception_ptr&)): Likewise.
(exception_ptr::_M_addref()): Add branch prediction.
* libsupc++/exception_ptr.h (exception_ptr::operator bool):
Add noexcept.
[!_GLIBCXX_EH_PTR_COMPAT] (operator==, operator!=): Define
inline as hidden friends. Remove declarations at namespace
scope.
(exception_ptr::exception_ptr()): Define inline.
(exception_ptr::exception_ptr(const exception_ptr&)):
Likewise.
(exception_ptr::~exception_ptr()): Likewise.
(exception_ptr::operator=(const exception_ptr&)):
Likewise.
(exception_ptr::swap(exception_ptr&)): Likewise.
* testsuite/util/testsuite_abi.cc: Add CXXABI_1.3.13.
* testsuite/18_support/exception_ptr/90295.cc: New test.
|
|
This patch enables SIMD modes for MVE auto-vectorization.
In this patch, the integer and float MVE SIMD modes are returned by
arm_preferred_simd_mode (TARGET_VECTORIZE_PREFERRED_SIMD_MODE hook) when
MVE or MVE_FLOAT is enabled. Then the expanders for auto-vectorization
can be used for generating MVE SIMD code.
This patch also fixes bugs in MVE vreiterpretq_*.c tests which are
revealed by the enabled MVE SIMD modes.
The tests are for checking the MVE reinterpret intrinsics.
There are two functions in each of the tests. The two functions contain
the pattern of identical code so that they are folded in icf pass.
Because of icf, the instruction count only checks one function which is
8. However when the SIMD modes are enabled, the estimation of the code
size becomes smaller so that inlining is applied after icf, then the
instruction count becomes 16 which causes failure of the tests.
Because the icf is not the expected pattern to be tested but causes
above issues, -fno-ipa-icf is applied to the tests to avoid unstable
instruction count.
gcc/ChangeLog:
2020-10-05 Dennis Zhang <dennis.zhang@arm.com>
* config/arm/arm.c (arm_preferred_simd_mode): Enable MVE SIMD modes.
gcc/testsuite/ChangeLog:
2020-10-05 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c: Use additional
option -fno-ipa-icf and change the instruction count from 8 to 16.
* gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c: Likewise.
|
|
Consider test-case test.c, with VLA A:
...
int main (void) {
int N = 1000;
int A[N];
#pragma acc declare copy(A)
return 0;
}
...
compiled using:
...
$ gcc test.c -fopenacc -S -fdump-tree-all
...
At original, we have:
...
#pragma acc declare map(tofrom:A);
...
but at gimple, we have a map (to:A.1), but not a map (from:A.1):
...
int[0:D.2074] * A.1;
{
int A[0:D.2074] [value-expr: *A.1];
saved_stack.2 = __builtin_stack_save ();
try
{
A.1 = __builtin_alloca_with_align (D.2078, 32);
#pragma omp target oacc_declare map(to:(*A.1) [len: D.2076])
}
finally
{
__builtin_stack_restore (saved_stack.2);
}
}
...
This is caused by the following incompatibility. When storing the desired
from clause in oacc_declare_returns, we use 'A.1' as the key:
...
10898 oacc_declare_returns->put (decl, c);
(gdb) call debug_generic_expr (decl)
A.1
(gdb) call debug_generic_expr (c)
map(from:(*A.1))
...
but when looking it up, we use 'A' as the key:
...
(gdb)
1471 tree *c = oacc_declare_returns->get (t);
(gdb) call debug_generic_expr (t)
A
...
Fix this by extracing the 'A.1' lookup key from 'A' using the decl-expr.
In addition, unshare the looked up value, to fix avoid running into
an "incorrect sharing of tree nodes" error.
Using these two fixes, we get our desired:
...
finally
{
+ #pragma omp target oacc_declare map(from:(*A.1))
__builtin_stack_restore (saved_stack.2);
}
...
Build on x86_64-linux with nvptx accelerator, tested libgomp.
gcc/ChangeLog:
2020-10-06 Tom de Vries <tdevries@suse.de>
PR middle-end/90861
* gimplify.c (gimplify_bind_expr): Handle lookup in
oacc_declare_returns using key with decl-expr.
libgomp/ChangeLog:
2020-10-06 Tom de Vries <tdevries@suse.de>
PR middle-end/90861
* testsuite/libgomp.oacc-c-c++-common/declare-vla.c: Remove xfail.
|
|
readelf -S prints:
There are 81999 section headers, starting at offset 0x1f488060:
Section Headers:
[Nr] Name Type Address Off Size ES Flg Lk Inf Al
[ 0] NULL 0000000000000000 000000 01404f 00 81998 0 0
[ 1] .group GROUP 0000000000000000 000040 000008 04 81995 105027 4
...
[81995] .symtab SYMTAB 0000000000000000 d5d9298 2db310 18 81997 105026 8
[81996] .symtab_shndx SYMTAB SECTION INDICES 0000000000000000 d8b45a8 079dd8 04 81995 0 4
[81997] .strtab STRTAB 0000000000000000 d92e380 80460c 00 0 0 1
...
Looking at the documentation:
Table 7–15 ELF sh_link and sh_info Interpretation
sh_type - sh_link
SHT_SYMTAB - The section header index of the associated string table.
SHT_SYMTAB_SHNDX - The section header index of the associated symbol table.
As seen, sh_link of a SHT_SYMTAB always points to a .strtab and readelf
confirms that.
So we need to use reverse mapping taken from
[81996] .symtab_shndx SYMTAB SECTION INDICES 0000000000000000 d8b45a8 079dd8 04 81995 0 4
where sh_link points to 81995.
libiberty/ChangeLog:
PR lto/97290
* simple-object-elf.c (simple_object_elf_copy_lto_debug_sections):
Use sh_link of a .symtab_shndx section.
|
|
consistency.
To maintain consistency with other Arm Architectures backend, iterators and iterator attributes are moved
from mve.md file to iterators.md. Also move enumerators for MVE unspecs from mve.md file to unspecs.md file.
gcc/ChangeLog:
2020-10-06 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/iterators.md (MVE_types): Move mode iterator from mve.md to
iterators.md.
(MVE_VLD_ST): Likewise.
(MVE_0): Likewise.
(MVE_1): Likewise.
(MVE_3): Likewise.
(MVE_2): Likewise.
(MVE_5): Likewise.
(MVE_6): Likewise.
(MVE_CNVT): Move mode attribute iterator from mve.md to iterators.md.
(MVE_LANES): Likewise.
(MVE_constraint): Likewise.
(MVE_constraint1): Likewise.
(MVE_constraint2): Likewise.
(MVE_constraint3): Likewise.
(MVE_pred): Likewise.
(MVE_pred1): Likewise.
(MVE_pred2): Likewise.
(MVE_pred3): Likewise.
(MVE_B_ELEM): Likewise.
(MVE_H_ELEM): Likewise.
(V_sz_elem1): Likewise.
(V_extr_elem): Likewise.
(earlyclobber_32): Likewise.
(supf): Move int attribute from mve.md to iterators.md.
(mode1): Likewise.
(VCVTQ_TO_F): Move int iterator from mve.md to iterators.md.
(VMVNQ_N): Likewise.
(VREV64Q): Likewise.
(VCVTQ_FROM_F): Likewise.
(VREV16Q): Likewise.
(VCVTAQ): Likewise.
(VMVNQ): Likewise.
(VDUPQ_N): Likewise.
(VCLZQ): Likewise.
(VADDVQ): Likewise.
(VREV32Q): Likewise.
(VMOVLBQ): Likewise.
(VMOVLTQ): Likewise.
(VCVTPQ): Likewise.
(VCVTNQ): Likewise.
(VCVTMQ): Likewise.
(VADDLVQ): Likewise.
(VCTPQ): Likewise.
(VCTPQ_M): Likewise.
(VCVTQ_N_TO_F): Likewise.
(VCREATEQ): Likewise.
(VSHRQ_N): Likewise.
(VCVTQ_N_FROM_F): Likewise.
(VADDLVQ_P): Likewise.
(VCMPNEQ): Likewise.
(VSHLQ): Likewise.
(VABDQ): Likewise.
(VADDQ_N): Likewise.
(VADDVAQ): Likewise.
(VADDVQ_P): Likewise.
(VANDQ): Likewise.
(VBICQ): Likewise.
(VBRSRQ_N): Likewise.
(VCADDQ_ROT270): Likewise.
(VCADDQ_ROT90): Likewise.
(VCMPEQQ): Likewise.
(VCMPEQQ_N): Likewise.
(VCMPNEQ_N): Likewise.
(VEORQ): Likewise.
(VHADDQ): Likewise.
(VHADDQ_N): Likewise.
(VHSUBQ): Likewise.
(VHSUBQ_N): Likewise.
(VMAXQ): Likewise.
(VMAXVQ): Likewise.
(VMINQ): Likewise.
(VMINVQ): Likewise.
(VMLADAVQ): Likewise.
(VMULHQ): Likewise.
(VMULLBQ_INT): Likewise.
(VMULLTQ_INT): Likewise.
(VMULQ): Likewise.
(VMULQ_N): Likewise.
(VORNQ): Likewise.
(VORRQ): Likewise.
(VQADDQ): Likewise.
(VQADDQ_N): Likewise.
(VQRSHLQ): Likewise.
(VQRSHLQ_N): Likewise.
(VQSHLQ): Likewise.
(VQSHLQ_N): Likewise.
(VQSHLQ_R): Likewise.
(VQSUBQ): Likewise.
(VQSUBQ_N): Likewise.
(VRHADDQ): Likewise.
(VRMULHQ): Likewise.
(VRSHLQ): Likewise.
(VRSHLQ_N): Likewise.
(VRSHRQ_N): Likewise.
(VSHLQ_N): Likewise.
(VSHLQ_R): Likewise.
(VSUBQ): Likewise.
(VSUBQ_N): Likewise.
(VADDLVAQ): Likewise.
(VBICQ_N): Likewise.
(VMLALDAVQ): Likewise.
(VMLALDAVXQ): Likewise.
(VMOVNBQ): Likewise.
(VMOVNTQ): Likewise.
(VORRQ_N): Likewise.
(VQMOVNBQ): Likewise.
(VQMOVNTQ): Likewise.
(VSHLLBQ_N): Likewise.
(VSHLLTQ_N): Likewise.
(VRMLALDAVHQ): Likewise.
(VBICQ_M_N): Likewise.
(VCVTAQ_M): Likewise.
(VCVTQ_M_TO_F): Likewise.
(VQRSHRNBQ_N): Likewise.
(VABAVQ): Likewise.
(VSHLCQ): Likewise.
(VRMLALDAVHAQ): Likewise.
(VADDVAQ_P): Likewise.
(VCLZQ_M): Likewise.
(VCMPEQQ_M_N): Likewise.
(VCMPEQQ_M): Likewise.
(VCMPNEQ_M_N): Likewise.
(VCMPNEQ_M): Likewise.
(VDUPQ_M_N): Likewise.
(VMAXVQ_P): Likewise.
(VMINVQ_P): Likewise.
(VMLADAVAQ): Likewise.
(VMLADAVQ_P): Likewise.
(VMLAQ_N): Likewise.
(VMLASQ_N): Likewise.
(VMVNQ_M): Likewise.
(VPSELQ): Likewise.
(VQDMLAHQ_N): Likewise.
(VQRDMLAHQ_N): Likewise.
(VQRDMLASHQ_N): Likewise.
(VQRSHLQ_M_N): Likewise.
(VQSHLQ_M_R): Likewise.
(VREV64Q_M): Likewise.
(VRSHLQ_M_N): Likewise.
(VSHLQ_M_R): Likewise.
(VSLIQ_N): Likewise.
(VSRIQ_N): Likewise.
(VMLALDAVQ_P): Likewise.
(VQMOVNBQ_M): Likewise.
(VMOVLTQ_M): Likewise.
(VMOVNBQ_M): Likewise.
(VRSHRNTQ_N): Likewise.
(VORRQ_M_N): Likewise.
(VREV32Q_M): Likewise.
(VREV16Q_M): Likewise.
(VQRSHRNTQ_N): Likewise.
(VMOVNTQ_M): Likewise.
(VMOVLBQ_M): Likewise.
(VMLALDAVAQ): Likewise.
(VQSHRNBQ_N): Likewise.
(VSHRNBQ_N): Likewise.
(VRSHRNBQ_N): Likewise.
(VMLALDAVXQ_P): Likewise.
(VQMOVNTQ_M): Likewise.
(VMVNQ_M_N): Likewise.
(VQSHRNTQ_N): Likewise.
(VMLALDAVAXQ): Likewise.
(VSHRNTQ_N): Likewise.
(VCVTMQ_M): Likewise.
(VCVTNQ_M): Likewise.
(VCVTPQ_M): Likewise.
(VCVTQ_M_N_FROM_F): Likewise.
(VCVTQ_M_FROM_F): Likewise.
(VRMLALDAVHQ_P): Likewise.
(VADDLVAQ_P): Likewise.
(VABAVQ_P): Likewise.
(VSHLQ_M): Likewise.
(VSRIQ_M_N): Likewise.
(VSUBQ_M): Likewise.
(VCVTQ_M_N_TO_F): Likewise.
(VHSUBQ_M): Likewise.
(VSLIQ_M_N): Likewise.
(VRSHLQ_M): Likewise.
(VMINQ_M): Likewise.
(VMULLBQ_INT_M): Likewise.
(VMULHQ_M): Likewise.
(VMULQ_M): Likewise.
(VHSUBQ_M_N): Likewise.
(VHADDQ_M_N): Likewise.
(VORRQ_M): Likewise.
(VRMULHQ_M): Likewise.
(VQADDQ_M): Likewise.
(VRSHRQ_M_N): Likewise.
(VQSUBQ_M_N): Likewise.
(VADDQ_M): Likewise.
(VORNQ_M): Likewise.
(VRHADDQ_M): Likewise.
(VQSHLQ_M): Likewise.
(VANDQ_M): Likewise.
(VBICQ_M): Likewise.
(VSHLQ_M_N): Likewise.
(VCADDQ_ROT270_M): Likewise.
(VQRSHLQ_M): Likewise.
(VQADDQ_M_N): Likewise.
(VADDQ_M_N): Likewise.
(VMAXQ_M): Likewise.
(VQSUBQ_M): Likewise.
(VMLASQ_M_N): Likewise.
(VMLADAVAQ_P): Likewise.
(VBRSRQ_M_N): Likewise.
(VMULQ_M_N): Likewise.
(VCADDQ_ROT90_M): Likewise.
(VMULLTQ_INT_M): Likewise.
(VEORQ_M): Likewise.
(VSHRQ_M_N): Likewise.
(VSUBQ_M_N): Likewise.
(VHADDQ_M): Likewise.
(VABDQ_M): Likewise.
(VMLAQ_M_N): Likewise.
(VQSHLQ_M_N): Likewise.
(VMLALDAVAQ_P): Likewise.
(VMLALDAVAXQ_P): Likewise.
(VQRSHRNBQ_M_N): Likewise.
(VQRSHRNTQ_M_N): Likewise.
(VQSHRNBQ_M_N): Likewise.
(VQSHRNTQ_M_N): Likewise.
(VRSHRNBQ_M_N): Likewise.
(VRSHRNTQ_M_N): Likewise.
(VSHLLBQ_M_N): Likewise.
(VSHLLTQ_M_N): Likewise.
(VSHRNBQ_M_N): Likewise.
(VSHRNTQ_M_N): Likewise.
(VSTRWSBQ): Likewise.
(VSTRBSOQ): Likewise.
(VSTRBQ): Likewise.
(VLDRBGOQ): Likewise.
(VLDRBQ): Likewise.
(VLDRWGBQ): Likewise.
(VLD1Q): Likewise.
(VLDRHGOQ): Likewise.
(VLDRHGSOQ): Likewise.
(VLDRHQ): Likewise.
(VLDRWQ): Likewise.
(VLDRDGBQ): Likewise.
(VLDRDGOQ): Likewise.
(VLDRDGSOQ): Likewise.
(VLDRWGOQ): Likewise.
(VLDRWGSOQ): Likewise.
(VST1Q): Likewise.
(VSTRHSOQ): Likewise.
(VSTRHSSOQ): Likewise.
(VSTRHQ): Likewise.
(VSTRWQ): Likewise.
(VSTRDSBQ): Likewise.
(VSTRDSOQ): Likewise.
(VSTRDSSOQ): Likewise.
(VSTRWSOQ): Likewise.
(VSTRWSSOQ): Likewise.
(VSTRWSBWBQ): Likewise.
(VLDRWGBWBQ): Likewise.
(VSTRDSBWBQ): Likewise.
(VLDRDGBWBQ): Likewise.
(VADCIQ): Likewise.
(VADCIQ_M): Likewise.
(VSBCQ): Likewise.
(VSBCQ_M): Likewise.
(VSBCIQ): Likewise.
(VSBCIQ_M): Likewise.
(VADCQ): Likewise.
(VADCQ_M): Likewise.
(UQRSHLLQ): Likewise.
(SQRSHRLQ): Likewise.
(VSHLCQ_M): Likewise.
* config/arm/mve.md (MVE_types): Move mode iterator to iterators.md from mve.md.
(MVE_VLD_ST): Likewise.
(MVE_0): Likewise.
(MVE_1): Likewise.
(MVE_3): Likewise.
(MVE_2): Likewise.
(MVE_5): Likewise.
(MVE_6): Likewise.
(MVE_CNVT): Move mode attribute iterator to iterators.md from mve.md.
(MVE_LANES): Likewise.
(MVE_constraint): Likewise.
(MVE_constraint1): Likewise.
(MVE_constraint2): Likewise.
(MVE_constraint3): Likewise.
(MVE_pred): Likewise.
(MVE_pred1): Likewise.
(MVE_pred2): Likewise.
(MVE_pred3): Likewise.
(MVE_B_ELEM): Likewise.
(MVE_H_ELEM): Likewise.
(V_sz_elem1): Likewise.
(V_extr_elem): Likewise.
(earlyclobber_32): Likewise.
(supf): Move int attribute to iterators.md from mve.md.
(mode1): Likewise.
(VCVTQ_TO_F): Move int iterator to iterators.md from mve.md.
(VMVNQ_N): Likewise.
(VREV64Q): Likewise.
(VCVTQ_FROM_F): Likewise.
(VREV16Q): Likewise.
(VCVTAQ): Likewise.
(VMVNQ): Likewise.
(VDUPQ_N): Likewise.
(VCLZQ): Likewise.
(VADDVQ): Likewise.
(VREV32Q): Likewise.
(VMOVLBQ): Likewise.
(VMOVLTQ): Likewise.
(VCVTPQ): Likewise.
(VCVTNQ): Likewise.
(VCVTMQ): Likewise.
(VADDLVQ): Likewise.
(VCTPQ): Likewise.
(VCTPQ_M): Likewise.
(VCVTQ_N_TO_F): Likewise.
(VCREATEQ): Likewise.
(VSHRQ_N): Likewise.
(VCVTQ_N_FROM_F): Likewise.
(VADDLVQ_P): Likewise.
(VCMPNEQ): Likewise.
(VSHLQ): Likewise.
(VABDQ): Likewise.
(VADDQ_N): Likewise.
(VADDVAQ): Likewise.
(VADDVQ_P): Likewise.
(VANDQ): Likewise.
(VBICQ): Likewise.
(VBRSRQ_N): Likewise.
(VCADDQ_ROT270): Likewise.
(VCADDQ_ROT90): Likewise.
(VCMPEQQ): Likewise.
(VCMPEQQ_N): Likewise.
(VCMPNEQ_N): Likewise.
(VEORQ): Likewise.
(VHADDQ): Likewise.
(VHADDQ_N): Likewise.
(VHSUBQ): Likewise.
(VHSUBQ_N): Likewise.
(VMAXQ): Likewise.
(VMAXVQ): Likewise.
(VMINQ): Likewise.
(VMINVQ): Likewise.
(VMLADAVQ): Likewise.
(VMULHQ): Likewise.
(VMULLBQ_INT): Likewise.
(VMULLTQ_INT): Likewise.
(VMULQ): Likewise.
(VMULQ_N): Likewise.
(VORNQ): Likewise.
(VORRQ): Likewise.
(VQADDQ): Likewise.
(VQADDQ_N): Likewise.
(VQRSHLQ): Likewise.
(VQRSHLQ_N): Likewise.
(VQSHLQ): Likewise.
(VQSHLQ_N): Likewise.
(VQSHLQ_R): Likewise.
(VQSUBQ): Likewise.
(VQSUBQ_N): Likewise.
(VRHADDQ): Likewise.
(VRMULHQ): Likewise.
(VRSHLQ): Likewise.
(VRSHLQ_N): Likewise.
(VRSHRQ_N): Likewise.
(VSHLQ_N): Likewise.
(VSHLQ_R): Likewise.
(VSUBQ): Likewise.
(VSUBQ_N): Likewise.
(VADDLVAQ): Likewise.
(VBICQ_N): Likewise.
(VMLALDAVQ): Likewise.
(VMLALDAVXQ): Likewise.
(VMOVNBQ): Likewise.
(VMOVNTQ): Likewise.
(VORRQ_N): Likewise.
(VQMOVNBQ): Likewise.
(VQMOVNTQ): Likewise.
(VSHLLBQ_N): Likewise.
(VSHLLTQ_N): Likewise.
(VRMLALDAVHQ): Likewise.
(VBICQ_M_N): Likewise.
(VCVTAQ_M): Likewise.
(VCVTQ_M_TO_F): Likewise.
(VQRSHRNBQ_N): Likewise.
(VABAVQ): Likewise.
(VSHLCQ): Likewise.
(VRMLALDAVHAQ): Likewise.
(VADDVAQ_P): Likewise.
(VCLZQ_M): Likewise.
(VCMPEQQ_M_N): Likewise.
(VCMPEQQ_M): Likewise.
(VCMPNEQ_M_N): Likewise.
(VCMPNEQ_M): Likewise.
(VDUPQ_M_N): Likewise.
(VMAXVQ_P): Likewise.
(VMINVQ_P): Likewise.
(VMLADAVAQ): Likewise.
(VMLADAVQ_P): Likewise.
(VMLAQ_N): Likewise.
(VMLASQ_N): Likewise.
(VMVNQ_M): Likewise.
(VPSELQ): Likewise.
(VQDMLAHQ_N): Likewise.
(VQRDMLAHQ_N): Likewise.
(VQRDMLASHQ_N): Likewise.
(VQRSHLQ_M_N): Likewise.
(VQSHLQ_M_R): Likewise.
(VREV64Q_M): Likewise.
(VRSHLQ_M_N): Likewise.
(VSHLQ_M_R): Likewise.
(VSLIQ_N): Likewise.
(VSRIQ_N): Likewise.
(VMLALDAVQ_P): Likewise.
(VQMOVNBQ_M): Likewise.
(VMOVLTQ_M): Likewise.
(VMOVNBQ_M): Likewise.
(VRSHRNTQ_N): Likewise.
(VORRQ_M_N): Likewise.
(VREV32Q_M): Likewise.
(VREV16Q_M): Likewise.
(VQRSHRNTQ_N): Likewise.
(VMOVNTQ_M): Likewise.
(VMOVLBQ_M): Likewise.
(VMLALDAVAQ): Likewise.
(VQSHRNBQ_N): Likewise.
(VSHRNBQ_N): Likewise.
(VRSHRNBQ_N): Likewise.
(VMLALDAVXQ_P): Likewise.
(VQMOVNTQ_M): Likewise.
(VMVNQ_M_N): Likewise.
(VQSHRNTQ_N): Likewise.
(VMLALDAVAXQ): Likewise.
(VSHRNTQ_N): Likewise.
(VCVTMQ_M): Likewise.
(VCVTNQ_M): Likewise.
(VCVTPQ_M): Likewise.
(VCVTQ_M_N_FROM_F): Likewise.
(VCVTQ_M_FROM_F): Likewise.
(VRMLALDAVHQ_P): Likewise.
(VADDLVAQ_P): Likewise.
(VABAVQ_P): Likewise.
(VSHLQ_M): Likewise.
(VSRIQ_M_N): Likewise.
(VSUBQ_M): Likewise.
(VCVTQ_M_N_TO_F): Likewise.
(VHSUBQ_M): Likewise.
(VSLIQ_M_N): Likewise.
(VRSHLQ_M): Likewise.
(VMINQ_M): Likewise.
(VMULLBQ_INT_M): Likewise.
(VMULHQ_M): Likewise.
(VMULQ_M): Likewise.
(VHSUBQ_M_N): Likewise.
(VHADDQ_M_N): Likewise.
(VORRQ_M): Likewise.
(VRMULHQ_M): Likewise.
(VQADDQ_M): Likewise.
(VRSHRQ_M_N): Likewise.
(VQSUBQ_M_N): Likewise.
(VADDQ_M): Likewise.
(VORNQ_M): Likewise.
(VRHADDQ_M): Likewise.
(VQSHLQ_M): Likewise.
(VANDQ_M): Likewise.
(VBICQ_M): Likewise.
(VSHLQ_M_N): Likewise.
(VCADDQ_ROT270_M): Likewise.
(VQRSHLQ_M): Likewise.
(VQADDQ_M_N): Likewise.
(VADDQ_M_N): Likewise.
(VMAXQ_M): Likewise.
(VQSUBQ_M): Likewise.
(VMLASQ_M_N): Likewise.
(VMLADAVAQ_P): Likewise.
(VBRSRQ_M_N): Likewise.
(VMULQ_M_N): Likewise.
(VCADDQ_ROT90_M): Likewise.
(VMULLTQ_INT_M): Likewise.
(VEORQ_M): Likewise.
(VSHRQ_M_N): Likewise.
(VSUBQ_M_N): Likewise.
(VHADDQ_M): Likewise.
(VABDQ_M): Likewise.
(VMLAQ_M_N): Likewise.
(VQSHLQ_M_N): Likewise.
(VMLALDAVAQ_P): Likewise.
(VMLALDAVAXQ_P): Likewise.
(VQRSHRNBQ_M_N): Likewise.
(VQRSHRNTQ_M_N): Likewise.
(VQSHRNBQ_M_N): Likewise.
(VQSHRNTQ_M_N): Likewise.
(VRSHRNBQ_M_N): Likewise.
(VRSHRNTQ_M_N): Likewise.
(VSHLLBQ_M_N): Likewise.
(VSHLLTQ_M_N): Likewise.
(VSHRNBQ_M_N): Likewise.
(VSHRNTQ_M_N): Likewise.
(VSTRWSBQ): Likewise.
(VSTRBSOQ): Likewise.
(VSTRBQ): Likewise.
(VLDRBGOQ): Likewise.
(VLDRBQ): Likewise.
(VLDRWGBQ): Likewise.
(VLD1Q): Likewise.
(VLDRHGOQ): Likewise.
(VLDRHGSOQ): Likewise.
(VLDRHQ): Likewise.
(VLDRWQ): Likewise.
(VLDRDGBQ): Likewise.
(VLDRDGOQ): Likewise.
(VLDRDGSOQ): Likewise.
(VLDRWGOQ): Likewise.
(VLDRWGSOQ): Likewise.
(VST1Q): Likewise.
(VSTRHSOQ): Likewise.
(VSTRHSSOQ): Likewise.
(VSTRHQ): Likewise.
(VSTRWQ): Likewise.
(VSTRDSBQ): Likewise.
(VSTRDSOQ): Likewise.
(VSTRDSSOQ): Likewise.
(VSTRWSOQ): Likewise.
(VSTRWSSOQ): Likewise.
(VSTRWSBWBQ): Likewise.
(VLDRWGBWBQ): Likewise.
(VSTRDSBWBQ): Likewise.
(VLDRDGBWBQ): Likewise.
(VADCIQ): Likewise.
(VADCIQ_M): Likewise.
(VSBCQ): Likewise.
(VSBCQ_M): Likewise.
(VSBCIQ): Likewise.
(VSBCIQ_M): Likewise.
(VADCQ): Likewise.
(VADCQ_M): Likewise.
(UQRSHLLQ): Likewise.
(SQRSHRLQ): Likewise.
(VSHLCQ_M): Likewise.
(define_c_enum "unspec"): Move MVE enumerator to unspecs.md from mve.md.
* config/arm/unspecs.md (define_c_enum "unspec"): Move MVE enumerator from
mve.md to unspecs.md.
|
|
gcc/ChangeLog:
* common.opt: Remove -fdbg-cnt-list from deferred options.
* dbgcnt.c (dbg_cnt_set_limit_by_index): Make a copy
to original_limits.
(dbg_cnt_list_all_counters): Print also current counter value
and print to stderr.
* opts-global.c (handle_common_deferred_options): Do not handle
-fdbg-cnt-list.
* opts.c (common_handle_option): Likewise.
* toplev.c (finalize): Handle it after compilation here.
|
|
gcc/ChangeLog:
* dbgcnt.c (dbg_cnt): Report also upper limit.
|
|
ChangeLog:
PR target/97302
* configure.ac: Only set with_gmp to /usr/local
if not building in tree.
* configure: Regenerate.
|
|
The fix "[omp, ftracer] Don't duplicate blocks in SIMT region" adds iteration
over insns in ignore_bb_p, which makes it more expensive.
Counteract this by piggybacking the computation of can_duplicate_bb_p onto
count_insns, which is called at the start of ftracer.
Bootstrapped and reg-tested on x86_64-linux.
gcc/ChangeLog:
2020-10-05 Tom de Vries <tdevries@suse.de>
* tracer.c (count_insns): Rename to ...
(analyze_bb): ... this.
(cache_can_duplicate_bb_p, cached_can_duplicate_bb_p): New function.
(ignore_bb_p): Use cached_can_duplicate_bb_p.
(tail_duplicate): Call cache_can_duplicate_bb_p.
|
|
Factor out can_duplicate_bb_p out of ignore_bb_p.
Also factor out can_duplicate_insn_p and can_duplicate_bb_no_insn_iter_p to
expose the parts of can_duplicate_bb_p that are per-bb and per-insn.
Bootstrapped and reg-tested on x86_64-linux.
gcc/ChangeLog:
2020-10-05 Tom de Vries <tdevries@suse.de>
* tracer.c (can_duplicate_insn_p, can_duplicate_bb_no_insn_iter_p)
(can_duplicate_bb_p): New function, factored out of ...
(ignore_bb_p): ... here.
|
|
In commit ef275d1f2083f8a1fa1b59a3cd07fd3e8431023e I implemented the
wrong resolution of LWG 3474. This removes the deduction guide and
alters the views::join factory to create the right type explicitly.
libstdc++-v3/ChangeLog:
* include/std/ranges (join_view): Remove deduction guide.
(views::join): Add explicit template argument list to prevent
deducing the wrong type.
* testsuite/std/ranges/adaptors/join.cc: Move test for LWG 3474
here, from ...
* testsuite/std/ranges/adaptors/join_lwg3474.cc: Removed.
|
|
As written in the comment, tree-ssa-math-opts.c wouldn't create a DIVMOD
ifn call for division + modulo by constant for the fear that during
expansion we could generate better code for those cases.
If the divisoris a power of two, that is certainly the case always,
but otherwise expand_divmod can punt in many cases, e.g. if the division
type's precision is above HOST_BITS_PER_WIDE_INT, we don't even call
choose_multiplier, because it works on HOST_WIDE_INTs (true, something
we should fix eventually now that we have wide_ints), or if pre/post shift
is larger than BITS_PER_WORD.
So, the following patch recognizes DIVMOD with constant last argument even
when it is unclear if expand_divmod will be able to optimize it, and then
during DIVMOD expansion if the divisor is constant attempts to expand it as
division + modulo and if they actually don't contain any libcalls or
division/modulo, they are kept as is, otherwise that sequence is thrown away
and divmod optab or libcall is used.
2020-10-06 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/97282
* tree-ssa-math-opts.c (divmod_candidate_p): Don't return false for
constant op2 if it is not a power of two and the type has precision
larger than HOST_BITS_PER_WIDE_INT or BITS_PER_WORD.
* internal-fn.c (contains_call_div_mod): New function.
(expand_DIVMOD): If last argument is a constant, try to expand it as
TRUNC_DIV_EXPR followed by TRUNC_MOD_EXPR, but if the sequence
contains any calls or {,U}{DIV,MOD} rtxes, throw it away and use
divmod optab or divmod libfunc.
* gcc.target/i386/pr97282.c: New test.
|
|
gcc/ChangeLog:
* value-range.h (irange_allocator::allocate): Increase
newir storage by one.
|
|
This ICEs because node->alias_target is (not yet) a FUNCTION_DECL, but
IDENTIFIER_NODE.
I guess we should retry the discovery before LTO streaming out, the reason
to do it this early is that it can affect the gimplification and omp lowering.
2020-10-06 Jakub Jelinek <jakub@redhat.com>
PR middle-end/97289
* omp-offload.c (omp_discover_declare_target_tgt_fn_r): Only follow
node->alias_target if it is a FUNCTION_DECL.
* c-c++-common/gomp/pr97289.c: New test.
|
|
This patch rearranges feature bits for MVE and FP to implement the
following flags for -mcpu=cortex-m55.
- +nomve: equivalent to armv8.1-m.main+fp.dp+dsp.
- +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve).
- +nofp: equivalent to armv8.1-m.main+mve (+dsp is implied by +mve).
- +nodsp: equivalent to armv8.1-m.main+fp.dp.
Combinations of the above:
- +nomve+nofp: equivalent to armv8.1-m.main+dsp.
- +nodsp+nofp: equivalent to armv8.1-m.main.
Due to MVE and FP sharing vfp_base, some new syntax was required in the CPU
description to implement the concept of 'implied bits'. These are non-named
features added to the ISA late, depending on whether one or more features which
depend on them are present. This means vfp_base can be present when only one of
MVE and FP is removed, but absent when both are removed.
gcc/ChangeLog:
2020-07-31 Joe Ramsay <joe.ramsay@arm.com>
* config/arm/arm-cpus.in:
(ALL_FPU_INTERNAL): Remove vfp_base.
(VFPv2): Remove vfp_base.
(MVE): Remove vfp_base.
(vfp_base): Redefine as implied bit dependent on MVE or FP
(cortex-m55): Add flags to disable MVE, MVE FP, FP and DSP extensions.
* config/arm/arm.c (arm_configure_build_target): Add implied bits to ISA.
* config/arm/parsecpu.awk:
(gen_isa): Print implied bits and their dependencies to ISA header.
(gen_data): Add parsing for implied feature bits.
gcc/testsuite/ChangeLog:
* gcc.target/arm/cortex-m55-nodsp-flag-hard.c: New test.
* gcc.target/arm/cortex-m55-nodsp-flag-softfp.c: New test.
* gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c: New test.
* gcc.target/arm/cortex-m55-nofp-flag-hard.c: New test.
* gcc.target/arm/cortex-m55-nofp-flag-softfp.c: New test.
* gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c: New test.
* gcc.target/arm/cortex-m55-nomve-flag-hard.c: New test.
* gcc.target/arm/cortex-m55-nomve-flag-softfp.c: New test.
* gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c: New test.
* gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c: New test.
* gcc.target/arm/multilib.exp: Add tests for -mcpu=cortex-m55.
|
|
gcc/ChangeLog:
* doc/invoke.texi: Add z15/arch13 to the list of documented
-march/-mtune options.
|
|
The implementation of Stream_from_file mishandled several cases:
* It reversed the check for whether bytes were already available in
the peek buffer.
* It considered positive return values from lseek to be an error, when
only a -1 return value indicates an error.
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/259437
|
|
|
|
This avoids unnecessary instantiations of std::numeric_limits or
inclusion of <limits> when a more lightweight alternative would work.
Some uses can be replaced with __gnu_cxx::__int_traits and some can just
use size_t(-1) directly where SIZE_MAX is needed.
libstdc++-v3/ChangeLog:
* include/bits/regex.h: Use __int_traits<int> instead of
std::numeric_limits<int>.
* include/bits/uniform_int_dist.h: Use __int_traits<T>::__max
instead of std::numeric_limits<T>::max().
* include/bits/hashtable_policy.h: Use size_t(-1) instead of
std::numeric_limits<size_t>::max().
* include/std/regex: Include <ext/numeric_traits.h>.
* include/std/string_view: Use typedef for __int_traits<int>.
* src/c++11/hashtable_c++0x.cc: Use size_t(-1) instead of
std::numeric_limits<size_t>::max().
* testsuite/std/ranges/iota/96042.cc: Include <limits>.
* testsuite/std/ranges/iota/difference_type.cc: Likewise.
* testsuite/std/ranges/subrange/96042.cc: Likewise.
|
|
gcc/cp/ChangeLog:
* cp-tree.h (NON_UNION_CLASS_TYPE_P): Fix typo in a comment.
|
|
When adding new features to <numeric> I included the required headers
adjacent to the new code. This cleans it up by moving all the includes
to the start of the file.
libstdc++-v3/ChangeLog:
* include/std/numeric: Move all #include directives to the top
of the header.
* testsuite/26_numerics/gcd/gcd_neg.cc: Adjust dg-error line
numbers.
* testsuite/26_numerics/lcm/lcm_neg.cc: Likewise.
|
|
These are cleanups so that multi-range union/intersect doesn't
have to deal with legacy code. Instead, these should be done in
legacy mode.
gcc/ChangeLog:
* value-range.cc (irange::legacy_intersect): Only handle
legacy ranges.
(irange::legacy_union): Same.
(irange::union_): When unioning legacy with non-legacy,
first convert to legacy and do everything in legacy mode.
(irange::intersect): Same, but for intersect.
* range-op.cc (range_tests): Adjust for above changes.
|
|
This patch imports three fixes from the ranger branch:
1. Fold division by zero into varying instead of undefined.
This provides compatibility with existing stuff on trunk.
2. Solver changes for lshift.
This should not affect anything on trunk, as it only involves
the GORI solver which is yet to be contributed.
3. Preserve existing behavior for ABS([-MIN,-MIN]).
This is actually unrepresentable, but trunk has traditionally
treated this as [-MIN,-MIN] so this patch just syncs range-ops
with the rest of trunk.
gcc/ChangeLog:
* range-op.cc (operator_div::wi_fold): Return varying for
division by zero.
(class operator_rshift): Move class up.
(operator_abs::wi_fold): Return [-MIN,-MIN] for ABS([-MIN,-MIN]).
(operator_tests): Adjust tests.
|
|
> See my comment above for Martins attempts to improve things. I don't
> really want to try decide what to do with those late diagnostic IL
> printing but my commit was blamed for showing target-mem-ref unsupported.
>
> I don't have much time to spend to think what to best print and what not,
> but yes, printing only the MEM_REF part is certainly imprecise.
Here is an updated version of the patch that prints TARGET_MEM_REF the way
it should be printed - as C representation of what it actually means.
Of course it would be better to have the original expressions, but with the
late diagnostics we no longer have them.
2020-10-05 Richard Biener <rguenther@suse.de>
Jakub Jelinek <jakub@redhat.com>
PR c++/97197
gcc/cp/
* error.c (dump_expr): Handle TARGET_MEM_REF.
gcc/c-family/
* c-pretty-print.c: Include langhooks.h.
(c_pretty_printer::postfix_expression): Handle TARGET_MEM_REF as
expression.
(c_pretty_printer::expression): Handle TARGET_MEM_REF as
unary_expression.
(c_pretty_printer::unary_expression): Handle TARGET_MEM_REF.
|
|
std::allocator and std::pmr::polymorphic_allocator should throw
std::bad_array_new_length from their allocate member functions if the
number of bytes required cannot be represented in std::size_t.
libstdc++-v3/ChangeLog:
* config/abi/pre/gnu.ver: Add new symbol.
* include/bits/functexcept.h (__throw_bad_array_new_length):
Declare new function.
* include/ext/malloc_allocator.h (malloc_allocator::allocate):
Throw bad_array_new_length for impossible sizes (LWG 3190).
* include/ext/new_allocator.h (new_allocator::allocate):
Likewise.
* include/std/memory_resource (polymorphic_allocator::allocate)
(polymorphic_allocator::allocate_object): Use new function,
__throw_bad_array_new_length.
* src/c++11/functexcept.cc (__throw_bad_array_new_length):
Define.
* testsuite/20_util/allocator/lwg3190.cc: New test.
|
|
As IFN_GOMP_SIMT_XCHG_* are part of the group marked by
IFN_GOMP_SIMT_ENTER_ALLOC/IFN_GOMP_SIMT_EXIT, handle them conservatively
in ignore_bb_p.
Build on x86_64-linux with nvptx accelerator, tested with libgomp.
gcc/ChangeLog:
2020-10-05 Tom de Vries <tdevries@suse.de>
* tracer.c (ignore_bb_p): Ignore GOMP_SIMT_XCHG_*.
|
|
My change to namespace-scope spell corrections ignored the issue that
different targets might have different builtins, and therefore perturb
iteration order. This fixes it by using an intermediate array of
identifier, which we sort before considering.
gcc/cp/
* name-lookup.c (maybe_add_fuzzy_decl): New.
(maybe_add_fuzzy_binding): New.
(consider_binding_level): Use intermediate sortable vector for
namespace bindings.
gcc/testsuite/
* c-c++-common/spellcheck-reserved.c: Restore diagnostic.
|
|
This patch adds vendor and part numbers which were missing from the
initial entry for Neoverse V1 in AArch32 GCC.
gcc/ChangeLog:
* config/arm/arm-cpus.in (neoverse-v1): Add missing vendor and
part numbers.
|
|
In commit ab3f4b27abe "[omp, ftracer] Don't duplicate blocks in SIMT region" I
added a comment in ignore_bb_p suggesting a reordering of SIMT_VOTE_ANY and
SIMT_EXIT, which is not possible since VOTE_ANY may have data dependencies to
storage that is deallocated by SIMT_EXIT.
I've now opened a PR (PR97291) to describe the problem the reordering was
intended to fix.
Remove the incorrect suggestion.
gcc/ChangeLog:
2020-10-05 Tom de Vries <tdevries@suse.de>
* tracer.c (ignore_bb_p): Remove incorrect suggestion.
|
|
As Jonathan Wakely pointed out[1], my change in commit
f9ddb696a289cc48d24d3d23c0b324cb88de9573 should have been rounding to
the target clock duration type rather than the input clock duration type
in __atomic_futex_unsigned::_M_load_when_equal_until just as (e.g.)
condition_variable does.
As well as fixing this, let's create a rather contrived test that fails
with the previous code, but unfortunately only when run on a machine
with an uptime of over 208.5 days, and even then not always.
[1] https://gcc.gnu.org/pipermail/libstdc++/2020-September/051004.html
libstdc++-v3/ChangeLog:
PR libstdc++/91486
* include/bits/atomic_futex.h:
(__atomic_futex_unsigned::_M_load_when_equal_until): Use target
clock duration type when rounding.
* testsuite/30_threads/async/async.cc (test_pr91486_wait_for):
Rename from test_pr91486.
(float_steady_clock): New class for test.
(test_pr91486_wait_until): New test.
|
|
Commit 53ad6b1979f4bd7121e977c4a44151b14d8a0147 split the implementation
of std::chrono::__detail::ceil so that when compiling for C++17 and
later std::chrono::ceil is used but when compiling for earlier versions
a separate implementation is used to comply with C++11's limited
constexpr rules. Let's run the equivalent of the existing
std::chrono::ceil test cases on std::chrono::__detail::ceil too to make
sure that it doesn't get broken.
libstdc++-v3/ChangeLog:
* testsuite/20_util/duration_cast/rounding_c++11.cc: Copy
rounding.cc and alter to support compilation for C++11 and to
test std::chrono::__detail::ceil.
|
|
We missed these out of the git commit messages.
|
|
> This breaks ia64:
>
> In file included from ./tm.h:23,
> from ../../gcc/gencheck.c:23:
> ./options.h:7816:40: error: ISO C++ forbids zero-size array 'explicit_mask' [-Werror=pedantic]
> 7816 | unsigned HOST_WIDE_INT explicit_mask[0];
> | ^
> ./options.h:7816:26: error: zero-size array member 'cl_target_option::explicit_mask' not at end of 'struct cl_target_option' [-Werror=pedantic]
> 7816 | unsigned HOST_WIDE_INT explicit_mask[0];
> | ^~~~~~~~~~~~~
> ./options.h:7812:16: note: in the definition of 'struct cl_target_option'
> 7812 | struct GTY(()) cl_target_option
> | ^~~~~~~~~~~~~~~~
Oops, sorry.
The following patch should fix that and should also fix streaming of the
new explicit_mask_* members.
2020-10-05 Jakub Jelinek <jakub@redhat.com>
* opth-gen.awk: Don't emit explicit_mask array if n_target_explicit
is equal to n_target_explicit_mask.
* optc-save-gen.awk: Compute has_target_explicit_mask and if false,
don't emit code iterating over explicit_mask array elements. Stream
also explicit_mask_* target members.
|
|
I've noticed a -Wnarrowing warning on gimple-ssa-store-merging.c, this
change fixes that up.
2020-10-05 Jakub Jelinek <jakub@redhat.com>
* gimple-ssa-store-merging.c
(imm_store_chain_info::output_merged_store): Use ~0U instead of ~0 in
unsigned int array initializer.
|
|
When running the libgomp testsuite on x86_64-linux with nvptx accelerator on
the test-case included in this patch, we run into:
...
FAIL: libgomp.fortran/pr95654.f90 -O3 -fomit-frame-pointer -funroll-loops \
-fpeel-loops -ftracer -finline-functions execution test
...
The test-case is a minimal version of this FAIL:
...
FAIL: libgomp.fortran/pr66199-5.f90 -O3 -fomit-frame-pointer -funroll-loops \
-fpeel-loops -ftracer -finline-functions execution test
...
but that one has stopped failing at commit c2ebf4f10de "openmp: Add support
for non-rect simd and improve collapsed simd support".
The problem is that ftracer duplicates a block containing GOMP_SIMT_VOTE_ANY.
That is, before ftracer we have (dropping the GOMP_SIMT_ prefix):
...
bb4(ENTER_ALLOC)
*----------+
| \
| \
| v
| *
v bb8
*<------------*
bb5(VOTE_ANY)
*-------------+
| |
| |
| |
| |
| v
| *
v bb7(XCHG_IDX)
*<------------*
bb6(EXIT)
...
The XCHG_IDX internal-fn does inter-SIMT-lane communication, which for nvptx
maps onto shfl, an operator which has the requirement that the warp executing
the operator is convergent. The warp diverges at bb4, and
reconverges at bb5, and does not diverge by going to bb7, so the shfl is
indeed executed by a convergent warp.
After ftracer, we have:
...
bb4(ENTER_ALLOC)
*----------+
| \
| \
| \
| \
v v
* *
bb5(VOTE_ANY) bb8(VOTE_ANY)
* *
|\ /|
| \ +--------+ |
| \/ |
| /\ |
| / +----------v
|/ *
v bb7(XCHG_IDX)
*<--------------*
bb6(EXIT)
...
The warp diverges again at bb5, but does not reconverge again before bb6, so
the shfl is executed by a divergent warp, which causes the FAIL.
Fix this by making ftracer ignore blocks containing ENTER_ALLOC, VOTE_ANY and
EXIT, effectively treating the SIMT region conservatively.
An argument can be made that the test needs to be added in a more
generic place, like gimple_can_duplicate_bb_p or some such, and that ftracer
then needs to use the generic test. But that's a discussion with a much
broader scope, so I'm leaving that for another patch.
Bootstrapped and reg-tested on x86_64-linux.
Build on x86_64-linux with nvptx accelerator, tested with libgomp.
gcc/ChangeLog:
PR fortran/95654
* tracer.c (ignore_bb_p): Ignore GOMP_SIMT_ENTER_ALLOC,
GOMP_SIMT_VOTE_ANY and GOMP_SIMT_EXIT.
libgomp/ChangeLog:
2020-10-05 Tom de Vries <tdevries@suse.de>
PR fortran/95654
* testsuite/libgomp.fortran/pr95654.f90: New test.
|
|
|
|
The optional KIND argument to the MINLOC/MAXLOC intrinsic must not be
passed to the library function, as the kind conversion of the result
is treated explicitly elsewhere.
gcc/fortran/ChangeLog:
PR fortran/97272
* trans-intrinsic.c (strip_kind_from_actual): Helper function for
removal of KIND argument.
(gfc_conv_intrinsic_minmaxloc): Ignore KIND argument here, as it
is treated elsewhere.
gcc/testsuite/ChangeLog:
PR fortran/97272
* gfortran.dg/pr97272.f90: New test.
|
|
|
|
In recent Technology Levels of AIX 7.2, new "#ifdef __cplusplus" have been
added. Thus, the aix_malloc fix was applied in wrong locations. This patch
increases the context to avoid this.
fixincludes/ChangeLog:
2020-10-03 Clément Chigot <clement.chigot@atos.net>
* inclhack.def (aix_malloc): Add more context to select.
* fixincl.x: Regenerate.
* tests/base/malloc.h: Update expected results.
|
|
Mask/InverseMask options
Seems I've missed that set_option has special treatment for
CLVC_BIT_CLEAR/CLVC_BIT_SET.
Which means I'll need to change the generic handling, so that for
global_options_set elements mentioned in CLVC_BIT_* options are treated
differently, instead of using the accumulated bitmasks they'll need to use
their specific bitmask variables during the option saving/restoring.
Here is a patch that implements that.
2020-10-03 Jakub Jelinek <jakub@redhat.com>
* opth-gen.awk: For variables referenced in Mask and InverseMask,
don't use the explicit_mask bitmask array, but add separate
explicit_mask_* members with the same types as the variables.
* optc-save-gen.awk: Save, restore, compare and hash the separate
explicit_mask_* members.
|
|
* gcc.dg/tree-ssa/modref-3.c: New test.
|
|
this patch implements tracking of access ranges. This is only applied when
base pointer is an arugment. Incrementally i will extend it to also track
TBAA basetype so we can disambiguate ranges for accesses to same basetype
(which makes is quite bit more effective). For this reason i track the access
offset separately from parameter offset (the second track combined adjustments
to the parameter). This is I think last feature I would like to add to the
memory access summary this stage1.
Further work will be needed to opitmize the summary and merge adjacent
range/make collapsing more intelingent (so we do not lose track that often),
but I wanted to keep basic patch simple.
According to the cc1plus stats:
Alias oracle query stats:
refs_may_alias_p: 64108082 disambiguations, 74386675 queries
ref_maybe_used_by_call_p: 142319 disambiguations, 65004781 queries
call_may_clobber_ref_p: 23587 disambiguations, 29420 queries
nonoverlapping_component_refs_p: 0 disambiguations, 38117 queries
nonoverlapping_refs_since_match_p: 19489 disambiguations, 55748 must overlaps, 76044 queries
aliasing_component_refs_p: 54763 disambiguations, 755876 queries
TBAA oracle: 24184658 disambiguations 56823187 queries
16260329 are in alias set 0
10617146 queries asked about the same object
125 queries asked about the same alias set
0 access volatile
3960555 are dependent in the DAG
1800374 are aritificially in conflict with void *
Modref stats:
modref use: 10656 disambiguations, 47037 queries
modref clobber: 1473322 disambiguations, 1961464 queries
5027242 tbaa queries (2.563005 per modref query)
649087 base compares (0.330920 per modref query)
PTA query stats:
pt_solution_includes: 977385 disambiguations, 13609749 queries
pt_solutions_intersect: 1032703 disambiguations, 13187507 queries
Which should still compare with
https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554930.html
there is about 2% more load disambiguations and 3.6% more store that is not
great, but the TBAA part helps noticeably more and also this should help
with -fno-strict-aliasing.
I plan to work on improving param tracking too.
Bootstrapped/regtested x86_64-linux with the other changes, OK?
2020-10-02 Jan Hubicka <hubicka@ucw.cz>
* ipa-modref-tree.c (test_insert_search_collapse): Update andling
of accesses.
(test_merge): Likewise.
* ipa-modref-tree.h (struct modref_access_node): Add offset, size,
max_size, parm_offset and parm_offset_known.
(modref_access_node::useful_p): Constify.
(modref_access_node::range_info_useful_p): New predicate.
(modref_access_node::operator==): New.
(struct modref_parm_map): New structure.
(modref_tree::merge): Update for racking parameters)
* ipa-modref.c (dump_access): Dump new fields.
(get_access): Fill in new fields.
(merge_call_side_effects): Update handling of parm map.
(write_modref_records): Stream new fields.
(read_modref_records): Stream new fields.
(compute_parm_map): Update for new parm map.
(ipa_merge_modref_summary_after_inlining): Update.
(modref_propagate_in_scc): Update.
* tree-ssa-alias.c (modref_may_conflict): Handle known ranges.
|
|
PR other/97280
* doc/extend.texi: Replace roudnevenl with roundevenl
|
|
|
|
When Andrew Macleod investigated the recent rs6000 bootstrap failure,
he suggested a clean up of the headers in rs6000.c and rs6000-call.c.
It now is recommended to include ssa.h instead of the individual headers.
This also ensures that value-range.h is included and in the correct order
so that the tree-ssa-propagate.h inclusion of value-query.h and its
dependencies are satisfied.
Bootstrapped on powerpc-ibm-aix7.2.0.0 and powerpc64le-linux.
gcc/ChangeLog:
2020-10-02 David Edelsohn <dje.gcc@gmail.com>
Andrew MacLeod <amacleod@redhat.com>
* config/rs6000/rs6000.c: Include ssa.h. Reorder some headers.
* config/rs6000/rs6000-call.c: Same.
|
|
No one is interested in the mangled name of the C++20 template parameter
object for a class NTTP. So instead of printing
required for the satisfaction of ‘positive<T::ratio>’ [with T = X<::_ZTAXtl5ratioLin1ELi2EEE>]
let's print
required for the satisfaction of ‘positive<T::ratio>’ [with T = X<{-1, 2}>]
I don't think adding a test is necessary for this.
gcc/cp/ChangeLog:
PR c++/97014
* cxx-pretty-print.c (pp_cxx_template_argument_list): If the
argument is template_parm_object_p, print its DECL_INITIAL.
|
|
This fixes a linker error for older ARM cores without 64-bit atomics.
I think the { dg-add-options libatomic } is no longer needed, but it's
harmless to keep it there.
libstdc++-v3/ChangeLog:
* testsuite/29_atomics/atomic_float/value_init.cc: Use float
instead of double so that __atomic_load_8 isn't needed.
|
|
This test was supposed to verify that when __libc_single_threaded is
available we successfully detect recursive static initialization even
when linked to libpthread. But I forgot to that when recursive init is
detected, we terminate, and so the test fails.
This adds a terminate handler that exits cleanly, so the test passes
when recursive init is detected.
libstdc++-v3/ChangeLog:
* testsuite/18_support/96817.cc: Use terminate handler that
calls _Exit(0).
|
|
Here's the patch to remove DECL_ANTICIPATED, and with it hiddenness is
managed entirely in the symbol table. Sadly I couldn't get rid of the
actual field without more investigation -- it's repurposed for
OMP_PRIVATIZED_MEMBER. It looks like a the VAR-related flags in
lang_decl_base are not completely orthogonal, so perhaps some can be
turned into an enumeration or something. But that's more than I want
to do right now.
DECL_FRIEND_P Is still slightly suspect as it appears to mean more
than just in-class definition. However, I'm leaving that for now.
gcc/cp/
* cp-tree.h (lang_decl_base): anticipated_p is not used for
anticipatedness.
(DECL_ANTICIPATED): Delete.
* decl.c (duplicate_decls): Delete DECL_ANTICIPATED_management,
use was_hidden.
(cxx_builtin_function): Drop DECL_ANTICIPATED setting.
(xref_tag_1): Drop DECL_ANTICIPATED assert.
* name-lookup.c (name_lookup::adl_class_only): Drop
DECL_ANTICIPATED check.
(name_lookup::search_adl): Always dedup.
(anticipated_builtin_p): Reimplement.
(do_pushdecl): Drop DECL_ANTICIPATED asserts & update.
(lookup_elaborated_type_1): Drop DECL_ANTICIPATED update.
(do_pushtag): Drop DECL_ANTICIPATED setting.
* pt.c (push_template_decl): Likewise.
(tsubst_friend_class): Likewise.
libcc1/
* libcp1plugin.cc (libcp1plugin.cc): Drop DECL_ANTICIPATED test.
|
