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2024-11-15RISC-V: Remove unnecessary option for scalar SAT_ADD testcasePan Li123-186/+123
After we create a isolated folder to hold all SAT scalar test, we have fully control of what optimization options passing to the testcase. Thus, it is better to remove the unnecessary work around for flto option, as well as the -O3 option for each cases. The riscv.exp will pass sorts of different optimization options for each case. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_s_add-1-i16.c: Remove flto dg-skip workaround and -O3 option. * gcc.target/riscv/sat/sat_s_add-1-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_add-1-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_add-1-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_add-2-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_add-2-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_add-2-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_add-2-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_add-3-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_add-3-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_add-3-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_add-3-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_add-4-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_add-4-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_add-4-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_add-4-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-1-1.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-1.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-2-1.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-2.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-3-1.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-3.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-4.c: Ditto. * gcc.target/riscv/sat/sat_u_add-1-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-1-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-1-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-1-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-2-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-2-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-2-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-2-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-3-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-3-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-3-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-3-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-4-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-4-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-4-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-4-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-5-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-5-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-5-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-5-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-6-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-6-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-6-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-6-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-1-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-1-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-1-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-1-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-2-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-2-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-2-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-2-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-3-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-3-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-3-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-3-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-4-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-4-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-4-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-4-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-1.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-10.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-11.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-12.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-13.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-14.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-15.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-17.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-18.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-19.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-2.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-20.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-21.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-22.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-23.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-24.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-25.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-26.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-27.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-28.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-29.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-3.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-30.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-31.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-33.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-34.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-35.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-36.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-37.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-38.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-39.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-4.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-40.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-41.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-42.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-43.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-44.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-45.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-46.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-47.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-48.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-49.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-5.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-50.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-51.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-52.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-53.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-54.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-55.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-56.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-57.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-58.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-59.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-6.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-60.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-7.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-9.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com> Signed-off-by: Pan Li <pan2.li@intel.com>
2024-11-15testsuite: Change 3 tests from c++14 to c++11Jakub Jelinek3-3/+3
These tests are valid C++11, so we can run them in C++11 too. 2024-11-15 Jakub Jelinek <jakub@redhat.com> * g++.dg/tree-ssa/pr116868.C: Change effective target from c++14 to c++11. * g++.dg/tree-ssa/pr96945.C: Likewise. * g++.dg/tree-ssa/pr110819.C: Likewise.
2024-11-15c: Add _Decimal64x supportJakub Jelinek24-14/+285
The following patch adds _Decimal64x type support. Our dfp libraries (dpd & libbid) can only handle decimal32, decimal64 and decimal128 formats and I don't see that changing any time soon, so the following patch just hardcodes that _Decimal64x has the same mode as _Decimal128 (but is a distinct type). In the unlikely event some target would introduce something different that can be of course changed with target hooks but would be an ABI change. _Decimal128x is optional and we don't have a wider decimal type, so that type isn't added. 2024-11-15 Jakub Jelinek <jakub@redhat.com> gcc/ * tree-core.h (enum tree_index): Add TI_DFLOAT64X_TYPE. * tree.h (dfloat64x_type_node): Define. * tree.cc (build_common_tree_nodes): Initialize dfloat64x_type_node. * builtin-types.def (BT_DFLOAT64X): New DEF_PRIMITIVE_TYPE. (BT_FN_DFLOAT64X): New DEF_FUNCTION_TYPE_0. (BT_FN_DFLOAT64X_CONST_STRING, BT_FN_DFLOAT64X_DFLOAT64X): New DEF_FUNCTION_TYPE_1. * builtins.def (BUILT_IN_FABSD64X, BUILT_IN_INFD64X, BUILT_IN_NAND64X, BUILT_IN_NANSD64X): New builtins. * builtins.cc (expand_builtin): Handle BUILT_IN_FABSD64X. (fold_builtin_0): Handle BUILT_IN_INFD64X. (fold_builtin_1): Handle BUILT_IN_FABSD64X. * fold-const-call.cc (fold_const_call): Handle CFN_BUILT_IN_NAND64X and CFN_BUILT_IN_NANSD64X. * ginclude/float.h (DEC64X_MANT_DIG, DEC64X_MIN_EXP, DEC64X_MAX_EXP, DEC64X_MAX, DEC64X_EPSILON, DEC64X_MIN, DEC64X_TRUE_MIN, DEC64X_SNAN): Redefine. gcc/c-family/ * c-common.h (enum rid): Add RID_DFLOAT64X. * c-common.cc (c_global_trees): Fix comment typo. Add dfloat64x_type_node. (c_common_nodes_and_builtins): Handle RID_DFLOAT64X. * c-cppbuiltin.cc (c_cpp_builtins): Call builtin_define_decimal_float_constants also for dfloat64x_type_node if non-NULL. * c-lex.cc (interpret_float): Handle d64x suffixes. * c-pretty-print.cc (pp_c_floating_constant): Print d64x suffixes on dfloat64x_type_node typed constants. gcc/c/ * c-tree.h (enum c_typespec_keyword): Add cts_dfloat64x and adjust comment. * c-parser.cc (c_keyword_starts_typename, c_token_starts_declspecs, c_parser_declspecs, c_parser_gnu_attribute_any_word): Handle RID_DFLOAT64X. (c_parser_postfix_expression): Handle _Decimal64x arguments in __builtin_tgmath. (warn_for_abs): Handle BUILT_IN_FABSD64X. * c-decl.cc (declspecs_add_type): Handle cts_dfloat64x and RID_DFLOAT64X. (finish_declspecs): Handle cts_dfloat64x. * c-typeck.cc (c_common_type): Handle dfloat64x_type_node. gcc/testsuite/ * gcc.dg/dfp/c11-decimal64x-1.c: New test. * gcc.dg/dfp/c11-decimal64x-2.c: New test. * gcc.dg/dfp/c23-decimal64x-1.c: New test. * gcc.dg/dfp/c23-decimal64x-2.c: New test. * gcc.dg/dfp/c23-decimal64x-3.c: New test. * gcc.dg/dfp/c23-decimal64x-4.c: New test. libcpp/ * expr.cc (interpret_float_suffix): Handle d64x and D64x suffixes, adjust comment.
2024-11-15testsuite: fix g++.dg/tree-ssa/pr58483.CMarek Polacek1-2/+1
This test mistakenly used two dg-do compile. Since it passes in C++11 as well, we can run it in C++11 and up. gcc/testsuite/ChangeLog: * g++.dg/tree-ssa/pr58483.C: Run in C++11 and up.
2024-11-15RISC-V: Move scalar SAT_ADD test cases to a isolated folderPan Li188-1/+1041
Move the scalar SAT_ADD includes both the signed and unsigned integer to the folder gcc.target/riscv/sat. According to the implementation the below options will be appended for each test cases. * -O2 * -O3 * -Ofast * -Os * -Oz Then we can see the test log similar as below: Executing on host: .../sat_s_add-1-i8.c ... -O2 -march=rv64gc -S -o sat_s_add-1-i8.s Executing on host: .../sat_s_add-1-i8.c ... -O3 -march=rv64gc -S -o sat_s_add-1-i8.s Executing on host: .../sat_s_add-1-i8.c ... -Ofast -march=rv64gc -S -o sat_s_add-1-i8.s Executing on host: .../sat_s_add-1-i8.c ... -Oz -march=rv64gc -S -o sat_s_add-1-i8.s Executing on host: .../sat_s_add-1-i8.c ... -Os -march=rv64gc -S -o sat_s_add-1-i8.s The below test suites are passed for this patch. * The rv64gcv fully regression test. Committed as pre-approved by kito. gcc/testsuite/ChangeLog: * gcc.target/riscv/riscv.exp: Add new folder sat under riscv and add 5 options for each sat test. * gcc.target/riscv/sat_s_add-1-i16.c: Move to... * gcc.target/riscv/sat/sat_s_add-1-i16.c: ...here. * gcc.target/riscv/sat_s_add-1-i32.c: Move to... * gcc.target/riscv/sat/sat_s_add-1-i32.c: ...here. * gcc.target/riscv/sat_s_add-1-i64.c: Move to... * gcc.target/riscv/sat/sat_s_add-1-i64.c: ...here. * gcc.target/riscv/sat_s_add-1-i8.c: Move to... * gcc.target/riscv/sat/sat_s_add-1-i8.c: ...here. * gcc.target/riscv/sat_s_add-2-i16.c: Move to... * gcc.target/riscv/sat/sat_s_add-2-i16.c: ...here. * gcc.target/riscv/sat_s_add-2-i32.c: Move to... * gcc.target/riscv/sat/sat_s_add-2-i32.c: ...here. * gcc.target/riscv/sat_s_add-2-i64.c: Move to... * gcc.target/riscv/sat/sat_s_add-2-i64.c: ...here. * gcc.target/riscv/sat_s_add-2-i8.c: Move to... * gcc.target/riscv/sat/sat_s_add-2-i8.c: ...here. * gcc.target/riscv/sat_s_add-3-i16.c: Move to... * gcc.target/riscv/sat/sat_s_add-3-i16.c: ...here. * gcc.target/riscv/sat_s_add-3-i32.c: Move to... * gcc.target/riscv/sat/sat_s_add-3-i32.c: ...here. * gcc.target/riscv/sat_s_add-3-i64.c: Move to... * gcc.target/riscv/sat/sat_s_add-3-i64.c: ...here. * gcc.target/riscv/sat_s_add-3-i8.c: Move to... * gcc.target/riscv/sat/sat_s_add-3-i8.c: ...here. * gcc.target/riscv/sat_s_add-4-i16.c: Move to... * gcc.target/riscv/sat/sat_s_add-4-i16.c: ...here. * gcc.target/riscv/sat_s_add-4-i32.c: Move to... * gcc.target/riscv/sat/sat_s_add-4-i32.c: ...here. * gcc.target/riscv/sat_s_add-4-i64.c: Move to... * gcc.target/riscv/sat/sat_s_add-4-i64.c: ...here. * gcc.target/riscv/sat_s_add-4-i8.c: Move to... * gcc.target/riscv/sat/sat_s_add-4-i8.c: ...here. * gcc.target/riscv/sat_s_add-run-1-i16.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-1-i16.c: ...here. * gcc.target/riscv/sat_s_add-run-1-i32.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-1-i32.c: ...here. * gcc.target/riscv/sat_s_add-run-1-i64.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-1-i64.c: ...here. * gcc.target/riscv/sat_s_add-run-1-i8.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-1-i8.c: ...here. * gcc.target/riscv/sat_s_add-run-2-i16.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-2-i16.c: ...here. * gcc.target/riscv/sat_s_add-run-2-i32.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-2-i32.c: ...here. * gcc.target/riscv/sat_s_add-run-2-i64.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-2-i64.c: ...here. * gcc.target/riscv/sat_s_add-run-2-i8.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-2-i8.c: ...here. * gcc.target/riscv/sat_s_add-run-3-i16.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-3-i16.c: ...here. * gcc.target/riscv/sat_s_add-run-3-i32.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-3-i32.c: ...here. * gcc.target/riscv/sat_s_add-run-3-i64.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-3-i64.c: ...here. * gcc.target/riscv/sat_s_add-run-3-i8.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-3-i8.c: ...here. * gcc.target/riscv/sat_s_add-run-4-i16.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-4-i16.c: ...here. * gcc.target/riscv/sat_s_add-run-4-i32.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-4-i32.c: ...here. * gcc.target/riscv/sat_s_add-run-4-i64.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-4-i64.c: ...here. * gcc.target/riscv/sat_s_add-run-4-i8.c: Move to... * gcc.target/riscv/sat/sat_s_add-run-4-i8.c: ...here. * gcc.target/riscv/sat_s_add_imm-1-1.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-1-1.c: ...here. * gcc.target/riscv/sat_s_add_imm-1.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-1.c: ...here. * gcc.target/riscv/sat_s_add_imm-2-1.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-2-1.c: ...here. * gcc.target/riscv/sat_s_add_imm-2.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-2.c: ...here. * gcc.target/riscv/sat_s_add_imm-3-1.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-3-1.c: ...here. * gcc.target/riscv/sat_s_add_imm-3.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-3.c: ...here. * gcc.target/riscv/sat_s_add_imm-4.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-4.c: ...here. * gcc.target/riscv/sat_s_add_imm-run-1.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-run-1.c: ...here. * gcc.target/riscv/sat_s_add_imm-run-2.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-run-2.c: ...here. * gcc.target/riscv/sat_s_add_imm-run-3.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-run-3.c: ...here. * gcc.target/riscv/sat_s_add_imm-run-4.c: Move to... * gcc.target/riscv/sat/sat_s_add_imm-run-4.c: ...here. * gcc.target/riscv/sat_u_add-1-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-1-u16.c: ...here. * gcc.target/riscv/sat_u_add-1-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-1-u32.c: ...here. * gcc.target/riscv/sat_u_add-1-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-1-u64.c: ...here. * gcc.target/riscv/sat_u_add-1-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-1-u8.c: ...here. * gcc.target/riscv/sat_u_add-2-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-2-u16.c: ...here. * gcc.target/riscv/sat_u_add-2-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-2-u32.c: ...here. * gcc.target/riscv/sat_u_add-2-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-2-u64.c: ...here. * gcc.target/riscv/sat_u_add-2-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-2-u8.c: ...here. * gcc.target/riscv/sat_u_add-3-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-3-u16.c: ...here. * gcc.target/riscv/sat_u_add-3-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-3-u32.c: ...here. * gcc.target/riscv/sat_u_add-3-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-3-u64.c: ...here. * gcc.target/riscv/sat_u_add-3-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-3-u8.c: ...here. * gcc.target/riscv/sat_u_add-4-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-4-u16.c: ...here. * gcc.target/riscv/sat_u_add-4-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-4-u32.c: ...here. * gcc.target/riscv/sat_u_add-4-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-4-u64.c: ...here. * gcc.target/riscv/sat_u_add-4-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-4-u8.c: ...here. * gcc.target/riscv/sat_u_add-5-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-5-u16.c: ...here. * gcc.target/riscv/sat_u_add-5-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-5-u32.c: ...here. * gcc.target/riscv/sat_u_add-5-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-5-u64.c: ...here. * gcc.target/riscv/sat_u_add-5-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-5-u8.c: ...here. * gcc.target/riscv/sat_u_add-6-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-6-u16.c: ...here. * gcc.target/riscv/sat_u_add-6-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-6-u32.c: ...here. * gcc.target/riscv/sat_u_add-6-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-6-u64.c: ...here. * gcc.target/riscv/sat_u_add-6-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-6-u8.c: ...here. * gcc.target/riscv/sat_u_add-run-1-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-1-u16.c: ...here. * gcc.target/riscv/sat_u_add-run-1-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-1-u32.c: ...here. * gcc.target/riscv/sat_u_add-run-1-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-1-u64.c: ...here. * gcc.target/riscv/sat_u_add-run-1-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-1-u8.c: ...here. * gcc.target/riscv/sat_u_add-run-2-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-2-u16.c: ...here. * gcc.target/riscv/sat_u_add-run-2-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-2-u32.c: ...here. * gcc.target/riscv/sat_u_add-run-2-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-2-u64.c: ...here. * gcc.target/riscv/sat_u_add-run-2-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-2-u8.c: ...here. * gcc.target/riscv/sat_u_add-run-3-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-3-u16.c: ...here. * gcc.target/riscv/sat_u_add-run-3-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-3-u32.c: ...here. * gcc.target/riscv/sat_u_add-run-3-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-3-u64.c: ...here. * gcc.target/riscv/sat_u_add-run-3-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-3-u8.c: ...here. * gcc.target/riscv/sat_u_add-run-4-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-4-u16.c: ...here. * gcc.target/riscv/sat_u_add-run-4-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-4-u32.c: ...here. * gcc.target/riscv/sat_u_add-run-4-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-4-u64.c: ...here. * gcc.target/riscv/sat_u_add-run-4-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-4-u8.c: ...here. * gcc.target/riscv/sat_u_add-run-5-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-5-u16.c: ...here. * gcc.target/riscv/sat_u_add-run-5-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-5-u32.c: ...here. * gcc.target/riscv/sat_u_add-run-5-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-5-u64.c: ...here. * gcc.target/riscv/sat_u_add-run-5-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-5-u8.c: ...here. * gcc.target/riscv/sat_u_add-run-6-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-6-u16.c: ...here. * gcc.target/riscv/sat_u_add-run-6-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-6-u32.c: ...here. * gcc.target/riscv/sat_u_add-run-6-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-6-u64.c: ...here. * gcc.target/riscv/sat_u_add-run-6-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add-run-6-u8.c: ...here. * gcc.target/riscv/sat_u_add_imm-1-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-1-u16.c: ...here. * gcc.target/riscv/sat_u_add_imm-1-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-1-u32.c: ...here. * gcc.target/riscv/sat_u_add_imm-1-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-1-u64.c: ...here. * gcc.target/riscv/sat_u_add_imm-1-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-1-u8.c: ...here. * gcc.target/riscv/sat_u_add_imm-2-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-2-u16.c: ...here. * gcc.target/riscv/sat_u_add_imm-2-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-2-u32.c: ...here. * gcc.target/riscv/sat_u_add_imm-2-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-2-u64.c: ...here. * gcc.target/riscv/sat_u_add_imm-2-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-2-u8.c: ...here. * gcc.target/riscv/sat_u_add_imm-3-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-3-u16.c: ...here. * gcc.target/riscv/sat_u_add_imm-3-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-3-u32.c: ...here. * gcc.target/riscv/sat_u_add_imm-3-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-3-u64.c: ...here. * gcc.target/riscv/sat_u_add_imm-3-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-3-u8.c: ...here. * gcc.target/riscv/sat_u_add_imm-4-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-4-u16.c: ...here. * gcc.target/riscv/sat_u_add_imm-4-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-4-u32.c: ...here. * gcc.target/riscv/sat_u_add_imm-4-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-4-u64.c: ...here. * gcc.target/riscv/sat_u_add_imm-4-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-4-u8.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-1-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-1-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-1-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-1-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-2-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-2-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-2-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-2-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-3-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-3-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-3-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-3-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-4-u16.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-4-u32.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-4-u64.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c: ...here. * gcc.target/riscv/sat_u_add_imm-run-4-u8.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-1.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-1.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-10.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-10.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-11.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-11.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-12.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-12.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-13.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-13.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-14.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-14.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-15.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-15.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-16.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-16.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-17.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-17.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-18.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-18.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-19.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-19.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-2.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-2.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-20.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-20.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-21.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-21.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-22.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-22.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-23.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-23.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-24.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-24.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-25.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-25.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-26.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-26.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-27.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-27.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-28.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-28.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-29.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-29.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-3.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-3.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-30.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-30.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-31.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-31.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-32.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-32.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-33.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-33.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-34.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-34.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-35.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-35.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-36.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-36.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-37.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-37.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-38.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-38.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-39.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-39.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-4.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-4.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-40.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-40.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-41.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-41.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-42.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-42.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-43.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-43.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-44.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-44.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-45.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-45.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-46.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-46.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-47.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-47.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-48.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-48.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-49.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-49.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-5.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-5.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-50.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-50.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-51.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-51.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-52.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-52.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-53.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-53.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-54.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-54.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-55.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-55.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-56.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-56.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-57.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-57.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-58.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-58.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-59.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-59.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-6.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-6.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-60.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-60.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-7.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-7.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-8.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-8.c: ...here. * gcc.target/riscv/sat_u_add_imm_type_check-9.c: Move to... * gcc.target/riscv/sat/sat_u_add_imm_type_check-9.c: ...here. * gcc.target/riscv/sat/sat_arith.h: New test. * gcc.target/riscv/sat/sat_arith_data.h: New test. * gcc.target/riscv/sat/scalar_sat_binary.h: New test. * gcc.target/riscv/sat/scalar_sat_binary_run_xxx.h: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-11-15rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p5Kewen Lin1-24/+44
The current handlings in rs6000_emit_vector_compare is a bit complicated to me, especially after we emit vector float comparison insn with the given code directly. So it's better to refactor the handlings of vector integer comparison here. This is part 5, it's to refactor all the handlings of vector integer comparison to make it neat. This patch doesn't introduce any functionality change. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refactor the handlings of vector integer comparison.
2024-11-15rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p4Kewen Lin1-70/+17
The current handlings in rs6000_emit_vector_compare is a bit complicated to me, especially after we emit vector float comparison insn with the given code directly. So it's better to refactor the handlings of vector integer comparison here. This is part 4, it's to rework the handlings on GE/GEU/LE/LEU, also make the function not recursive any more. This patch doesn't introduce any functionality change. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refine the handlings for operators GE/GEU/LE/LEU.
2024-11-15rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p3Kewen Lin1-20/+10
The current handlings in rs6000_emit_vector_compare is a bit complicated to me, especially after we emit vector float comparison insn with the given code directly. So it's better to refactor the handlings of vector integer comparison here. This is part 3, it's to refactor the handlings on NE. This patch doesn't introduce any functionality change. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refactor the handlings for operator NE.
2024-11-15rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p2Kewen Lin1-23/+9
The current handlings in rs6000_emit_vector_compare is a bit complicated to me, especially after we emit vector float comparison insn with the given code directly. So it's better to refactor the handlings of vector integer comparison here. This is part 2, it's to refactor the handlings on LT and LTU. This patch doesn't introduce any functionality change. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Refine the handlings for operators LT and LTU.
2024-11-15rs6000: Rework vector integer comparison in rs6000_emit_vector_compare - p1Kewen Lin1-28/+9
The current handlings in rs6000_emit_vector_compare is a bit complicated to me, especially after we emit vector float comparison insn with the given code directly. So it's better to refactor the handlings of vector integer comparison here. This is part 1, it's to remove the helper function rs6000_emit_vector_compare_inner and move the logics into rs6000_emit_vector_compare. This patch doesn't introduce any functionality change. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Remove. (rs6000_emit_vector_compare): Emit rtx comparison for operators EQ/ GT/GTU directly.
2024-11-15rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p4Kewen Lin1-20/+4
All kinds of vector float comparison operators have been supported in a rtl comparison pattern as vector.md, we can just emit an rtx comparison insn with the given comparison operator in function rs6000_emit_vector_compare instead of checking and handling the reverse condition cases. This is part 4, it further checks for comparison opeators LT/UNGE. In rs6000_emit_vector_compare, for the handling of LT, it switches to use code GT, swaps operands and try again, it's exactly the same as what we have in vector.md: ; lt(a,b) = gt(b,a) As to UNGE, in rs6000_emit_vector_compare, it uses reversed code LT and further operates on the result with one_cmpl, it's also the same as what's in vector.md: ; unge(a,b) = ~lt(a,b) This patch should not have any functionality change too. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Emit rtx comparison for operators LT/UNGE of MODE_VECTOR_FLOAT directly. (rs6000_emit_vector_compare): Move assertion of no MODE_VECTOR_FLOAT to function beginning.
2024-11-15rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p3Kewen Lin2-5/+30
All kinds of vector float comparison operators have been supported in a rtl comparison pattern as vector.md, we can just emit an rtx comparison insn with the given comparison operator in function rs6000_emit_vector_compare instead of checking and handling the reverse condition cases. This is part 3, it further checks for comparison opeators LE/UNGT. In rs6000_emit_vector_compare, UNGT is handled with reversed code LE and inverting with one_cmpl_optab, LE is handled with LT ior EQ, while in vector.md, we have the support: ; le(a,b) = ge(b,a) ; ungt(a,b) = ~le(a,b) The associated test case shows it's an improvement. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Emit rtx comparison for operators LE/UNGT of MODE_VECTOR_FLOAT directly. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vcond-fp.c: New test.
2024-11-15rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p2Kewen Lin1-12/+8
All kinds of vector float comparison operators have been supported in a rtl comparison pattern as vector.md, we can just emit an rtx comparison insn with the given comparison operator in function rs6000_emit_vector_compare instead of checking and handling the reverse condition cases. This is part 2, it further checks for comparison opeators NE/UNLE/UNLT. In rs6000_emit_vector_compare, they are handled with reversed code which is queried from function reverse_condition_maybe_unordered and inverting with one_cmpl_optab. It's the same as what we have in vector.md: ; ne(a,b) = ~eq(a,b) ; unle(a,b) = ~gt(a,b) ; unlt(a,b) = ~ge(a,b) The operators on the right side have been supported in part 1. This patch should not have any functionality change too. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Emit rtx comparison for operators NE/UNLE/UNLT of MODE_VECTOR_FLOAT directly.
2024-11-15rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p1Kewen Lin1-16/+31
All kinds of vector float comparison operators have been supported in a rtl comparison pattern as vector.md, we can just emit an rtx comparison insn with the given comparison operator in function rs6000_emit_vector_compare instead of checking and handling the reverse condition cases. This is part 1, it only handles the operators which are already emitted with an rtx comparison previously in function rs6000_emit_vector_compare_inner, they are EQ/GT/GE/ORDERED/ UNORDERED/UNEQ/LTGT. There is no functionality change. With this change, rs6000_emit_vector_compare_inner would only work for vector integer comparison handling, it would be cleaned up later in vector integer comparison rework. gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_vector_compare_inner): Move MODE_VECTOR_FLOAT handlings out. (rs6000_emit_vector_compare): Emit rtx comparison for operators EQ/GT/ GE/UNORDERED/ORDERED/UNEQ/LTGT of MODE_VECTOR_FLOAT directly, and adjust one call site of rs6000_emit_vector_compare_inner to rs6000_emit_vector_compare.
2024-11-15Daily bump.GCC Administrator5-1/+68
2024-11-15libstdc++: Fix indentation in std::list::emplace_backJonathan Wakely1-1/+1
libstdc++-v3/ChangeLog: * include/bits/stl_list.h (list::emplace_back): Fix indentation.
2024-11-14[RISC-V][V2] Fix type on vector move patternsJeff Law1-2/+8
Updated version of my prior patch to fix type attributes on the pre-allocation vector move pattern. This version just adds a suitable set of attributes to a second pattern that was obviously wrong. Passed on my tester for rv64 and rv32 crosses. Bootstrapped and regression tested on riscv64-linux-gnu as well. -- So I was looking into a horrific schedule for SAD a week or so ago and came across this gem. Basically we were treating a vector load as a vector move from a scheduling standpoint during sched1. Naturally we didn't expose much ILP during sched1. That in turn caused the register allocator to pack the pseudos onto the physical vector registers tightly. regrename didn't do anything useful and the resulting code had too many false dependencies for sched2 to do anything useful. As a result we were taking many load->use stalls in x264's SAD routine. I'm confident the types are fine, but I'm a lot less sure about the other attributes (mode, avl_type_index, mode_idx). If someone could take a look at that, it'd be greatly appreciated. There's other cases that may need similar treatment. But I didn't want to muck with them until I understood those other attributes and how they need adjustments. In particular mov<VLS_AVL_REG:mode><P:mode>_lra appears to have the same problem. -- gcc/ * config/riscv/vector.md (mov<mode> pattern/splitter): Fix type and other attributes. (mov<VLS_AVL_REG:mode><P:mode>_lra): Likewise.
2024-11-14Fortran: fix passing of NULL() actual argument to character dummy [PR104819]Harald Anlauf2-0/+300
Ensure that character length is set and passed by the call to a procedure when its dummy argument is NULL() with MOLD argument present, or set length to either 0 or the callee's expected character length. For assumed-rank dummies, use the rank of the MOLD argument. Generate temporaries for passed arguments when needed. PR fortran/104819 gcc/fortran/ChangeLog: * trans-expr.cc (conv_null_actual): Helper function to handle passing of NULL() to non-optional dummy arguments of non-bind(c) procedures. (gfc_conv_procedure_call): Use it for character dummies. gcc/testsuite/ChangeLog: * gfortran.dg/null_actual_6.f90: New test.
2024-11-14gcc: regenerate configureSam James1-6/+8
r15-5257-g56ded80b96b0f6 didn't regenerate configure correctly. See https://inbox.sourceware.org/gcc-patches/ZzZf69gORVPRo6Ct@zen.kayari.org/. gcc/ChangeLog: * configure: Regenerate.
2024-11-15The fix for PR117191Denis Chertykov1-0/+5
Wrong code appears after dse2 pass because it removes necessary insns. (ie insn 554 - store to frame spill slot) This happened because LRA pass doesn't cleanup the code exactly like reload does. The reload1.c has a special pass for such cleanup. The reload removes CLOBBER insns with spill slots like this: (insn 202 184 186 7 (clobber (mem/c:TI (plus:HI (reg/f:HI 28 r28) (const_int 1 [0x1])) [3 %sfp+1 S16 A8])) -1 (nil)) Fragment from reload1.c: -------------------------------------------------------------------------------- reload_completed = 1; /* Make a pass over all the insns and delete all USEs which we inserted only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED notes. Delete all CLOBBER insns, except those that refer to the return value and the special mem:BLK CLOBBERs added to prevent the scheduler from misarranging variable-array code, and simplify (subreg (reg)) operands. Strip and regenerate REG_INC notes that may have been moved around. */ for (insn = first; insn; insn = NEXT_INSN (insn)) if (INSN_P (insn)) { rtx *pnote; if (CALL_P (insn)) replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn), VOIDmode, CALL_INSN_FUNCTION_USAGE (insn)); if ((GET_CODE (PATTERN (insn)) == USE /* We mark with QImode USEs introduced by reload itself. */ && (GET_MODE (insn) == QImode || find_reg_note (insn, REG_EQUAL, NULL_RTX))) || (GET_CODE (PATTERN (insn)) == CLOBBER && (!MEM_P (XEXP (PATTERN (insn), 0)) || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH && XEXP (XEXP (PATTERN (insn), 0), 0) != stack_pointer_rtx)) && (!REG_P (XEXP (PATTERN (insn), 0)) || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) { delete_insn (insn); continue; } -------------------------------------------------------------------------------- LRA have a similar place where it removes unnecessary insns, but not CLOBBER insns with memory spill slots. It's `lra_final_code_change' function. I just mark a CLOBBER insn with pseudo spilled to memory for removing it later together with LRA temporary CLOBBER insns. PR rtl-optimization/117191 gcc/ * lra-spills.cc (spill_pseudos): Mark a CLOBBER insn with pseudo spilled to memory for removing it later together with LRA temporary CLOBBER insns.
2024-11-14libstdc++: Make equal and is_permutation short-circuit (LWG 3560)Jonathan Wakely6-26/+145
We already implement short-circuiting for random access iterators, but we also need to do so for ranges::equal and ranges::is_permutation when given sized ranges that are not random access ranges (e.g. std::list). libstdc++-v3/ChangeLog: * include/bits/ranges_algo.h (__is_permutation_fn::operator()): Short-circuit for sized ranges with different sizes, as per LWG 3560. * include/bits/ranges_algobase.h (__equal_fn::operator()): Likewise. * include/bits/stl_algo.h (__is_permutation): Use if-constexpr for random access iterator branches. * include/bits/stl_algobase.h (__equal4): Likewise. * testsuite/25_algorithms/equal/lwg3560.cc: New test. * testsuite/25_algorithms/is_permutation/lwg3560.cc: New test. Reviewed-by: Patrick Palka <ppalka@redhat.com>
2024-11-14ipa: Rationalize IPA-VR computations across pass-through jump functionsMartin Jambor1-114/+67
Currently ipa_value_range_from_jfunc and propagate_vr_across_jump_function contain similar but not same code for dealing with pass-through jump functions. This patch puts these common bits into one function which can also handle comparison operations. gcc/ChangeLog: 2024-11-01 Martin Jambor <mjambor@suse.cz> PR ipa/114985 * ipa-cp.cc (ipa_vr_intersect_with_arith_jfunc): New function. (ipa_value_range_from_jfunc): Move the common functionality to the above new function, adjust the rest so that it works with it well. (propagate_vr_across_jump_function): Likewise.
2024-11-14libstdc++: Implement LWG 3563 changes to keys_view and values_viewPatrick Palka2-2/+18
This LWG issue corrects the definition of these alias templates to make them suitable for alias CTAD. libstdc++-v3/ChangeLog: * include/std/ranges (keys_view): Adjust as per LWG 3563. (values_view): Likewise. * testsuite/std/ranges/adaptors/elements.cc (test08): New test. Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
2024-11-14libstdc++: Fix get<0> constraint for lvalue ranges::subrange (LWG 3589)Jonathan Wakely2-1/+34
Apprived at October 2021 plenary. libstdc++-v3/ChangeLog: * include/bits/ranges_util.h (subrange::begin): Fix constraint, as per LWG 3589. * testsuite/std/ranges/subrange/lwg3589.cc: New test.
2024-11-14Daily bump.GCC Administrator16-1/+1268
2024-11-14contrib: Add another ignored commitJeff Law1-0/+1
* gcc-changelog/git_update_version.py (ignored_commits): Add another ignored commit.
2024-11-14libstdc++: Make _GLIBCXX_NODISCARD work for C++11 and C++14Jonathan Wakely27-41/+39
The _GLIBCXX_NODISCARD macro only expands to [[__nodiscard__]] for C++17 and later, but all supported compilers will allow us to use that for C++11 and C++14 too. Enable it for those older standards, to give improved diagnostics for users of those older standards. libstdc++-v3/ChangeLog: * include/bits/c++config (_GLIBCXX_NODISCARD): Expand for C++11 and C++14. * testsuite/22_locale/locale/cons/12438.cc: Adjust dg-warning to expect nodiscard warnings for C++11 and C++14 as well. * testsuite/22_locale/locale/operations/2.cc: Likewise. * testsuite/25_algorithms/equal/debug/1_neg.cc: Likewise. * testsuite/25_algorithms/equal/debug/2_neg.cc: Likewise. * testsuite/25_algorithms/equal/debug/3_neg.cc: Likewise. * testsuite/25_algorithms/find_first_of/concept_check_1.cc: Likewise. * testsuite/25_algorithms/is_permutation/2.cc: Likewise. * testsuite/25_algorithms/lexicographical_compare/71545.cc: Likewise. * testsuite/25_algorithms/lower_bound/33613.cc: Likewise. * testsuite/25_algorithms/lower_bound/debug/irreflexive.cc: Likewise. * testsuite/25_algorithms/lower_bound/debug/partitioned_neg.cc: Likewise. * testsuite/25_algorithms/lower_bound/debug/partitioned_pred_neg.cc: Likewise. * testsuite/25_algorithms/minmax/3.cc: Likewise. * testsuite/25_algorithms/search/78346.cc: Likewise. * testsuite/25_algorithms/search_n/58358.cc: Likewise. * testsuite/25_algorithms/unique/1.cc: Likewise. * testsuite/25_algorithms/unique/11480.cc: Likewise. * testsuite/25_algorithms/upper_bound/33613.cc: Likewise. * testsuite/25_algorithms/upper_bound/debug/partitioned_neg.cc: Likewise. * testsuite/25_algorithms/upper_bound/debug/partitioned_pred_neg.cc: Likewise. * testsuite/27_io/ios_base/types/fmtflags/bitmask_operators.cc: Likewise. * testsuite/27_io/ios_base/types/iostate/bitmask_operators.cc: Likewise. * testsuite/27_io/ios_base/types/openmode/bitmask_operators.cc: Likewise. * testsuite/ext/concept_checks.cc: Likewise. * testsuite/ext/is_heap/47709.cc: Likewise. * testsuite/ext/is_sorted/cxx0x.cc: Likewise.
2024-11-14contrib: Add 2 further ignored commitsJeff Law1-0/+2
I goof'd and double-reverted a change. Add those to the ignore list, leaving the final reversion as-is. * gcc-changelog/git_update_version.py (ignored_commits): Add 2 further commits.
2024-11-14libstdc++: stdc++.h and <coroutine>Jason Merrill1-3/+3
r13-3036 moved #include <coroutine> into the new freestanding section, but also moved it from a C++20 section to a C++23 section. This patch moves it back. Incidentally, I'm curious why a few headers were removed from the hosted section (including <coroutine>), but most were left in place, so we have redundant includes of most hosted headers. libstdc++-v3/ChangeLog: * include/precompiled/stdc++.h: <coroutine> is C++20.
2024-11-14c++: fix namespace alias exportJason Merrill3-2/+28
This affected std::views in module std. gcc/cp/ChangeLog: * name-lookup.cc (do_namespace_alias): set_originating_module after pushdecl. gcc/testsuite/ChangeLog: * g++.dg/modules/namespace-7_a.C: New test. * g++.dg/modules/namespace-7_b.C: New test.
2024-11-14c++: module dialect tweakJason Merrill1-2/+3
Coroutines have been enabled by -std=c++20 since GCC 11. gcc/cp/ChangeLog: * module.cc (module_state_config::get_dialect): Expect coroutines in C++20.
2024-11-14Fix common.opt.urlsJan Hubicka1-1/+1
gcc/ChangeLog: * common.opt.urls: Fix.
2024-11-14Revert "Reapply "[PATCH v2] RISC-V: zero_extend(not) -> xor optimization ↵Jeff Law2-36/+0
[PR112398]"" This reverts commit 10d76b7f1e5b63ad6d2b92940c39007913ced037.
2024-11-14aarch64: Fix nonlocal goto tests incompatible with GCSYury Khrustalev4-3/+36
gcc/testsuite/ChangeLog: * gcc.target/aarch64/gcs-nonlocal-3.c: New test. * gcc.target/aarch64/sme/nonlocal_goto_4.c: Update. * gcc.target/aarch64/sme/nonlocal_goto_5.c: Update. * gcc.target/aarch64/sme/nonlocal_goto_6.c: Update.
2024-11-14aarch64: Fix tests incompatible with GCSMatthieu Longo2-6/+26
gcc/testsuite/ChangeLog: * g++.target/aarch64/return_address_sign_ab_exception.C: Update. * gcc.target/aarch64/eh_return.c: Update.
2024-11-14aarch64: Add tests and docs for indirect_return attributeRichard Ball4-0/+121
This patch adds a new testcase and docs for indirect_return attribute. gcc/ChangeLog: * doc/extend.texi: Add AArch64 docs for indirect_return attribute. gcc/testsuite/ChangeLog: * gcc.target/aarch64/indirect_return-1.c: New test. * gcc.target/aarch64/indirect_return-2.c: New test. * gcc.target/aarch64/indirect_return-3.c: New test. Co-authored-by: Yury Khrustalev <yury.khrustalev@arm.com>
2024-11-14aarch64: Introduce indirect_return attributeSzabolcs Nagy8-15/+88
Tail calls of indirect_return functions from non-indirect_return functions are disallowed even if BTI is disabled, since the call site may have BTI enabled. Needed for swapcontext within the same function when GCS is enabled. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_gnu_attributes): Add indirect_return. (aarch64_gen_callee_cookie): Use indirect_return attribute. (aarch64_callee_indirect_return): New. (aarch_fun_is_indirect_return): New. (aarch64_function_ok_for_sibcall): Disallow tail calls if caller is non-indirect_return but callee is indirect_return. (aarch64_function_arg): Add indirect_return to cookie. (aarch64_init_cumulative_args): Record indirect_return in CUMULATIVE_ARGS. (aarch64_comp_type_attributes): Check indirect_return attribute. (aarch64_output_mi_thunk): Add indirect_return to cookie. * config/aarch64/aarch64.h (CUMULATIVE_ARGS): Add new field indirect_return. * config/aarch64/aarch64.md (tlsdesc_small_<mode>): Update. * config/aarch64/aarch64-opts.h (AARCH64_NUM_ABI_ATTRIBUTES): New. * config/aarch64/aarch64-protos.h (aarch64_gen_callee_cookie): Update. * config/arm/aarch-bti-insert.cc (call_needs_bti_j): New. (rest_of_insert_bti): Use call_needs_bti_j. * config/arm/aarch-common-protos.h (aarch_fun_is_indirect_return): New. * config/arm/arm.cc (aarch_fun_is_indirect_return): New. Co-authored-by: Yury Khrustalev <yury.khrustalev@arm.com>
2024-11-14aarch64: libatomic: add GCS marking to asmSzabolcs Nagy1-2/+9
libatomic/ChangeLog: * config/linux/aarch64/atomic_16.S (FEATURE_1_GCS): Define. (GCS_FLAG): Define if GCS is enabled. (GNU_PROPERTY): Add GCS_FLAG.
2024-11-14aarch64: libgcc: add GCS marking to asmSzabolcs Nagy1-2/+14
libgcc/ChangeLog: * config/aarch64/aarch64-asm.h (FEATURE_1_GCS): Define. (GCS_FLAG): Define if GCS is enabled. (GNU_PROPERTY): Add GCS_FLAG.
2024-11-14aarch64: Emit GNU property NOTE for GCSSzabolcs Nagy1-0/+5
gcc/ChangeLog: * config/aarch64/aarch64.cc (GNU_PROPERTY_AARCH64_FEATURE_1_GCS): Define. (aarch64_file_end_indicate_exec_stack): Set GCS property bit.
2024-11-14aarch64: Add GCS support to the unwinderSzabolcs Nagy1-1/+58
Follows the current linux ABI that uses single signal entry token and shared shadow stack between thread and alt stack. Could be behind __ARM_FEATURE_GCS_DEFAULT ifdef (only do anything special with gcs compat codegen) but there is a runtime check anyway. Change affected tests to be compatible with -mbranch-protection=standard libgcc/ChangeLog: * config/aarch64/aarch64-unwind.h (_Unwind_Frames_Extra): Update. (_Unwind_Frames_Increment): Define.
2024-11-14aarch64: Add target pragma tests for gcsSzabolcs Nagy1-0/+35
gcc/testsuite/ChangeLog: * gcc.target/aarch64/pragma_cpp_predefs_4.c: Add gcs specific tests.
2024-11-14aarch64: Add test for GCS ACLE defsSzabolcs Nagy1-0/+30
gcc/testsuite/ChangeLog: * gcc.target/aarch64/pragma_cpp_predefs_1.c: GCS test.
2024-11-14aarch64: Add ACLE feature macros for GCSSzabolcs Nagy1-0/+3
gcc/ChangeLog: * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define macros for GCS.
2024-11-14aarch64: Add non-local goto and jump tests for GCSSzabolcs Nagy6-0/+64
These are scan asm tests only, relying on existing execution tests for runtime coverage. gcc/testsuite/ChangeLog: * gcc.target/aarch64/gcs-nonlocal-1.c: New test. * gcc.target/aarch64/gcs-nonlocal-1-track-speculation.c: New test. * gcc.target/aarch64/gcs-nonlocal-2.c: New test. * gcc.target/aarch64/gcs-nonlocal-2-track-speculation.c: New test. * gcc.target/aarch64/gcs-nonlocal-1.h: New header file. * gcc.target/aarch64/gcs-nonlocal-2.h: New header file.
2024-11-14aarch64: Add GCS support for nonlocal stack saveSzabolcs Nagy3-2/+91
Nonlocal stack save and restore has to also save and restore the GCS pointer. This is used in __builtin_setjmp/longjmp and nonlocal goto. The GCS specific code is only emitted if GCS branch-protection is enabled and the code always checks at runtime if GCS is enabled. The new -mbranch-protection=gcs and old -mbranch-protection=none code are ABI compatible: jmpbuf for __builtin_setjmp has space for 5 pointers, the layout is old layout: fp, pc, sp, unused, unused new layout: fp, pc, sp, gcsp, unused Note: the ILP32 code generation is wrong as it saves the pointers with Pmode (i.e. 8 bytes per pointer), but the user supplied buffer size is for 5 pointers (4 bytes per pointer), this is not fixed. The nonlocal goto has no ABI compatibility issues as the goto and its destination are in the same translation unit. We use CDImode to allow extra space for GCS without the effect of 16-byte alignment. gcc/ChangeLog: * config/aarch64/aarch64.h (STACK_SAVEAREA_MODE): Make space for gcs. * config/aarch64/aarch64.md (save_stack_nonlocal): New. (restore_stack_nonlocal): New. * tree-nested.cc (get_nl_goto_field): Updated.
2024-11-14aarch64: Add __builtin_aarch64_gcs* and __gcs* testsSzabolcs Nagy4-0/+184
gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/gcs-1.c: New test. * gcc.target/aarch64/gcspopm-1.c: New test. * gcc.target/aarch64/gcspr-1.c: New test. * gcc.target/aarch64/gcsss-1.c: New test. Co-authored-by: Yury Khrustalev <yury.khrustalev@arm.com>
2024-11-14aarch64: Add ACLE __gcs* intrinsicsYury Khrustalev1-0/+9
Add the following ACLE intrinsics: - void *__gcspr(void); - uint64_t __gcspopm(void); - void *__gcsss(void *); gcc/ChangeLog: * config/aarch64/arm_acle.h (__gcspr): New. (__gcspopm): New. (__gcsss): New.
2024-11-14aarch64: Add GCS builtinsSzabolcs Nagy1-0/+75
Add new builtins for GCS: void *__builtin_aarch64_gcspr (void) uint64_t __builtin_aarch64_gcspopm (void) void *__builtin_aarch64_gcsss (void *) The builtins are always enabled, but should be used behind runtime checks in case the target does not support GCS. They are thin wrappers around the corresponding instructions. The GCS pointer is modelled with void * type (normal stores do not work on GCS memory, but it is writable via the gcsss operation or via GCSSTR if enabled so not const) and an entry on the GCS is modelled with uint64_t (since it has fixed size and can be a token that's not a pointer). gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc (enum aarch64_builtins): Add AARCH64_BUILTIN_GCSPR, AARCH64_BUILTIN_GCSPOPM, AARCH64_BUILTIN_GCSSS. (aarch64_init_gcs_builtins): New. (aarch64_general_init_builtins): Call aarch64_init_gcs_builtins. (aarch64_expand_gcs_builtin): New. (aarch64_general_expand_builtin): Call aarch64_expand_gcs_builtin. Co-authored-by: Richard Sandiford <richard.sandiford@arm.com>
2024-11-14aarch64: Add GCS instructionsSzabolcs Nagy1-0/+39
Add instructions for the Guarded Control Stack extension. GCSSS1 and GCSSS2 are always used together in the compiler and an extra "mov xn, 0" should be always added before GCSSS2 to clear the output register. This is needed to get reasonable result when GCS is disabled, when these instructions are NOPs. Since the instructions are expected to be used behind runtime feature checks, this is mainly relevant if GCS can be disabled asynchronously. GCSPOPM does not have embedded move and code code that emits this instruction must first emit a zeroing of operand 1 to get a reasonable result when GCS is not enabled. The output of GCSPOPM is usually not needed, so a separate gcspopm_xzr was added to model that. Did not do the same for GCSSS as it is a less common operation. The used mnemonics do not depend on updated assembler since these instructions can be used without new -march setting behind a runtime check. Reading the GCSPR is modelled as unspec_volatile so it does not get reordered wrt the other instructions changing the GCSPR. gcc/ChangeLog: * config/aarch64/aarch64.md (aarch64_load_gcspr): New. (aarch64_gcspopm): New. (aarch64_gcspopm_xzr): New. (aarch64_gcsss1): New. (aarch64_gcsss2): New. Co-authored-by: Richard Sandiford <richard.sandiford@arm.com>
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