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2020-08-21driver: Fix several memory leaks [PR63854]Alex Coplan1-8/+52
This patch fixes several memory leaks in the driver, all of which relate to the handling of static specs. We introduce functions set_static_spec_{shared,owned}() which are used to enforce proper memory management when updating the strings in the static_specs table. This is achieved by making use of the alloc_p field in the table entries. Similarly to set_spec(), each time we update an entry, we check whether alloc_p is set, and free the old value if so. We then set alloc_p correctly based on whether we "own" this memory or whether we're just taking a pointer to a shared string which we shouldn't free. The following table shows the number of leaks found by AddressSanitizer when running a minimal libgccjit program on AArch64. The test program does the whole libgccjit compilation cycle in a loop (including acquiring and releasing the context), and the table below shows the number of leaks for different iterations of that loop. +--------------+-----+-----+------+---------------+ | # of runs > | 1 | 2 | 3 | Leaks per run | +--------------+-----+-----+------+---------------+ | Before patch | 463 | 940 | 1417 | 477 | +--------------+-----+-----+------+---------------+ | After patch | 416 | 846 | 1276 | 430 | +--------------+-----+-----+------+---------------+ gcc/ChangeLog: PR jit/63854 * gcc.c (set_static_spec): New. (set_static_spec_owned): New. (set_static_spec_shared): New. (driver::maybe_putenv_COLLECT_LTO_WRAPPER): Use set_static_spec_owned() to take ownership of lto_wrapper_file such that it gets freed in driver::finalize. (driver::maybe_run_linker): Use set_static_spec_shared() to ensure that we don't try and free() the static string "ld", also ensuring that any previously-allocated string in linker_name_spec is freed. Likewise with argv0. (driver::finalize): Use set_static_spec_shared() when resetting specs that previously had allocated strings; remove if(0) around call to free().
2020-08-21Allow try_split to split RTX_FRAME_RELATED_P insnsSenthil Kumar Selvaraj3-65/+90
Instead of rejecting RTX_FRAME_RELATED_P insns, allow try_split to split such insns, provided the split is after reload, and the result of the split is a single insn. recog.c:peep2_attempt already splits an RTX_FRAME_RELATED_P insn splitting to a single insn. This patch refactors existing code copying frame related info to a separate function (copy_frame_info_to_split_insn) and calls it from both peep2_attempt and try_split. 2020-08-21 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org> gcc/ChangeLog: * emit-rtl.c (try_split): Call copy_frame_info_to_split_insn to split certain RTX_FRAME_RELATED_P insns. * recog.c (copy_frame_info_to_split_insn): New function. (peep2_attempt): Split copying of frame related info of RTX_FRAME_RELATED_P insns into above function and call it. * recog.h (copy_frame_info_to_split_insn): Declare it.
2020-08-21libstdc++: Skip PSTL tests when installed TBB is too old [PR 96718]Jonathan Wakely4-0/+4
These tests do not actually require TBB, because they only inspect the feature test macros present in the headers. However, if TBB is installed then its headers will be included, and the version will be checked. If the version is too old, compilation fails due to a #error directive. This change disables the tests if TBB is not present, so that we skip them instead of failing. libstdc++-v3/ChangeLog: PR libstdc++/96718 * testsuite/25_algorithms/pstl/feature_test-2.cc: Require tbb-backend effective target. * testsuite/25_algorithms/pstl/feature_test-3.cc: Likewise. * testsuite/25_algorithms/pstl/feature_test-5.cc: Likewise. * testsuite/25_algorithms/pstl/feature_test.cc: Likewise.
2020-08-21Enable bitwise operation for type mask.liuhongt13-68/+472
Enable operator or/xor/and/andn/not for mask register, kxnor is not enabled since there's no corresponding instruction for general registers. gcc/ PR target/88808 * config/i386/i386.c (ix86_preferred_reload_class): Allow QImode data go into mask registers. * config/i386/i386.md: (*movhi_internal): Adjust constraints for mask registers. (*movqi_internal): Ditto. (*anddi_1): Support mask register operations (*and<mode>_1): Ditto. (*andqi_1): Ditto. (*andn<mode>_1): Ditto. (*<code><mode>_1): Ditto. (*<code>qi_1): Ditto. (*one_cmpl<mode>2_1): Ditto. (*one_cmplsi2_1_zext): Ditto. (*one_cmplqi2_1): Ditto. (define_peephole2): Move constant 0/-1 directly into mask registers. * config/i386/predicates.md (mask_reg_operand): New predicate. * config/i386/sse.md (define_split): Add post-reload splitters that would convert "generic" patterns to mask patterns. (*knotsi_1_zext): New define_insn. gcc/testsuite/ * gcc.target/i386/bitwise_mask_op-1.c: New test. * gcc.target/i386/bitwise_mask_op-2.c: New test. * gcc.target/i386/bitwise_mask_op-3.c: New test. * gcc.target/i386/avx512bw-pr88465.c: New testcase. * gcc.target/i386/avx512bw-kunpckwd-1.c: Adjust testcase. * gcc.target/i386/avx512bw-kunpckwd-3.c: Ditto. * gcc.target/i386/avx512dq-kmovb-5.c: Ditto. * gcc.target/i386/avx512f-kmovw-5.c: Ditto. * gcc.target/i386/pr55342.c: Ditto.
2020-08-21According to instruction_tables.pdfliuhongt1-4/+4
1. Set cost of movement inside mask registers a bit higher than gpr's. 2. Set cost of movement between mask register and gpr much higher than movement inside gpr, but still less equal than load/store. 3. Set cost of mask register load/store a bit higher than gpr load/store. gcc/ * config/i386/x86-tune-costs.h (skylake_cost): Adjust cost model.
2020-08-21Enable direct movement between gpr and mask registers in pass_reload.liuhongt7-3/+128
Changelog gcc/ * config/i386/i386.c (inline_secondary_memory_needed): No memory is needed between mask regs and gpr. (ix86_hard_regno_mode_ok): Add condition TARGET_AVX512F for mask regno. * config/i386/i386.h (enum reg_class): Add INT_MASK_REGS. (REG_CLASS_NAMES): Ditto. (REG_CLASS_CONTENTS): Ditto. * config/i386/i386.md: Exclude mask register in define_peephole2 which is avaiable only for gpr. gcc/testsuite/ * gcc.target/i386/spill_to_mask-1.c: New tests. * gcc.target/i386/spill_to_mask-2.c: New tests. * gcc.target/i386/spill_to_mask-3.c: New tests. * gcc.target/i386/spill_to_mask-4.c: New tests.
2020-08-21x86: Add cost model for operation of mask registers.H.J. Lu3-0/+185
gcc/ PR target/71453 * config/i386/i386.h (struct processor_costs): Add member mask_to_integer, integer_to_mask, mask_load[3], mask_store[3], mask_move. * config/i386/x86-tune-costs.h (ix86_size_cost, i386_cost, i386_cost, pentium_cost, lakemont_cost, pentiumpro_cost, geode_cost, k6_cost, athlon_cost, k8_cost, amdfam10_cost, bdver_cost, znver1_cost, znver2_cost, skylake_cost, btver1_cost, btver2_cost, pentium4_cost, nocona_cost, atom_cost, slm_cost, intel_cost, generic_cost, core_cost): Initialize mask_load[3], mask_store[3], mask_move, integer_to_mask, mask_to_integer for all target costs. * config/i386/i386.c (ix86_register_move_cost): Using cost model of mask registers. (inline_memory_move_cost): Ditto. (ix86_register_move_cost): Ditto.
2020-08-20analyzer: add regression tests [PR95152]David Malcolm2-0/+17
PR analyzer/95152 reports various ICEs in region_model::get_or_create_mem_ref. I removed this function as part of the state rewrite in r11-2694-g808f4dfeb3a95f50f15e71148e5c1067f90a126d. I've verified that these two test cases reproduce the issue with 10.2 and don't ICE with trunk; adding them as regression tests. gcc/testsuite/ChangeLog: PR analyzer/95152 * gcc.dg/analyzer/pr95152-4.c: New test. * gcc.dg/analyzer/pr95152-5.c: New test.
2020-08-21Daily bump.GCC Administrator11-1/+147
2020-08-21d: Merge upstream dmd 1b5a53d01.Iain Buclaw5-11/+69
Fixes an ICE in setValue at dmd/dinterpret.c:7046 This was originally seen when running the testsuite for a 16-bit target, however, it could be reproduced on 32-bit using long[] as well. Reviewed-on: https://github.com/dlang/dmd/pull/11547 gcc/d/ChangeLog: * dmd/MERGE: Merge upstream dmd 1b5a53d01.
2020-08-20analyzer: fix infinite recursion ICE on unions [PR96723]David Malcolm3-0/+14
Attempts to store sm-state into a union in C++ triggered an infinite recursion when trying to generate a representative tree, due to erroneously trying to use the dtor of the union as a field. Fix it by filtering out non-FIELD_DECLs when walking TYPE_FIELDs in region::get_subregions_for_binding. gcc/analyzer/ChangeLog: PR analyzer/96723 * region-model-manager.cc (region_model_manager::get_field_region): Assert that field is a FIELD_DECL. * region.cc (region::get_subregions_for_binding): In union-handling, filter the TYPE_FIELDS traversal to just FIELD_DECLs. gcc/testsuite/ChangeLog: PR analyzer/96723 * g++.dg/analyzer/pr96723.C: New test.
2020-08-20libstdc++: Fix typo in ChangeLogJonathan Wakely1-1/+1
2020-08-20configure: Also check C++11 (flags) for ${build} compiler not only for ${host}Tobias Burnus3-11/+1039
config/ChangeLog: PR bootstrap/96612 * ax_cxx_compile_stdcxx.m4: Add fourth argument to check also the CXX_FOR_BUILD compiler. ChangeLog: PR bootstrap/96612 * configure.ac: Run AX_CXX_COMPILE_STDCXX also for ${build} compiler, if not the same as ${host}. * configure: Regenerate.
2020-08-20libstdc++: Make incrementable<__int128> satisfied in strict modeJonathan Wakely2-1/+38
This adds specializations of std::incrementable_traits so that 128-bit integers are always considered incrementable (and therefore usable with std::ranges::iota_view) even when they don't satisfy std::integral. libstdc++-v3/ChangeLog: * include/bits/iterator_concepts.h [__STRICT_ANSI__] (incrementable_traits<__int128>): Define specialization. (incrementable_traits<unsigned __int128>): Likewise. * testsuite/std/ranges/iota/96042.cc: Test iota_view with __int128.
2020-08-20This patch fixes PRs 96100 and 96101.Paul Thomas2-2/+44
2020-08-20 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/96100 PR fortran/96101 * trans-array.c (get_array_charlen): Tidy up the evaluation of the string length for array constructors. Avoid trailing array references. Ensure string lengths of deferred length components are set. For parentheses operator apply string length to both the primary expression and the enclosed expression. gcc/testsuite/ PR fortran/96100 PR fortran/96101 * gfortran.dg/char_length_23.f90: New test.
2020-08-20vxworks: Fix GCC selftests for *-wrs-vxworks7-* targetsIain Buclaw1-5/+11
Currently when building a cross-compiler targeting arm-wrs-vxworks7, the self-tests fail unless the VSB_DIR environment variable is set. This prevents attempts at designating the location of runtime header files, libraries or startfiles, which would fail on unset environment variables and aren't needed for such tests. gcc/ChangeLog: * config/vxworks.h (VXWORKS_ADDITIONAL_CPP_SPEC): Don't include VxWorks header files if -fself-test is used. (STARTFILE_PREFIX_SPEC): Avoid using VSB_DIR if -fself-test is used.
2020-08-20Fix obvious typo were errmsg_len was assigned to errmsg.Andre Vehreschild1-1/+1
gcc/fortran/ChangeLog: 2020-08-20 Andre Vehreschild <vehre@gcc.gnu.org> PR fortran/94958 * trans-array.c (gfc_bcast_alloc_comp): Use the correct variable.
2020-08-20arm: Require MVE memory operand for destination of vst1q intrinsicJoe Ramsay6-17/+37
Previously, the machine description patterns for vst1q accepted a generic memory operand for the destination, which could lead to an unrecognised builtin when expanding vst1q* intrinsics. This change fixes the pattern to only accept MVE memory operands. gcc/ChangeLog: PR target/96683 * config/arm/mve.md (mve_vst1q_f<mode>): Require MVE memory operand for destination. (mve_vst1q_<supf><mode>): Likewise. gcc/testsuite/ChangeLog: PR target/96683 * gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_s16.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_s8.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_u16.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_u8.c: New test.
2020-08-20libgomp: adjust nvptx_free callback context checkingChung-Lin Tang1-7/+15
Change test for CUDA callback context in nvptx_free() from using GOMP_PLUGIN_acc_thread () into checking for CUDA_ERROR_NOT_PERMITTED, for the former only works for OpenACC, but not OpenMP offloading. 2020-08-20 Chung-Lin Tang <cltang@codesourcery.com> libgomp/ * plugin/plugin-nvptx.c (nvptx_free): Change "GOMP_PLUGIN_acc_thread () == NULL" test into check of CUDA_ERROR_NOT_PERMITTED status for cuMemGetAddressRange. Adjust comments.
2020-08-20Fortran: Fix OpenMP's 'if(simd:' etc. conditionsTobias Burnus3-2/+122
gcc/fortran/ChangeLog: * openmp.c (gfc_match_omp_clauses): Re-order 'if' clause pasing to avoid creating spurious symbols. libgomp/ChangeLog: * testsuite/libgomp.fortran/lastprivate-conditional-10.f90: New test.
2020-08-20testsuite: Remove test for arm32 in arm_soft_okChristophe Lyon1-6/+4
There is no reason to check for arm32 when checking for -mfloat=abi-soft support. Instead this implies skipping some tests when targetting a thumb-1 cpu, while they pass. This patch removes the arm32 check, and uses the same skeleton as arm_softfp_ok and arm_hard_ok. 2020-08-20 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ * lib/target-supports.exp (arm_soft_ok): Remove arm32 check.
2020-08-20testsuite: Skip arm/pure-code tests for arm*-*-uclinuxfdpiceabiChristophe Lyon1-1/+7
FDPIC it uses PIC code, which is incompatible with -mpure-code, so we want to skip these tests for arm*-*-uclinuxfdpiceabi. This patch also fixes a typo where the final closing bracket was commented out. 2020-08-20 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ * gcc.target/arm/pure-code/pure-code.exp: Skip for arm*-*-uclinuxfdpiceabi. Fix missing closing bracket.
2020-08-20Fortran : rejected f0.d edit descriptor PR96436Mark Eggleston11-1/+142
Zero length f format descriptors are valid for Fortran 95 and later. For g format descriptors from Fortran 2008 and later. Finally for D, E, EN and ES for Fortran 2018 and later. 2020-08-20 Mark Eggleston <markeggleston@gcc.gnu.org> libgfortran/ PR fortran/96436 * io/format.c (parse_format_list): Add new local variable "standard" to hold the required standard to check. If the format width is zero select standard depending on descriptor. Call notification_std using the new standard variable. 2020-08-20 Mark Eggleston <markeggleston@gcc.gnu.org> gcc/testsuite/ PR fortran/96436 * gfortran.dg/pr96436_1.f90: New test. * gfortran.dg/pr96436_2.f90: New test. * gfortran.dg/pr96436_3.f90: New test. * gfortran.dg/pr96436_4.f90: New test. * gfortran.dg/pr96436_5.f90: New test. * gfortran.dg/pr96436_6.f90: New test. * gfortran.dg/pr96436_7.f90: New test. * gfortran.dg/pr96436_8.f90: New test. * gfortran.dg/pr96436_9.f90 * gfortran.dg/pr96436_10.f90
2020-08-19analyzer: fix ICE on vector comparisons [PR96713]David Malcolm2-13/+20
gcc/analyzer/ChangeLog: PR analyzer/96713 * region-model.cc (region_model::get_gassign_result): For comparisons, only use eval_condition when the lhs has boolean type, and use get_or_create_constant_svalue on the boolean constants directly rather than via get_rvalue. gcc/testsuite/ChangeLog: PR analyzer/96713 * gcc.dg/analyzer/pr96713.c: New test.
2020-08-20Daily bump.GCC Administrator6-1/+399
2020-08-19c++: Check satisfaction before non-dep convs. [CWG2369]Jason Merrill22-38/+106
It's very hard to use concepts to protect a template from hard errors due to unwanted instantiation if constraints aren't checked until after doing all substitution and checking of non-dependent conversions. It was pretty straightforward to insert the satisfaction check into the logic, but I needed to make the 3-parameter version of satisfy_declaration_constraints call push_tinst_level like the 2-parameter version already does. For simplicity, I also made it add any needed outer template arguments from the TEMPLATE_DECL to the args. The testsuite changes are mostly because this change causes unsatisfaction to cause deduction to fail rather than reject the candidate later in overload resolution. gcc/cp/ChangeLog: DR 2369 * cp-tree.h (push_tinst_level, push_tinst_level_loc): Declare. * constraint.cc (satisfy_declaration_constraints): Use add_outermost_template_args and push_tinst_level. * pt.c (add_outermost_template_args): Handle getting a TEMPLATE_DECL as the first argument. (push_tinst_level, push_tinst_level_loc): No longer static. (fn_type_unification): Check satisfaction before non-dependent conversions. gcc/testsuite/ChangeLog: DR 2369 * g++.dg/concepts/diagnostic10.C: Adjust expexcted errors. * g++.dg/concepts/diagnostic13.C: Adjust expexcted errors. * g++.dg/concepts/diagnostic2.C: Adjust expexcted errors. * g++.dg/concepts/diagnostic3.C: Adjust expexcted errors. * g++.dg/concepts/diagnostic4.C: Adjust expexcted errors. * g++.dg/concepts/diagnostic5.C: Adjust expexcted errors. * g++.dg/concepts/diagnostic9.C: Adjust expexcted errors. * g++.dg/concepts/expression2.C: Adjust expexcted errors. * g++.dg/concepts/fn5.C: Adjust expexcted errors. * g++.dg/concepts/placeholder5.C: Adjust expexcted errors. * g++.dg/concepts/pr67595.C: Adjust expexcted errors. * g++.dg/cpp2a/concepts-pr78752-2.C: Adjust expexcted errors. * g++.dg/cpp2a/concepts-pr84140.C: Adjust expexcted errors. * g++.dg/cpp2a/concepts-recursive-sat3.C: Adjust expexcted errors. * g++.dg/cpp2a/concepts-requires18.C: Adjust expexcted errors. * g++.dg/cpp2a/concepts-requires19.C: Adjust expexcted errors. * g++.dg/cpp2a/concepts3.C: Adjust expexcted errors. * g++.dg/cpp2a/concepts-nondep1.C: New test. * g++.dg/cpp2a/concepts-nondep1a.C: New test.
2020-08-19libstdc++: Make make-unsigned-like-t<__int128> work [PR 96042]Jonathan Wakely2-4/+48
As well as ensuring that numeric_limits<__int128> is defined, we need to ensure that make-unsigned-like-t and to-unsigned-like work correctly for 128-bit integers in strict mode. This ensures that a subrange created from an iota_view's iterator and sentinel can represent its size. Co-authored-by: Patrick Palka <ppalka@redhat.com> libstdc++-v3/ChangeLog: 2020-08-19 Jonathan Wakely <jwakely@redhat.com> Patrick Palka <ppalka@redhat.com> PR libstdc++/96042 * include/bits/range_access.h (__detail::__to_unsigned_like): Do not use make_unsigned_t<T> in the return type, as it can result in an error before the integral<T> constraint is checked. [__STRICT_ANSI__]: Add overloads for 128-bit integer types. (__detail::__make_unsigned_like_t): Define as the return type of __to_unsigned_like. * testsuite/std/ranges/subrange/96042.cc: New test.
2020-08-19analyzer: fix ICE on deref_rvalue on SK_COMPOUND [PR96643]David Malcolm2-21/+31
gcc/analyzer/ChangeLog: PR analyzer/96643 * region-model.cc (region_model::deref_rvalue): Rather than attempting to handle all svalue kinds in the switch, only cover the special cases, and move symbolic-region handling to after the switch, thus implicitly handling the missing case SK_COMPOUND. gcc/testsuite/ChangeLog: PR analyzer/96643 * g++.dg/analyzer/pr96643.C: New test.
2020-08-19analyzer: fix ICE on folding vector 0 [PR96705]David Malcolm2-2/+11
gcc/analyzer/ChangeLog: * region-model-manager.cc PR analyzer/96705 (region_model_manager::maybe_fold_binop): Check that we have an integral type before calling build_int_cst. gcc/testsuite/ChangeLog: PR analyzer/96705 * gcc.dg/analyzer/pr96705.c: New test.
2020-08-19analyzer: fix ICE converting float to int [PR96699]David Malcolm2-0/+18
gcc/analyzer/ChangeLog: PR analyzer/96699 * region-model-manager.cc (region_model_manager::get_or_create_cast): Use FIX_TRUNC_EXPR for casting from REAL_TYPE to INTEGER_TYPE. gcc/testsuite/ChangeLog: PR analyzer/96699 * gcc.dg/analyzer/pr96699.c: New test.
2020-08-19rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro ↵Carl Love3-322/+347
definitions. gcc/ChangeLog 2020-08-19 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-builtin.def (BU_P10V_0, BU_P10V_1, BU_P10V_2, BU_P10V_3): Rename BU_P10V_VSX_0, BU_P10V_VSX_1, BU_P10V_VSX_2, BU_P10V_VSX_3 respectively. (BU_P10V_4): Remove. (BU_P10V_AV_0, BU_P10V_AV_1, BU_P10V_AV_2, BU_P10V_AV_3, BU_P10V_AV_4): New definitions for Power 10 Altivec macros. (VSTRIBR, VSTRIHR, VSTRIBL, VSTRIHL, VSTRIBR_P, VSTRIHR_P, VSTRIBL_P, VSTRIHL_P, MTVSRBM, MTVSRHM, MTVSRWM, MTVSRDM, MTVSRQM, VEXPANDMB, VEXPANDMH, VEXPANDMW, VEXPANDMD, VEXPANDMQ, VEXTRACTMB, VEXTRACTMH, VEXTRACTMW, VEXTRACTMD, VEXTRACTMQ): Replace macro expansion BU_P10V_1 with BU_P10V_AV_1. (VCLRLB, VCLRRB, VCFUGED, VCLZDM, VCTZDM, VPDEPD, VPEXTD, VGNB, VCNTMBB, VCNTMBH, VCNTMBW, VCNTMBD): Replace macro expansion BU_P10V_2 with BU_P10V_AV_2. (VEXTRACTBL, VEXTRACTHL, VEXTRACTWL, VEXTRACTDL, VEXTRACTBR, VEXTRACTHR, VEXTRACTWR, VEXTRACTDR, VINSERTGPRBL, VINSERTGPRHL, VINSERTGPRWL, VINSERTGPRDL, VINSERTVPRBL, VINSERTVPRHL, VINSERTVPRWL, VINSERTGPRBR, VINSERTGPRHR, VINSERTGPRWR, VINSERTGPRDR, VINSERTVPRBR, VINSERTVPRHR, VINSERTVPRWR, VREPLACE_ELT_V4SI, VREPLACE_ELT_UV4SI, VREPLACE_ELT_V2DF, VREPLACE_ELT_V4SF, VREPLACE_ELT_V2DI, VREPLACE_ELT_UV2DI, VREPLACE_UN_V4SI, VREPLACE_UN_UV4SI, VREPLACE_UN_V4SF, VREPLACE_UN_V2DI, VREPLACE_UN_UV2DI, VREPLACE_UN_V2DF, VSLDB_V16QI, VSLDB_V8HI, VSLDB_V4SI, VSLDB_V2DI, VSRDB_V16QI, VSRDB_V8HI, VSRDB_V4SI, VSRDB_V2DI): Replace macro expansion BU_P10V_3 with BU_P10V_AV_3. (VXXSPLTIW_V4SI, VXXSPLTIW_V4SF, VXXSPLTID): Replace macro expansion BU_P10V_1 with BU_P10V_AV_1. (XXGENPCVM_V16QI, XXGENPCVM_V8HI, XXGENPCVM_V4SI, XXGENPCVM_V2DI): Replace macro expansion BU_P10V_2 with BU_P10V_VSX_2. (VXXSPLTI32DX_V4SI, VXXSPLTI32DX_V4SF, VXXBLEND_V16QI, VXXBLEND_V8HI, VXXBLEND_V4SI, VXXBLEND_V2DI, VXXBLEND_V4SF, VXXBLEND_V2DF): Replace macor expansion BU_P10V_3 with BU_P10V_VSX_3. (XXEVAL, VXXPERMX): Replace macro expansion BU_P10V_4 with BU_P10V_VSX_4. (XVCVBF16SP, XVCVSPBF16): Replace macro expansion BU_VSX_1 with BU_P10V_VSX_1. Also change MISC to CONST. * config/rs6000/rs6000-c.c: (P10_BUILTIN_VXXPERMX): Replace with P10V_BUILTIN_VXXPERMX. (P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRRB, P10_BUILTIN_VGNB, P10_BUILTIN_XXEVAL, P10_BUILTIN_VXXPERMX, P10_BUILTIN_VEXTRACTBL, P10_BUILTIN_VEXTRACTHL, P10_BUILTIN_VEXTRACTWL, P10_BUILTIN_VEXTRACTDL, P10_BUILTIN_VINSERTGPRHL, P10_BUILTIN_VINSERTGPRWL, P10_BUILTIN_VINSERTGPRDL, P10_BUILTIN_VINSERTVPRBL, P10_BUILTIN_VINSERTVPRHL, P10_BUILTIN_VEXTRACTBR, P10_BUILTIN_VEXTRACTHR, P10_BUILTIN_VEXTRACTWR, P10_BUILTIN_VEXTRACTDR, P10_BUILTIN_VINSERTGPRBR, P10_BUILTIN_VINSERTGPRHR, P10_BUILTIN_VINSERTGPRWR, P10_BUILTIN_VINSERTGPRDR, P10_BUILTIN_VINSERTVPRBR, P10_BUILTIN_VINSERTVPRHR, P10_BUILTIN_VINSERTVPRWR, P10_BUILTIN_VREPLACE_ELT_UV4SI, P10_BUILTIN_VREPLACE_ELT_V4SI, P10_BUILTIN_VREPLACE_ELT_UV2DI, P10_BUILTIN_VREPLACE_ELT_V2DI, P10_BUILTIN_VREPLACE_ELT_V2DF, P10_BUILTIN_VREPLACE_UN_UV4SI, P10_BUILTIN_VREPLACE_UN_V4SI, P10_BUILTIN_VREPLACE_UN_V4SF, P10_BUILTIN_VREPLACE_UN_UV2DI, P10_BUILTIN_VREPLACE_UN_V2DI, P10_BUILTIN_VREPLACE_UN_V2DF, P10_BUILTIN_VSLDB_V16QI, P10_BUILTIN_VSLDB_V16QI, P10_BUILTIN_VSLDB_V8HI, P10_BUILTIN_VSLDB_V4SI, P10_BUILTIN_VSLDB_V2DI, P10_BUILTIN_VXXSPLTIW_V4SI, P10_BUILTIN_VXXSPLTIW_V4SF, P10_BUILTIN_VXXSPLTID, P10_BUILTIN_VXXSPLTI32DX_V4SI, P10_BUILTIN_VXXSPLTI32DX_V4SF, P10_BUILTIN_VXXBLEND_V16QI, P10_BUILTIN_VXXBLEND_V8HI, P10_BUILTIN_VXXBLEND_V4SI, P10_BUILTIN_VXXBLEND_V2DI, P10_BUILTIN_VXXBLEND_V4SF, P10_BUILTIN_VXXBLEND_V2DF, P10_BUILTIN_VSRDB_V16QI, P10_BUILTIN_VSRDB_V8HI, P10_BUILTIN_VSRDB_V4SI, P10_BUILTIN_VSRDB_V2DI, P10_BUILTIN_VSTRIBL, P10_BUILTIN_VSTRIHL, P10_BUILTIN_VSTRIBL_P, P10_BUILTIN_VSTRIHL_P, P10_BUILTIN_VSTRIBR, P10_BUILTIN_VSTRIHR, P10_BUILTIN_VSTRIBR_P, P10_BUILTIN_VSTRIHR_P, P10_BUILTIN_MTVSRBM, P10_BUILTIN_MTVSRHM, P10_BUILTIN_MTVSRWM, P10_BUILTIN_MTVSRDM, P10_BUILTIN_MTVSRQM, P10_BUILTIN_VCNTMBB, P10_BUILTIN_VCNTMBH, P10_BUILTIN_VCNTMBW, P10_BUILTIN_VCNTMBD, P10_BUILTIN_VEXPANDMB, P10_BUILTIN_VEXPANDMH, P10_BUILTIN_VEXPANDMW, P10_BUILTIN_VEXPANDMD, P10_BUILTIN_VEXPANDMQ, P10_BUILTIN_VEXTRACTMB, P10_BUILTIN_VEXTRACTMH, P10_BUILTIN_VEXTRACTMW, P10_BUILTIN_VEXTRACTMD, P10_BUILTIN_VEXTRACTMQ, P10_BUILTIN_XVTLSBB_ZEROS, P10_BUILTIN_XVTLSBB_ONES): Replace with P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRRB, P10V_BUILTIN_VGNB, P10V_BUILTIN_XXEVAL, P10V_BUILTIN_VXXPERMX, P10V_BUILTIN_VEXTRACTBL, P10V_BUILTIN_VEXTRACTHL, P10V_BUILTIN_VEXTRACTWL, P10V_BUILTIN_VEXTRACTDL, P10V_BUILTIN_VINSERTGPRHL, P10V_BUILTIN_VINSERTGPRWL, P10V_BUILTIN_VINSERTGPRDL, P10V_BUILTIN_VINSERTVPRBL,P10V_BUILTIN_VINSERTVPRHL, P10V_BUILTIN_VEXTRACTBR, P10V_BUILTIN_VEXTRACTHR P10V_BUILTIN_VEXTRACTWR, P10V_BUILTIN_VEXTRACTDR, P10V_BUILTIN_VINSERTGPRBR, P10V_BUILTIN_VINSERTGPRHR, P10V_BUILTIN_VINSERTGPRWR, P10V_BUILTIN_VINSERTGPRDR, P10V_BUILTIN_VINSERTVPRBR, P10V_BUILTIN_VINSERTVPRHR, P10V_BUILTIN_VINSERTVPRWR, P10V_BUILTIN_VREPLACE_ELT_UV4SI, P10V_BUILTIN_VREPLACE_ELT_V4SI, P10V_BUILTIN_VREPLACE_ELT_UV2DI, P10V_BUILTIN_VREPLACE_ELT_V2DI, P10V_BUILTIN_VREPLACE_ELT_V2DF, P10V_BUILTIN_VREPLACE_UN_UV4SI, P10V_BUILTIN_VREPLACE_UN_V4SI, P10V_BUILTIN_VREPLACE_UN_V4SF, P10V_BUILTIN_VREPLACE_UN_UV2DI, P10V_BUILTIN_VREPLACE_UN_V2DI, P10V_BUILTIN_VREPLACE_UN_V2DF, P10V_BUILTIN_VSLDB_V16QI, P10V_BUILTIN_VSLDB_V16QI, P10V_BUILTIN_VSLDB_V8HI, P10V_BUILTIN_VSLDB_V4SI, P10V_BUILTIN_VSLDB_V2DI, P10V_BUILTIN_VXXSPLTIW_V4SI, P10V_BUILTIN_VXXSPLTIW_V4SF, P10V_BUILTIN_VXXSPLTID, P10V_BUILTIN_VXXSPLTI32DX_V4SI, P10V_BUILTIN_VXXSPLTI32DX_V4SF, P10V_BUILTIN_VXXBLEND_V16QI, P10V_BUILTIN_VXXBLEND_V8HI, P10V_BUILTIN_VXXBLEND_V4SI, P10V_BUILTIN_VXXBLEND_V2DI, P10V_BUILTIN_VXXBLEND_V4SF, P10V_BUILTIN_VXXBLEND_V2DF, P10V_BUILTIN_VSRDB_V16QI, P10V_BUILTIN_VSRDB_V8HI, P10V_BUILTIN_VSRDB_V4SI, P10V_BUILTIN_VSRDB_V2DI, P10V_BUILTIN_VSTRIBL, P10V_BUILTIN_VSTRIHL, P10V_BUILTIN_VSTRIBL_P, P10V_BUILTIN_VSTRIHL_P, P10V_BUILTIN_VSTRIBR, P10V_BUILTIN_VSTRIHR, P10V_BUILTIN_VSTRIBR_P, P10V_BUILTIN_VSTRIHR_P, P10V_BUILTIN_MTVSRBM, P10V_BUILTIN_MTVSRHM, P10V_BUILTIN_MTVSRWM, P10V_BUILTIN_MTVSRDM, P10V_BUILTIN_MTVSRQM, P10V_BUILTIN_VCNTMBB, P10V_BUILTIN_VCNTMBH, P10V_BUILTIN_VCNTMBW, P10V_BUILTIN_VCNTMBD, P10V_BUILTIN_VEXPANDMB, P10V_BUILTIN_VEXPANDMH, P10V_BUILTIN_VEXPANDMW, P10V_BUILTIN_VEXPANDMD, P10V_BUILTIN_VEXPANDMQ, P10V_BUILTIN_VEXTRACTMB, P10V_BUILTIN_VEXTRACTMH, P10V_BUILTIN_VEXTRACTMW, P10V_BUILTIN_VEXTRACTMD, P10V_BUILTIN_VEXTRACTMQ, P10V_BUILTIN_XVTLSBB_ZEROS, P10V_BUILTIN_XVTLSBB_ONES respectively. * config/rs6000/rs6000-call.c: Ditto above, change P10_BUILTIN_name to P10V_BUILTIN_name. (P10_BUILTIN_XVCVSPBF16, P10_BUILTIN_XVCVBF16SP): Change to P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SP respectively.
2020-08-19rs6000: Enable more sibcalls when TOC is not preservedBill Schmidt2-21/+28
A function compiled with the PC-relative addressing model does not require r2 to contain a TOC pointer, and does not guarantee that r2 will be preserved for its caller. Such a function can make sibcalls without restriction based on TOC preservation rules. However, a caller that does preserve r2 cannot make a sibcall to a callee that does not. 2020-08-19 Bill Schmidt <wschmidt@linux.ibm.com> gcc/ * config/rs6000/rs6000-logue.c (rs6000_decl_ok_for_sibcall): Sibcalls are always legal when the caller doesn't preserve r2. gcc/testsuite/ * gcc.target/powerpc/pcrel-sibcall-1.c: Adjust.
2020-08-19libstdc++: Remove deprecated comparison operators for RB treesJonathan Wakely1-16/+0
These functions were deprecated in GCC 9.1.0 because they are never used by the library. This patch removes them for GCC 11. libstdc++-v3/ChangeLog: * include/bits/stl_tree.h (operator!=, operator>, operator<=) (operator>=): Remove deprecated functions.
2020-08-19libstdc++: Make __int128 meet integer-class requirements [PR 96042]Jonathan Wakely3-5/+62
Because __int128 can be used as the difference type for iota_view, we need to ensure that it meets the requirements of an integer-class type. The requirements in [iterator.concept.winc] p10 include numeric_limits being specialized and giving meaningful answers. Currently we only specialize numeric_limits for non-standard integer types in non-strict modes. However, nothing prevents us from defining an explicit specialization for any implementation-defined type, so it doesn't matter whether std::is_integral<__int128> is true or not. This patch ensures that the numeric_limits specializations for signed and unsigned __int128 are defined whenever __int128 is available. It also makes the __numeric_traits and __int_limits helpers work for __int128, via a new __gnu_cxx::__is_integer_nonstrict trait. libstdc++-v3/ChangeLog: PR libstdc++/96042 * include/ext/numeric_traits.h (__is_integer_nonstrict): New trait which is true for 128-bit integers even in strict modes. (__numeric_traits_integer, __numeric_traits): Use __is_integer_nonstrict instead of __is_integer. * include/std/limits [__STRICT_ANSI__ && __SIZEOF_INT128__] (numeric_limits<__int128>, (numeric_limits<unsigned __int128>): Define. * testsuite/std/ranges/iota/96042.cc: New test.
2020-08-19i386: Use code_for_ instead of gen_ for parameterized names more.Uros Bizjak1-17/+19
Some builtins are better expanded to patterns with parametrized names via code_for_ than gen_ helpers. No functional changes. 2020-08-19 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: * config/i386/i386-expand.c (ix86_expand_builtin) [case IX86_BUILTIN_ENQCMD, case IX86_BUILTIN_ENQCMDS]: Rewrite expansion to use code_for_enqcmd. [case IX86_BUILTIN_WRSSD, case IX86_BUILTIN_WRSSQ]: Rewrite expansion to use code_for_wrss. [case IX86_BUILTIN_WRUSSD, case IX86_BUILTIN_WRUSSD]: Rewrite expansion to use code_for_wrss.
2020-08-19tree-optimization/94234 - add pattern for ptr-diff on addresses with same offsetFeng Xue2-0/+18
2020-08-19 Feng Xue <fxue@os.amperecomputing.com> gcc/ PR tree-optimization/94234 * match.pd ((PTR_A + OFF) - (PTR_B + OFF)) -> (PTR_A - PTR_B): New simplification. gcc/testsuite/ PR tree-optimization/94234 * gcc.dg/pr94234-1.c: New test.
2020-08-19libstdc++: Mention new macros in commentsJonathan Wakely1-0/+5
libstdc++-v3/ChangeLog: * include/bits/c++config (_GLIBCXX_DEPRECATED_SUGGEST) (_GLIBCXX11_DEPRECATED, _GLIBCXX11_DEPRECATED_SUGGEST) (_GLIBCXX17_DEPRECATED_SUGGEST, _GLIBCXX20_DEPRECATED_SUGGEST): Add new macros to comment.
2020-08-19libstdc++: integer-class types as per [iterator.concept.winc]Patrick Palka7-4/+1219
This implements signed and unsigned integer-class types, whose width is one bit larger than the widest supported signed and unsigned integral type respectively. In our case this is either __int128 and unsigned __int128, or long long and unsigned long long. Internally, the two integer-class types are represented as a largest supported unsigned integral type plus one extra bit. The signed integer-class type is represented in two's complement form with the extra bit acting as the sign bit. libstdc++-v3/ChangeLog: * include/Makefile.am (bits_headers): Add new header <bits/max_size_type.h>. * include/Makefile.in: Regenerate. * include/bits/iterator_concepts.h (ranges::__detail::__max_diff_type): Remove definition, replace with forward declaration of class __max_diff_type. (__detail::__max_size_type): Remove definition, replace with forward declaration of class __max_size_type. (__detail::__is_unsigned_int128, __is_signed_int128) (__is_int128): New concepts. (__detail::__is_integer_like): Accept __int128 and unsigned __int128. (__detail::__is_signed_integer_like): Accept __int128. * include/bits/max_size_type.h: New header. * include/bits/range_access.h: Include <bits/max_size_type.h>. (__detail::__to_unsigned_like): Two new overloads. * testsuite/std/ranges/iota/difference_type.cc: New test. * testsuite/std/ranges/iota/max_size_type.cc: New test.
2020-08-19x86: Detect Rocket Lake and Alder LakeH.J. Lu1-0/+10
From arch/x86/include/asm/intel-family.h on Linux kernel master branch: #define INTEL_FAM6_ROCKETLAKE 0xA7 #define INTEL_FAM6_ALDERLAKE 0x97 * common/config/i386/cpuinfo.h (get_intel_cpu): Detect Rocket Lake and Alder Lake.
2020-08-19libstdc++: Add deprecated attributes to old iostream membersJonathan Wakely7-18/+45
Back in 2017 I removed these prehistoric members (which were deprecated since C++98) for C++17 mode. But I didn't add deprecated attributes to most of them, so users didn't get any warning they would be going away. Apparently some poor souls do actually use some of these names, and so now that GCC 11 defaults to -std=gnu++17 some code has stopped compiling. This adds deprecated attributes to them, so that C++98/03/11/14 code will get a warning if it uses them. I'll also backport this to the release branches so that users can find out about the deprecation before they start using C++17. In order to give deprecated warnings even in C++98 mode this patch makes _GLIBCXX_DEPRECATED work even for C++98, adds _GLIBCXX11_DEPRECATED for the old meaning of _GLIBCXX_DEPRECATED, and adds new macros such as _GLIBCXX_DEPRECATED_SUGGEST for suggesting alternatives to deprecated features. libstdc++-v3/ChangeLog: * include/bits/c++config (_GLIBCXX_DEPRECATED): Define for all standard modes. (_GLIBCXX_DEPRECATED_SUGGEST): New macro for "use 'foo' instead" message in deprecated warnings. (_GLIBCXX11_DEPRECATED, _GLIBCXX11_DEPRECATED_SUGGEST): New macros for marking features derpecated in C++11. (_GLIBCXX17_DEPRECATED_SUGGEST, _GLIBCXX20_DEPRECATED_SUGGEST): New macros. * include/backward/auto_ptr.h (auto_ptr_ref, auto_ptr<void>): Use _GLIBCXX11_DEPRECATED instead of _GLIBCXX_DEPRECATED. (auto_ptr): Use _GLIBCXX11_DEPRECATED_SUGGEST. * include/backward/binders.h (binder1st, binder2nd): Likewise. * include/bits/ios_base.h (io_state, open_mode, seek_dir) (streampos, streamoff): Use _GLIBCXX_DEPRECATED_SUGGEST. * include/std/streambuf (stossc): Replace C++11 attribute with _GLIBCXX_DEPRECATED_SUGGEST. * include/std/type_traits (__is_nullptr_t): Use _GLIBCXX_DEPRECATED_SUGGEST instead of _GLIBCXX_DEPRECATED. * testsuite/27_io/types/1.cc: Check for deprecated warnings. Also check for io_state, open_mode and seek_dir typedefs.
2020-08-19libstdc++: assert that type traits are not misused with incomplete types [PR ↵Antony Polukhin6-4/+174
71579] libstdc++-v3/ChangeLog: 2020-08-19 Antony Polukhin <antoshkka@gmail.com> PR libstdc++/71579 * include/std/type_traits (invoke_result, is_nothrow_invocable_r) Add static_asserts to make sure that the argument of the type trait is not misused with incomplete types. (is_swappable_with, is_nothrow_swappable_with): Add static_asserts to make sure that the first and second arguments of the type trait are not misused with incomplete types. * testsuite/20_util/invoke_result/incomplete_neg.cc: New test. * testsuite/20_util/is_nothrow_invocable/incomplete_neg.cc: New test. * testsuite/20_util/is_nothrow_swappable/incomplete_neg.cc: New test. * testsuite/20_util/is_nothrow_swappable_with/incomplete_neg.cc: New test. * testsuite/20_util/is_swappable_with/incomplete_neg.cc: New test.
2020-08-19AArch64: Remove "fndecl && TREE_PUBLIC (fndecl)" in aarch64_init_cumulative_argsPeixin Qiao2-1/+11
This check will prevent the function type check of static funtion or calling via a funtion pointer. The function type should be checked no matter if the function has external linkage. gcc/ChangeLog: * config/aarch64/aarch64.c (aarch64_init_cumulative_args): Remove "fndecl && TREE_PUBLIC (fndecl)" check since it prevents the funtion type check when calling via a function pointer or when calling a static function. gcc/testsuite/ChangeLog: * gcc.target/aarch64/mgeneral-regs_7.c: New test.
2020-08-19testsuite: require c99 runtime for trigonometric optimisation testsPat Bernardi3-1/+4
A number of optimisation that simplify trigonometric expressions are only performed when the compiler knows the target has a C99 libm available. Since targets like *-elf may not have such a libm, a C99 runtime requirement is added to these tests. 2020-08-19 Pat Bernardi <bernardi@adacore.com> gcc/testsuite/ChangeLog * gcc.dg/sinatan-2.c: Add dg-require-effective-target c99_runtime. * gcc.dg/sinhovercosh-1.c: Likewise. * gcc.dg/tanhbysinh.c: Likewise.
2020-08-19[testsuite, nvptx] Add effective target sync_int_long_stackTom de Vries2-2/+14
The nvptx target currently doesn't support effective target sync_int_long, although it has support for 32-bit and 64-bit atomic. When enabling sync_int_long for nvptx, we run into a failure in gcc.dg/pr86314.c: ... nvptx-run: error getting kernel result: operation not supported on \ global/shared address space ... due to a ptx restriction: accesses to local memory are illegal, and the test-case does an atomic operation on a stack address, which is mapped to local memory. Fix this by adding a target sync_int_long_stack, wich returns false for nvptx, which can be used to mark test-cases that require sync_int_long support for stack addresses. Build on nvptx and tested with make check-gcc. gcc/testsuite/ChangeLog: PR target/96494 * lib/target-supports.exp (check_effective_target_sync_int_long): Return 1 for nvptx. (check_effective_target_sync_int_long_stack): New proc. * gcc.dg/pr86314.c: Require effective target sync_int_long_stack.
2020-08-18options: Make --help= see overridden valuesKewen Lin1-2/+8
Options "-Q --help=params" don't show the final values after target option overriding, instead it emits the default values in params.opt (without any explicit param settings). This patch makes it see overridden values. gcc/ChangeLog: * opts-global.c (decode_options): Call target_option_override_hook before it prints for --help=*.
2020-08-18analyzer: consider initializers for globals [PR96651]David Malcolm7-29/+224
PR analyzer/96651 reports a false positive in which a global that can't have been touched yet is checked in "main". The analyzer fails to reject code paths in which the initial value of the global makes the path condition impossible. This patch detects cases where the code path begins at the entrypoint of "main", and extracts values from initializers for globals that can't have been touched yet, rather than using a symbolic "INIT_VAL(REG)", fixing the false positive. gcc/analyzer/ChangeLog: PR analyzer/96651 * region-model.cc (region_model::called_from_main_p): New. (region_model::get_store_value): Move handling for globals into... (region_model::get_initial_value_for_global): ...this new function, and add logic for extracting values from decl initializers. * region-model.h (decl_region::get_svalue_for_constructor): New decl. (decl_region::get_svalue_for_initializer): New decl. (region_model::called_from_main_p): New decl. (region_model::get_initial_value_for_global): New. * region.cc (decl_region::maybe_get_constant_value): Move logic for getting an svalue from a CONSTRUCTOR node to... (decl_region::get_svalue_for_constructor): ...this new function. (decl_region::get_svalue_for_initializer): New. * store.cc (get_svalue_for_ctor_val): Rewrite in terms of region_model::get_rvalue. * store.h (binding_cluster::get_map): New accessor. gcc/testsuite/ChangeLog: PR analyzer/96651 * gcc.dg/analyzer/pr96651-1.c: New test. * gcc.dg/analyzer/pr96651-2.c: New test.
2020-08-18analyzer: fix ICE with negative bit offsets [PR96648]David Malcolm2-1/+38
PR analyzer/96648 reports an ICE within get_field_at_bit_offset due to a negative bit offset, arising due to pointer arithmetic. This patch replaces an assertion with handling for this case, fixing the ICE. gcc/analyzer/ChangeLog: PR analyzer/96648 * region.cc (get_field_at_bit_offset): Gracefully handle negative values for bit_offset. gcc/testsuite/ChangeLog: PR analyzer/96648 * gcc.dg/analyzer/pr96648.c: New test.
2020-08-19Daily bump.GCC Administrator9-1/+245
2020-08-18c++: alias template template_info settingNathan Sidwell2-8/+25
During the construction of alias templates we can alter its template_info. This is really weird, because that's morally immutable data. In this case it's ok, but let's not create a duplicate template_info, and add asserts to make sure it is changing in exactly the way we expect. gcc/cp/ * cp-tree.h (SET_TYPE_TEMPLTE_INFO): Do not deal with ALIAS templates. * pt.c (lookup_template_class_1): Special-case alias template template_info setting.
2020-08-18rs6000: Rename instruction xvcvbf16sp to xvcvbf16spnPeter Bergner5-8/+8
The xvcvbf16sp mnemonic, which was just added in ISA 3.1 has been renamed to xvcvbf16spn, to make it consistent with the other non-signaling conversion instructions which all end with "n". The only use of this instruction is in an MMA conversion built-in function, so there is little to no compatibility issue. gcc/ * config/rs6000/rs6000-builtin.def (BU_VSX_1): Rename xvcvbf16sp to xvcvbf16spn. * config/rs6000/rs6000-call.c (builtin_function_type): Likewise. * config/rs6000/vsx.md: Likewise. * doc/extend.texi: Likewise. gcc/testsuite/ * gcc.target/powerpc/mma-builtin-3.c: Rename xvcvbf16sp to xvcvbf16spn.
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