Age | Commit message (Collapse) | Author | Files | Lines |
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From-SVN: r259404
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From-SVN: r259376
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Rewrite size_must_be_zero_p with irange infrastructure. Previous
implementation did not get the bits in [7fff,ffff]. This fixes a
handful of regressions.
From-SVN: r259370
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From-SVN: r259365
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From-SVN: r259332
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From-SVN: r259304
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From-SVN: r259236
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otherwise we can never be sure of the required range type of the folded exprression
From-SVN: r259173
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From-SVN: r259172
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From-SVN: r259171
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From-SVN: r259084
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From-SVN: r259076
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disable with -fno-rvrp
From-SVN: r259033
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From-SVN: r259017
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From-SVN: r258999
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From-SVN: r258990
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From-SVN: r258817
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This merge has not been tested apart from building c/c++ with
--disable-bootstrap.
get_nonzero_bits_as_range() needs to be looked at.
From-SVN: r258769
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* constexpr.c (cxx_eval_bare_aggregate): Update constructor's flags
even when we replace an element.
* g++.dg/cpp0x/nsdmi14.C: New test.
* g++.dg/cpp1y/nsdmi-aggr10.C: New test.
From-SVN: r258703
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2018-03-21 Chenghua Xu <paul.hua.gm@gmail.com>
* gcc.dg/vect/vect-strided-shift-1.c: Add dg-skip-if for
MIPS with -mpaired-single directives.
From-SVN: r258702
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2018-03-20 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/85001
* interface.c (symbol_rank): Remove bogus null pointer check that
crept in when translating a ternary operator into an if-else
constructor.
2018-03-20 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/85001
* gfortran.dg/interface_41.f90: New test.
From-SVN: r258698
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From-SVN: r258697
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PR target/84838
* Minor grammar fixes for x86 options.
From-SVN: r258694
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2018-03-20 François Dumont <fdumont@gcc.gnu.org>
PR libstdc++/84998
* include/bits/stl_bvector.h: Fix std::hash friend declaration.
* include/std/bitset: Likewise.
* include/bits/stl_map.h (std::map<>): Fix _Rb_tree_merge_helper friend
declaration.
* include/bits/stl_multimap.h (std::multimap<>): Likewise.
* include/bits/stl_multiset.h (std::multiset<>): Likewise.
* include/bits/stl_set.h (std::set<>): Likewise.
* include/bits/unordered_map.h (std::unordered_map<>): Fix
_Hash_merge_helper friend declaration.
(std::unordered_multimap<>): Likewise.
* include/bits/unordered_set.h (std::unordered_set<>): Likewise.
(std::unordered_multiset<>): Likewise.
From-SVN: r258693
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s390x)
PR debug/84875
* dce.c (delete_unmarked_insns): Don't remove frame related noop moves
holding REG_CFA_RESTORE notes, instead turn them into a USE.
* gcc.dg/pr84875.c: New test.
From-SVN: r258692
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PR c++/84927
* constexpr.c (cxx_eval_bare_aggregate): Update constructor's flags
as we evaluate the elements.
(cxx_eval_constant_expression): Verify constructor's flags
unconditionally.
* g++.dg/cpp1y/nsdmi-aggr9.C: New test.
From-SVN: r258691
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From-SVN: r258690
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* cvt.c (cp_get_fndecl_from_callee): Add fold parameter.
(cp_get_callee_fndecl_nofold): New.
* cp-gimplify.c (cp_genericize_r): Use it instead.
* call.c (check_self_delegation): Likewise.
From-SVN: r258689
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PR target/83789
* config/rs6000/altivec.md (altivec_lvx_<mode>_2op): Delete define_insn.
(altivec_lvx_<mode>_1op): Likewise.
(altivec_stvx_<mode>_2op): Likewise.
(altivec_stvx_<mode>_1op): Likewise.
(altivec_lvx_<VM2:mode>): New define_expand.
(altivec_stvx_<VM2:mode>): Likewise.
(altivec_lvx_<VM2:mode>_2op_<P:mptrsize>): New define_insn.
(altivec_lvx_<VM2:mode>_1op_<P:mptrsize>): Likewise.
(altivec_stvx_<VM2:mode>_2op_<P:mptrsize>): Likewise.
(altivec_stvx_<VM2:mode>_1op_<P:mptrsize>): Likewise.
* config/rs6000/rs6000-p8swap.c (rs6000_gen_stvx): Use new expanders.
(rs6000_gen_lvx): Likewise.
* config/rs6000/rs6000.c (altivec_expand_lv_builtin): Likewise.
(altivec_expand_stv_builtin): Likewise.
(altivec_expand_builtin): Likewise.
* config/rs6000/vector.md: Likewise.
From-SVN: r258688
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It is tricky to get right. Aarch64 does it by adding the appropriate lane-swapping
operations during expansion.
I'd like to do the same on arm eventually, but we'd need to port and validate the VTBL-generating
code and add it to all the right places and I'm not comfortable enough doing it for GCC 8, but I am keen
in getting the wrong-code fixed.
As I say in the PR, vectorisation on armeb is already severely restricted (we disable many patterns on BYTES_BIG_ENDIAN)
and the load/store_lanes patterns really were not working properly at all, so disabling them is not
a radical approach.
The way to do that is to return false in ARRAY_MODE_SUPPORTED_P for BYTES_BIG_ENDIAN.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Also tested on armeb-none-eabi.
PR target/82518
* config/arm/arm.c (arm_array_mode_supported_p): Return false for
BYTES_BIG_ENDIAN.
* lib/target-supports.exp (check_effective_target_vect_load_lanes):
Disable for armeb targets.
* gcc.target/arm/pr82518.c: New test.
From-SVN: r258687
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https://gcc.gnu.org/ml/gcc-patches/2018-03/msg00961.html
PR c++/84962
* name-lookup.c (pushdecl_class_level): Push anon-struct's
member_vec, if there is one.
PR c++/84962
* g++.dg/lookup/pr84962.C: New.
From-SVN: r258686
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https://gcc.gnu.org/ml/gcc-patches/2018-03/msg00973.html
PR c++/84970
* cp-tree.h (lookup_list_keep): Declare.
* tree.c (lookup_list_keep): New, broken out of ...
(build_min): ... here. Call it.
* decl.c (cp_finish_decl): Call lookup_list_keep.
PR c++/84970
* g++.dg/lookup/pr84970.C: New.
From-SVN: r258685
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2018-03-20 Richard Biener <rguenther@suse.de>
PR target/84986
* config/i386/i386.c (ix86_add_stmt_cost): Only cost
sign-conversions as zero, fall back to standard scalar_stmt
cost for the rest.
* gcc.dg/vect/costmodel/x86_64/costmodel-pr84986.c: New testcase.
From-SVN: r258684
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2018-03-20 Martin Liska <mliska@suse.cz>
PR ipa/84825
* predict.c (rebuild_frequencies): Handle case when we have
PROFILE_ABSENT, but flag_guess_branch_prob is false.
2018-03-20 Martin Liska <mliska@suse.cz>
PR ipa/84825
* g++.dg/ipa/pr84825.C: New test.
From-SVN: r258683
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2018-03-20 Martin Liska <mliska@suse.cz>
* gcc.dg/lto/chkp-ctor-merge_0.c: Remove.
From-SVN: r258682
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PR target/84990
* dwarf2asm.c (dw2_output_indirect_constant_1): Temporarily turn off
flag_section_anchors.
* varasm.c (use_blocks_for_decl_p): Remove hack for
dw2_force_const_mem.
From-SVN: r258681
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* pt.c (rewrite_template_parm): Fix auto handling.
From-SVN: r258680
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2018-03-20 Richard Biener <rguenther@suse.de>
* testsuite/libgomp.graphite/force-parallel-4.c: XFAIL one
parallelizable loop.
From-SVN: r258679
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insn at -O2 and above at aarch64)
PR target/84845
* config/aarch64/aarch64.md (*aarch64_reg_<mode>3_neg_mask2): Rename
to ...
(*aarch64_<optab>_reg_<mode>3_neg_mask2): ... this. If pseudos can't
be created, use lowpart_subreg of operands[0] rather than operands[0]
itself.
(*aarch64_reg_<mode>3_minus_mask): Rename to ...
(*aarch64_ashl_reg_<mode>3_minus_mask): ... this.
(*aarch64_<optab>_reg_di3_mask2): Use const_int_operand predicate
and n constraint instead of aarch64_shift_imm_di and Usd.
(*aarch64_reg_<optab>_minus<mode>3): Rename to ...
(*aarch64_<optab>_reg_minus<mode>3): ... this.
* gcc.c-torture/compile/pr84845.c: New test.
From-SVN: r258678
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This patch fixes PR82989 so that we avoid NEON instructions when
-mneon-for-64bits is not enabled. This is more of a short term fix
for the real deeper problem of making an early decision of choosing
or rejecting NEON instructions. There is now a new ticket PR84467 to
deal with the longer term solution.
(Please refer to the discussion in the bug report for more details).
Sudi
*** gcc/ChangeLog ***
2018-03-20 Sudakshina Das <sudi.das@arm.com>
PR target/82989
* config/arm/neon.md (ashldi3_neon): Update ?s for constraints
to favor GPR over NEON registers.
(<shift>di3_neon): Likewise.
*** gcc/testsuite/ChangeLog ***
2018-03-20 Sudakshina Das <sudi.das@arm.com>
PR target/82989
* gcc.target/arm/pr82989.c: New test.
From-SVN: r258677
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2018-03-20 Tom de Vries <tom@codesourcery.com>
PR target/84952
* config/nvptx/nvptx.c (nvptx_single): Don't neuter bar.sync.
(nvptx_process_pars): Emit bar.sync asap and alap.
From-SVN: r258676
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From-SVN: r258675
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2018-03-20 Tom de Vries <tom@codesourcery.com>
PR target/84954
* config/nvptx/nvptx.c (prevent_branch_around_nothing): Also update
seen_label if seen_label is already set.
From-SVN: r258674
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shift exponent 32 is too large for 32-bit type 'int')
PR target/84945
* config/i386/i386.c (fold_builtin_cpu): For features above 31
use __cpu_features2 variable instead of __cpu_model.__cpu_features[0].
Use 1U instead of 1. Formatting fixes.
* gcc.target/i386/pr84945.c: New test.
* config/i386/cpuinfo.h (__cpu_features2): Declare.
* config/i386/cpuinfo.c (__cpu_features2): New variable for
ifndef SHARED only.
(set_feature): Define.
(get_available_features): Use set_feature macro. Set __cpu_features2
to the second word of features ifndef SHARED.
From-SVN: r258673
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2018-03-20 Christophe Lyon <christophe.lyon@linaro.org>
PR target/81647
* gcc.target/aarch64/pr81647.c: Require fenv_exceptions.
From-SVN: r258672
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PR c/84953
* builtins.c (fold_builtin_strpbrk): For strpbrk(x, "") use type
instead of TREE_TYPE (s1) for the return value.
* gcc.dg/pr84953.c: New test.
From-SVN: r258671
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From-SVN: r258670
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../../gcc/gimple-ssa-store-merging.c:3951)
PR tree-optimization/84946
* gimple-ssa-store-merging.c (mem_valid_for_store_merging): Compute
bitsize + bitsize in poly_uint64 rather than poly_int64.
From-SVN: r258665
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local class and PIC and sanitizer are active)
PR sanitizer/78651
* dwarf2asm.c: Include fold-const.c.
(dw2_output_indirect_constant_1): Set DECL_INITIAL (decl) to ADDR_EXPR
of decl rather than decl itself.
From-SVN: r258664
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x86)
PR sanitizer/84761
* sanitizer_common/sanitizer_linux_libcdep.cc (__GLIBC_PREREQ):
Define if not defined.
(DL_INTERNAL_FUNCTION): Don't define.
(InitTlsSize): For __i386__ if not compiled against glibc 2.27+
determine at runtime whether to use regparm(3), stdcall calling
convention for older glibcs or normal calling convention for
newer glibcs for call to _dl_get_tls_static_info.
From-SVN: r258663
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