aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2021-06-16c++: static memfn from non-dependent base [PR101078]Jason Merrill2-2/+30
After my patch for PR91706, or before that with the qualified call, tsubst_baselink returned a BASELINK with BASELINK_BINFO indicating a base of a still-dependent derived class. We need to look up the relevant base binfo in the substituted class. PR c++/101078 PR c++/91706 gcc/cp/ChangeLog: * pt.c (tsubst_baselink): Update binfos in non-dependent case. gcc/testsuite/ChangeLog: * g++.dg/template/access39.C: New test.
2021-06-16Fortran - ICE in gfc_check_do_variable, at fortran/parse.c:4446Harald Anlauf4-1/+15
Avoid NULL pointer dereferences during error recovery. gcc/fortran/ChangeLog: PR fortran/95501 PR fortran/95502 * expr.c (gfc_check_pointer_assign): Avoid NULL pointer dereference. * match.c (gfc_match_pointer_assignment): Likewise. * parse.c (gfc_check_do_variable): Avoid comparison with NULL symtree. gcc/testsuite/ChangeLog: PR fortran/95501 PR fortran/95502 * gfortran.dg/pr95502.f90: New test.
2021-06-16Revert "Fortran - ICE in gfc_check_do_variable, at fortran/parse.c:4446"Harald Anlauf4-27/+1
This reverts commit 72e3d92178b44a3722519ec68e72e307443bda70.
2021-06-16Fortran - ICE in gfc_check_do_variable, at fortran/parse.c:4446Harald Anlauf4-1/+27
Avoid NULL pointer dereferences during error recovery. gcc/fortran/ChangeLog: PR fortran/95501 PR fortran/95502 * expr.c (gfc_check_pointer_assign): Avoid NULL pointer dereference. * match.c (gfc_match_pointer_assignment): Likewise. * parse.c (gfc_check_do_variable): Avoid comparison with NULL symtree. gcc/testsuite/ChangeLog: PR fortran/95501 PR fortran/95502 * gfortran.dg/pr95502.f90: New test.
2021-06-16Avoid loading an undefined value in the ranger_cache constructor.Andrew MacLeod1-1/+1
Enable_new_values takes a boolean, returning the old value. The constructor for ranger_cache initialized the m_new_value_p field by calling this routine and ignorng the result. This potentially loads the old value uninitialized. * gimple-range-cache.cc (ranger_cache::ranger_cache): Initialize m_new_value_p directly.
2021-06-16libcpp: location comparison within macro [PR100796]Jason Merrill3-10/+38
The patch for 96391 changed linemap_compare_locations to give up on comparing locations from macro expansions if we don't have column information. But in this testcase, the BOILERPLATE macro is multiple lines long, so we do want to compare locations within the macro. So this patch moves the LINE_MAP_MAX_LOCATION_WITH_COLS check inside the block, to use it for failing gracefully. PR c++/100796 PR preprocessor/96391 libcpp/ChangeLog: * line-map.c (linemap_compare_locations): Only use comparison with LINE_MAP_MAX_LOCATION_WITH_COLS to avoid abort. gcc/testsuite/ChangeLog: * g++.dg/plugin/location-overflow-test-pr100796.c: New test. * g++.dg/plugin/plugin.exp: Run it.
2021-06-16ii386: Add missing two element 64bit vector permutations [PR89021]Uros Bizjak2-25/+82
In addition to V8QI permutations, several other missing permutations are added for 64bit vector modes for TARGET_SSSE3 and TARGET_SSE4_1 targets. 2021-06-16 Uroš Bizjak <ubizjak@gmail.com> gcc/ PR target/89021 * config/i386/i386-expand.c (expand_vec_perm_2perm_pblendv): Handle 64bit modes for TARGET_SSE4_1. (expand_vec_perm_pshufb2): Handle 64bit modes for TARGET_SSSE3. (expand_vec_perm_even_odd_pack): Handle V4HI mode. (expand_vec_perm_even_odd_1) <case E_V4HImode>: Expand via expand_vec_perm_pshufb2 for TARGET_SSSE3 and via expand_vec_perm_even_odd_pack for TARGET_SSE4_1. * config/i386/mmx.md (mmx_packusdw): New insn pattern.
2021-06-16libstdc++: Use named struct for __decay_copyJonathan Wakely1-1/+2
In r12-1486-gcb326a6442f09cb36b05ce556fc91e10bfeb0cf6 I changed __decay_copy to be a function object of unnamed class type. This causes problems when importing the library headers: error: conflicting global module declaration 'constexpr const std::ranges::__cust_access::<unnamed struct> std::ranges::__cust_access::__decay_copy' The fix is to use a named struct instead of an anonymous one. Signed-off-by: Jonathan Wakely <jwakely@redhat.com> libstdc++-v3/ChangeLog: * include/bits/iterator_concepts.h (__decay_copy): Name type.
2021-06-16libstdc++: Revert final/non-addressable changes to ranges CPOsJonathan Wakely18-38/+68
In r12-1489-g8b93548778a487f31f21e0c6afe7e0bde9711fc4 I made the [range.access] CPO types final and non-addressable. Tim Song pointed out this is wrong. Only the [range.iter.ops] functions should be final and non-addressable. Revert the changes to the [range.access] objects. Signed-off-by: Jonathan Wakely <jwakely@redhat.com> libstdc++-v3/ChangeLog: * include/bits/ranges_base.h (ranges::begin, ranges::end) (ranges::cbegin, ranges::cend, ranges::rbeing, ranges::rend) (ranges::crbegin, ranges::crend, ranges::size, ranges::ssize) (ranges::empty, ranges::data, ranges::cdata): Remove final keywords and deleted operator& overloads. * testsuite/24_iterators/customization_points/iter_move.cc: Use new is_customization_point_object function. * testsuite/24_iterators/customization_points/iter_swap.cc: Likewise. * testsuite/std/concepts/concepts.lang/concept.swappable/swap.cc: Likewise. * testsuite/std/ranges/access/begin.cc: Likewise. * testsuite/std/ranges/access/cbegin.cc: Likewise. * testsuite/std/ranges/access/cdata.cc: Likewise. * testsuite/std/ranges/access/cend.cc: Likewise. * testsuite/std/ranges/access/crbegin.cc: Likewise. * testsuite/std/ranges/access/crend.cc: Likewise. * testsuite/std/ranges/access/data.cc: Likewise. * testsuite/std/ranges/access/empty.cc: Likewise. * testsuite/std/ranges/access/end.cc: Likewise. * testsuite/std/ranges/access/rbegin.cc: Likewise. * testsuite/std/ranges/access/rend.cc: Likewise. * testsuite/std/ranges/access/size.cc: Likewise. * testsuite/std/ranges/access/ssize.cc: Likewise. * testsuite/util/testsuite_iterators.h (is_customization_point_object): New function.
2021-06-16aarch64: Model zero-high-half semantics of ADDHN/SUBHN instructionsJonathan Wright2-6/+83
Model the zero-high-half semantics of the narrowing arithmetic Neon instructions in the aarch64_<sur><addsub>hn<mode> RTL pattern. Modeling these semantics allows for better RTL combinations while also removing some register allocation issues as the compiler now knows that the operation is totally destructive. Add new tests to narrow_zero_high_half.c to verify the benefit of this change. gcc/ChangeLog: 2021-06-14 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn<mode>): Change to an expander that emits the correct instruction depending on endianness. (aarch64_<sur><addsub>hn<mode>_insn_le): Define. (aarch64_<sur><addsub>hn<mode>_insn_be): Define. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_zero_high_half.c: Add new tests.
2021-06-16aarch64: Model zero-high-half semantics of [SU]QXTN instructionsJonathan Wright3-4/+59
Split the aarch64_<su>qmovn<mode> pattern into separate scalar and vector variants. Further split the vector RTL pattern into big/ little endian variants that model the zero-high-half semantics of the underlying instruction. Modeling these semantics allows for better RTL combinations while also removing some register allocation issues as the compiler now knows that the operation is totally destructive. Add new tests to narrow_zero_high_half.c to verify the benefit of this change. gcc/ChangeLog: 2021-06-14 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Split generator for aarch64_<su>qmovn builtins into scalar and vector variants. * config/aarch64/aarch64-simd.md (aarch64_<su>qmovn<mode>_insn_le): Define. (aarch64_<su>qmovn<mode>_insn_be): Define. (aarch64_<su>qmovn<mode>): Split into scalar and vector variants. Change vector variant to an expander that emits the correct instruction depending on endianness. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_zero_high_half.c: Add new tests.
2021-06-16aarch64: Model zero-high-half semantics of SQXTUN instruction in RTLJonathan Wright3-12/+63
Split the aarch64_sqmovun<mode> pattern into separate scalar and vector variants. Further split the vector pattern into big/little endian variants that model the zero-high-half semantics of the underlying instruction. Modeling these semantics allows for better RTL combinations while also removing some register allocation issues as the compiler now knows that the operation is totally destructive. Add new tests to narrow_zero_high_half.c to verify the benefit of this change. gcc/ChangeLog: 2021-06-14 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Split generator for aarch64_sqmovun builtins into scalar and vector variants. * config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>): Split into scalar and vector variants. Change vector variant to an expander that emits the correct instruction depending on endianness. (aarch64_sqmovun<mode>_insn_le): Define. (aarch64_sqmovun<mode>_insn_be): Define. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_zero_high_half.c: Add new tests.
2021-06-16aarch64: Model zero-high-half semantics of XTN instruction in RTLJonathan Wright3-35/+88
Modeling the zero-high-half semantics of the XTN narrowing instruction in RTL indicates to the compiler that this is a totally destructive operation. This enables more RTL simplifications and also prevents some register allocation issues. Add new tests to narrow_zero_high_half.c to verify the benefit of this change. gcc/ChangeLog: 2021-06-11 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le): Define - modeling zero-high-half semantics. (aarch64_xtn<mode>): Change to an expander that emits the appropriate instruction depending on endianness. (aarch64_xtn<mode>_insn_be): Define - modeling zero-high-half semantics. (aarch64_xtn2<mode>_le): Rename to... (aarch64_xtn2<mode>_insn_le): This. (aarch64_xtn2<mode>_be): Rename to... (aarch64_xtn2<mode>_insn_be): This. (vec_pack_trunc_<mode>): Emit truncation instruction instead of aarch64_xtn. * config/aarch64/iterators.md (Vnarrowd): Add Vnarrowd mode attribute iterator. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_zero_high_half.c: Add new tests.
2021-06-16testsuite: aarch64: Add zero-high-half tests for narrowing shiftsJonathan Wright1-0/+60
Add tests to verify that Neon narrowing-shift instructions clear the top half of the result vector. It is sufficient to show that a subsequent combine with a zero-vector is optimized away - leaving just the narrowing-shift instruction. gcc/testsuite/ChangeLog: 2021-06-15 Jonathan Wright <jonathan.wright@arm.com> * gcc.target/aarch64/narrow_zero_high_half.c: New test.
2021-06-16tree-sra: Do not refresh readonly decls (PR 100453)Martin Jambor2-4/+35
When SRA transforms an assignment where the RHS is an aggregate decl that it creates replacements for, the (least efficient) fallback method of dealing with them is to store all the replacements back into the original decl and then let the original assignment takes its course. That of course should not need to be done for TREE_READONLY bases which cannot change contents. The SRA code handled this situation only for DECL_IN_CONSTANT_POOL const decls, this patch modifies the check so that it tests for TREE_READONLY and I also looked at all other callers of generate_subtree_copies and added checks to another one dealing with the same exact situation and one which deals with it in a non-assignment context. gcc/ChangeLog: 2021-06-11 Martin Jambor <mjambor@suse.cz> PR tree-optimization/100453 * tree-sra.c (create_access): Disqualify any const candidates which are written to. (sra_modify_expr): Do not store sub-replacements back to a const base. (handle_unscalarized_data_in_subtree): Likewise. (sra_modify_assign): Likewise. Earlier, use TREE_READONLy test instead of constant_decl_p. gcc/testsuite/ChangeLog: 2021-06-10 Martin Jambor <mjambor@suse.cz> PR tree-optimization/100453 * gcc.dg/tree-ssa/pr100453.c: New test.
2021-06-16testsuite: Use noipa attribute instead of noinline, nocloneJakub Jelinek1-1/+1
I've noticed this test now on various arches sometimes FAILs, sometimes PASSes (the line 12 test in particular). The problem is that a = 0; initialization in the caller no longer happens before the f(&a) call as what the argument points to is only used in debug info. Making the function noipa forces the caller to initialize it and still tests what the test wants to test, namely that we don't consider *p as valid location for the c variable at line 18 (after it has been overwritten with *p = 1;). 2021-06-16 Jakub Jelinek <jakub@redhat.com> * gcc.dg/guality/pr49888.c (f): Use noipa attribute instead of noinline, noclone.
2021-06-16stor-layout: Create DECL_BIT_FIELD_REPRESENTATIVE even for bitfields in ↵Jakub Jelinek2-11/+44
unions [PR101062] The following testcase is miscompiled on x86_64-linux, the bitfield store is implemented as a RMW 64-bit operation at d+24 when the d variable has size of only 28 bytes and scheduling moves in between the R and W part a store to a different variable that happens to be right after the d variable. The reason for this is that we weren't creating DECL_BIT_FIELD_REPRESENTATIVEs for bitfields in unions. The following patch does create them, but treats all such bitfields as if they were in a structure where the particular bitfield is the only field. 2021-06-16 Jakub Jelinek <jakub@redhat.com> PR middle-end/101062 * stor-layout.c (finish_bitfield_representative): For fields in unions assume nextf is always NULL. (finish_bitfield_layout): Compute bit field representatives also in unions, but handle it as if each bitfield was the only field in the aggregate. * gcc.dg/pr101062.c: New test.
2021-06-16tree-optimization/101088 - fix SM invalidation issueRichard Biener2-5/+61
When we face a sm_ord vs sm_unord for the same ref during store sequence merging we assert that the ref is already marked unsupported. But it can be that it will only be marked so during the ongoing merging so instead of asserting mark it here. Also apply some optimization to not waste resources to search for already unsupported refs. 2021-06-16 Richard Biener <rguenther@suse.de> PR tree-optimization/101088 * tree-ssa-loop-im.c (sm_seq_valid_bb): Only look for supported refs on edges. Do not assert same ref but different kind stores are unsuported but mark them so. (hoist_memory_references): Only look for supported refs on exits. * gcc.dg/torture/pr101088.c: New testcase.
2021-06-16[PATCH] PR rtl-optimization/46235: Improved use of bt for bit tests on x86_64.Roger Sayle4-0/+276
This patch tackles PR46235 to improve the code generated for bit tests on x86_64 by making more use of the bt instruction. Currently, GCC emits bt instructions when followed by condition jumps (thanks to Uros' splitters). This patch adds splitters in i386.md, to catch the cases where bt is followed by a conditional move (as in the original report), or by a setc/setnc (as in comment 5 of the Bugzilla PR). With this patch, the function in the original PR int foo(int a, int x, int y) { if (a & (1 << x)) return a; return 1; } which with -O2 on mainline generates: foo: movl %edi, %eax movl %esi, %ecx sarl %cl, %eax testb $1, %al movl $1, %eax cmovne %edi, %eax ret now generates: foo: btl %esi, %edi movl $1, %eax cmovc %edi, %eax ret Likewise, IsBitSet1 and IsBitSet2 (from comment 5) bool IsBitSet1(unsigned char byte, int index) { return (byte & (1<<index)) != 0; } bool IsBitSet2(unsigned char byte, int index) { return (byte >> index) & 1; } Before: movzbl %dil, %eax movl %esi, %ecx sarl %cl, %eax andl $1, %eax ret After: movzbl %dil, %edi btl %esi, %edi setc %al ret According to Agner Fog, SAR/SHR r,cl takes 2 cycles on skylake, where BT r,r takes only one, so the performance improvements on recent hardware may be more significant than implied by just the reduced number of instructions. I've avoided transforming cases (such as btsi_setcsi) where using bt sequences may not be a clear win (over sarq/andl). 2010-06-15 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog PR rtl-optimization/46235 * config/i386/i386.md: New define_split for bt followed by cmov. (*bt<mode>_setcqi): New define_insn_and_split for bt followed by setc. (*bt<mode>_setncqi): New define_insn_and_split for bt then setnc. (*bt<mode>_setnc<mode>): New define_insn_and_split for bt followed by setnc with zero extension. gcc/testsuite/ChangeLog PR rtl-optimization/46235 * gcc.target/i386/bt-5.c: New test. * gcc.target/i386/bt-6.c: New test. * gcc.target/i386/bt-7.c: New test.
2021-06-16libffi: Fix up x86_64 classify_argumentJakub Jelinek2-4/+112
As the following testcase shows, libffi didn't handle properly classify_arguments of structures at byte offsets not divisible by UNITS_PER_WORD. The following patch adjusts it to match what config/i386/ classify_argument does for that and also ports the PR38781 fix there (the second chunk). This has been committed to upstream libffi already: https://github.com/libffi/libffi/commit/5651bea284ad0822eafe768e3443c2f4d7da2c8f 2021-06-16 Jakub Jelinek <jakub@redhat.com> * src/x86/ffi64.c (classify_argument): For FFI_TYPE_STRUCT set words to number of words needed for type->size + byte_offset bytes rather than just type->size bytes. Compute pos before the loop and check total size of the structure. * testsuite/libffi.call/nested_struct12.c: New test.
2021-06-16[Ada] Fix Is_Volatile_Function for functions declared in protected bodiesPiotr Trojanek1-2/+4
gcc/ada/ * sem_util.adb (Is_Volatile_Function): Follow the exact wording of SPARK (regarding volatile functions) and Ada (regarding protected functions).
2021-06-16[Ada] Ignore volatile restrictions in preanalysisPiotr Trojanek1-18/+14
gcc/ada/ * sem_util.adb (Is_OK_Volatile_Context): All references to volatile objects are legal in preanalysis. (Within_Volatile_Function): Previously it was wrongly called on Empty entities; now it is only called on E_Return_Statement, which allow the body to be greatly simplified.
2021-06-16[Ada] Do not generate an Itype_Reference node for slices in GNATprove modeYannick Moy1-3/+2
gcc/ada/ * sem_res.adb (Set_Slice_Subtype): Revert special-case introduced previously, which is not needed as Itypes created for slices are precisely always used.
2021-06-16[Ada] Fix floating-point exponentiation with Integer'First exponentEric Botcazou2-9/+10
gcc/ada/ * urealp.adb (Scale): Change first paramter to Uint and adjust. (Equivalent_Decimal_Exponent): Pass U.Den directly to Scale. * libgnat/s-exponr.adb (Negative): Rename to... (Safe_Negative): ...this and change its lower bound. (Exponr): Adjust to above renaming and deal with Integer'First.
2021-06-16[Ada] Fix detection of volatile expressions in restricted contextsPiotr Trojanek3-101/+91
gcc/ada/ * sem_res.adb (Flag_Effectively_Volatile_Objects): Detect also allocators within restricted contexts and not just entity names. (Resolve_Actuals): Remove duplicated code for detecting restricted contexts; it is now exclusively done in Is_OK_Volatile_Context. (Resolve_Entity_Name): Adapt to new parameter of Is_OK_Volatile_Context. * sem_util.ads, sem_util.adb (Is_OK_Volatile_Context): Adapt to handle contexts both inside and outside of subprogram call actual parameters. (Within_Subprogram_Call): Remove; now handled by Is_OK_Volatile_Context itself and its parameter.
2021-06-16[Ada] Cleanup repeated calls in Sloc_RangePiotr Trojanek1-12/+9
gcc/ada/ * sinput.adb (Sloc_Range): Refactor several repeated calls to Sloc and two comparisons with No_Location.
2021-06-16[Ada] Fix aliasing check for actual parameters passed by referencePiotr Trojanek1-18/+40
gcc/ada/ * checks.adb (Apply_Scalar_Range_Check): Fix handling of check depending on the parameter passing mechanism. Grammar adjustment ("has" => "have"). (Parameter_Passing_Mechanism_Specified): Add a hyphen in a comment.
2021-06-16[Ada] Remove unused initialization with New_ListPiotr Trojanek1-1/+1
gcc/ada/ * exp_ch3.adb (Build_Slice_Assignment): Remove unused initialization.
2021-06-16[Ada] Fix typos in all occurrences of "occuring" in GNATPiotr Trojanek3-6/+7
gcc/ada/ * restrict.adb, sem_attr.adb, types.ads: Fix typos in "occuring"; refill comment as necessary.
2021-06-16[Ada] Adapt Is_Actual_Parameter to also work for entry parametersPiotr Trojanek2-2/+4
gcc/ada/ * sem_util.ads (Is_Actual_Parameter): Update comment. * sem_util.adb (Is_Actual_Parameter): Also detect entry parameters.
2021-06-16[Ada] Wrong reference to System.Tasking in expanded codeArnaud Charlet7-47/+28
gcc/ada/ * rtsfind.ads, libgnarl/s-taskin.ads, exp_ch3.adb, exp_ch4.adb, exp_ch6.adb, exp_ch9.adb, sem_ch6.adb: Move master related entities to the expander directly.
2021-06-16[Ada] Cleanup related to volatile objects in restricted contextsPiotr Trojanek1-2/+6
gcc/ada/ * sem_res.adb (Is_Assignment_Or_Object_Expression): Whitespace cleanup. (Is_Attribute_Expression): Prevent AST climbing from going to the root of the compilation unit.
2021-06-16[Ada] Include info about containers in GNAT RM Implementation Advice sectionSteve Baird2-298/+337
gcc/ada/ * doc/gnat_rm/implementation_advice.rst: Add a section for RM A.18 . * gnat_rm.texi: Regenerate.
2021-06-16[Ada] Mixing of positional and named entries allowed in enum repJustin Squirek1-4/+12
gcc/ada/ * sem_ch13.adb (Analyze_Enumeration_Representation_Clause): Add check for the mixing of entries.
2021-06-16[Ada] Non-static Interrupt_Priority allowed with restriction Static_PrioritiesJustin Squirek1-0/+7
gcc/ada/ * sem_ch13.adb (Make_Aitem_Pragma): Check for static expressions in Priority aspect arguments for restriction Static_Priorities.
2021-06-16[Ada] Spurious accessibility error on "for of" loop parameterJustin Squirek1-0/+9
gcc/ada/ * sem_util.adb (Accessibility_Level): Take into account renamings of loop parameters.
2021-06-16[Ada] Fix ALI source location for dominance markersMatthieu Eyraud1-4/+19
gcc/ada/ * par_sco.adb (Set_Statement_Entry): Change sloc for dominance marker. (Traverse_One): Fix typo. (Output_Header): Fix comment.
2021-06-16[Ada] Don't look for aliases for generic subprogramsRichard Kenner1-2/+3
gcc/ada/ * exp_unst.adb (Register_Subprogram): Don't look for aliases for subprograms that are generic. Reorder tests for efficiency.
2021-06-16[Ada] Make Incomplete_Or_Partial_View independent of the contextEric Botcazou1-7/+14
gcc/ada/ * sem_util.adb (Incomplete_Or_Partial_View): Retrieve the scope of the parameter and use it to find its incomplete view, if any.
2021-06-16[Ada] Do not perform useless work in Check_No_Parts_ViolationsEric Botcazou1-16/+19
gcc/ada/ * freeze.adb (Check_No_Parts_Violations): Return earlier if the type is elementary or does not come from source.
2021-06-16[Ada] Fix missing array bounds checkingBob Duff1-4/+14
gcc/ada/ * ghost.adb: Add another special case where full analysis is needed. This bug is due to quirks in the way Mark_And_Set_Ghost_Assignment works (it happens very early, before name resolution is done).
2021-06-16[Ada] Use more straightforward implementation for Current_Entity_In_ScopeEric Botcazou1-8/+19
gcc/ada/ * sem_util.adb (Current_Entity_In_Scope): Reimplement.
2021-06-16[Ada] Remove extra parens around a function callPiotr Trojanek1-1/+1
gcc/ada/ * sem_ch8.adb (End_Scope): Remove extra parens.
2021-06-16[Ada] ACATS 4.1R-c611a04: Class-wide preconditions in dispatching callsJavier Miranda1-0/+10
gcc/ada/ * exp_disp.adb (Build_Class_Wide_Check): Ensure that evaluation of actuals is side effects free (since the check duplicates actuals).
2021-06-16[Ada] Implementation of AI12-0152: legality rules for Raise_ExpressionEd Schonberg1-0/+49
gcc/ada/ * sem_res.adb (Resolve_Raise_Expression): Apply Ada_2020 rules concerning the need for parentheses around Raise_Expressions in various contexts.
2021-06-16[Ada] Reorder code for validity checks of unchecked conversionsPiotr Trojanek1-13/+12
gcc/ada/ * sem_ch13.adb (Validate_Unchecked_Conversion): Move detection of generic types before switching to their private views; fix style in using AND THEN.
2021-06-16[Ada] Raise expressions and unconstrained componentsArnaud Charlet2-18/+8
gcc/ada/ * sem_ch3.adb (Analyze_Component_Declaration): Do not special case raise expressions. gcc/testsuite/ * gnat.dg/limited4.adb: Disable illegal code.
2021-06-16[Ada] Clarify the documentation of -gnaty0 style check optionSergey Rybin2-4/+31
gcc/ada/ * doc/gnat_ugn/building_executable_programs_with_gnat.rst: Instead of referring to the formatting of the Ada examples in Ada RM add use the list of checks that are actually performed. * gnat_ugn.texi: Regenerate.
2021-06-16[Ada] Small cleanup in C header filesEric Botcazou2-65/+9
gcc/ada/ * initialize.c: Do not include vxWorks.h and fcntl.h from here. (__gnat_initialize) [__MINGW32__]: Remove #ifdef and attribute (__gnat_initialize) [init_float]: Delete. (__gnat_initialize) [VxWorks]: Likewise. (__gnat_initialize) [PA-RISC HP-UX 10]: Likewise. * runtime.h: Add comment about vxWorks.h include.
2021-06-16[Ada] Small cleanup in System.ExceptionsEric Botcazou2-35/+2
gcc/ada/ * libgnat/s-except.ads (ZCX_By_Default): Delete. (Require_Body): Likewise. * libgnat/s-except.adb: Replace body with pragma No_Body.
generated by cgit v1.1 at 2025-03-03 12:29:09 +0000