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2023-06-06Daily bump.GCC Administrator3-1/+20
2023-06-05d: Warn when declared size of a special enum does not match its intrinsic type.Iain Buclaw5-0/+49
All special enums have declarations in the D runtime library, but the compiler will recognize and treat them specially if declared in any module. When the underlying base type of a special enum is a different size to its matched intrinsic, then this can cause undefined behavior at runtime. Detect and warn about when such a mismatch occurs. gcc/d/ChangeLog: * gdc.texi (Warnings): Document -Wextra and -Wmismatched-special-enum. * implement-d.texi (Special Enums): Add reference to warning option -Wmismatched-special-enum. * lang.opt: Add -Wextra and -Wmismatched-special-enum. * types.cc (TypeVisitor::visit (TypeEnum *)): Warn when declared special enum size mismatches its intrinsic type. gcc/testsuite/ChangeLog: * gdc.dg/Wmismatched_enum.d: New test. (cherry picked from commit 3ad9313a2e28287aa350d9dc3ea7746d8302662d)
2023-06-05Daily bump.GCC Administrator1-1/+1
2023-06-04Daily bump.GCC Administrator4-1/+29
2023-06-03Fortran: fix diagnostics for SELECT RANK [PR100607]Steve Kargl2-6/+52
gcc/fortran/ChangeLog: PR fortran/100607 * resolve.cc (resolve_select_rank): Remove duplicate error. (resolve_fl_var_and_proc): Prevent NULL pointer dereference and suppress error message for temporary. gcc/testsuite/ChangeLog: PR fortran/100607 * gfortran.dg/select_rank_6.f90: New test. (cherry picked from commit fae09dfc0e6bf4cfe35d817558827aea78c6426f)
2023-06-03fix radix sort on 32bit platforms [PR109670]Thomas Neumann1-5/+3
The radix sort uses two buffers, a1 for input and a2 for output. After every digit the role of the two buffers is swapped. When terminating the sort early the code made sure the output was in a2. However, when we run out of bits, as can happen on 32bit platforms, the sorted result was in a1, as we had just swapped a1 and a2. This patch fixes the problem by unconditionally having a1 as output after every loop iteration. This bug manifested itself only on 32bit platforms and even then only in some circumstances, as it needs frames where a swap is required due to differences in the top-most byte, which is affected by ASLR. The new logic was validated by exhaustive search over 32bit input values. libgcc/ChangeLog: PR libgcc/109670 * unwind-dw2-fde.c: Fix radix sort buffer management.
2023-06-03release the sorted FDE array when deregistering a frame [PR109685]Thomas Neumann1-0/+6
The atomic fastpath bypasses the code that releases the sort array which was lazily allocated during unwinding. We now check after deregistering if there is an array to free. libgcc/ChangeLog: PR libgcc/109685 * unwind-dw2-fde.c: Free sort array in atomic fast path.
2023-06-03Daily bump.GCC Administrator2-1/+8
2023-06-02target/110088: Improve operation of l-reg with const after move from d-reg.Georg-Johann Lay1-1/+40
After reload, there may be sequences like lreg = dreg lreg = lreg <op> const with an LD_REGS dreg, non-LD_REGS lreg, and <op> in PLUS, IOR, AND. If dreg dies after the first insn, it is possible to use dreg = dreg <op> const lreg = dreg instead which is more efficient. gcc/ PR target/110088 * config/avr/avr.md: Add an RTL peephole to optimize operations on non-LD_REGS after a move from LD_REGS. (piaop): New code iterator.
2023-06-02Daily bump.GCC Administrator3-1/+85
2023-06-01libstdc++: Fix std::abs(__float128) for -NaN and -0.0 [PR109758]Jonathan Wakely2-2/+63
The current implementation of this non-standard overload of std::abs incorrectly returns a negative value for negative NaNs and negative zero, because x < 0 is false in both cases. Use fabsl(long double) or fabsf128(_Float128) if those do the right thing. Otherwise, use __builtin_signbit(x) instead of x < 0 to detect negative inputs. This assumes that __builtin_signbit handles __float128 correctly, but that seems to be true for all of GCC, clang and icc. libstdc++-v3/ChangeLog: PR libstdc++/109758 * include/bits/std_abs.h (abs(__float128)): Handle negative NaN and negative zero correctly. * testsuite/26_numerics/headers/cmath/109758.cc: New test. (cherry picked from commit af595613acbd9863198ae69c7b1c9e856bca9e4f)
2023-06-01libstdc++: Remove test dependency on _GLIBCXX_USE_C99_STDINT_TR1Jonathan Wakely1-1/+1
This should have been done in r9-2028-g8ba7f29e3dd064 when std::shared_mutex was changed to be defined without depending on _GLIBCXX_USE_C99_STDINT_TR1. libstdc++-v3/ChangeLog: * testsuite/experimental/feat-cxx14.cc: Remove dependency on _GLIBCXX_USE_C99_STDINT_TR1. (cherry picked from commit 2c04284abe5d5f1148c709a769f3b83bee2485d0)
2023-06-01libstdc++: Remove test dependencies on _GLIBCXX_USE_C99_STDINT_TR1Jonathan Wakely2-4/+0
These #ifdef checks should have been removed in r9-2029-g612c9c702e2c9e when the u16string_view and u32string_view aliases were changed to be defined unconditionally. libstdc++-v3/ChangeLog: * testsuite/21_strings/basic_string_view/typedefs.cc: Remove dependency on _GLIBCXX_USE_C99_STDINT_TR1. * testsuite/experimental/string_view/typedefs.cc: Likewise. (cherry picked from commit fe0e3df6f3751a0164c8e92a0d6519f2e10527a8)
2023-06-01libstdc++: Fix PSTL test that fails in C++20Jonathan Wakely1-1/+1
This test fails in C++20 and later due to a warning: warning: C++20 says that these are ambiguous, even though the second is reversed: note: candidate 1: 'bool MyClass::operator==(const MyClass&)' note: candidate 2: 'bool MyClass::operator==(const MyClass&)' (reversed) note: try making the operator a 'const' member function FAIL: 26_numerics/pstl/numeric_ops/transform_reduce.cc (test for excess errors) libstdc++-v3/ChangeLog: * testsuite/26_numerics/pstl/numeric_ops/transform_reduce.cc: Add const to equality operator. (cherry picked from commit f8403c43045cd56b5f775e1cf12a3f22feca4b58)
2023-06-01libstdc++: Document removal of implicit allocator rebinding extensionsJonathan Wakely2-0/+22
Traditionally libstdc++ allowed containers to be instantiated with allocator's that have the wrong value type, implicitly rebinding the allocator to the container's value type. Since C++20 that has been explicitly ill-formed, so the extension is no longer supported in strict modes (e.g. -std=c++17) and in C++20 and later. libstdc++-v3/ChangeLog: * doc/xml/manual/evolution.xml: Document removal of implicit allocator rebinding extensions in strict mode and for C++20. * doc/html/*: Regenerate. (cherry picked from commit 8cbaf679a3c1875c5475bd1cb0fb86fb9d03b2d4)
2023-06-01libstdc++: Fix -Wnonnull warnings during configureJonathan Wakely2-8/+8
We should not test for nan by passing it a null pointer, as this can trigger -Wnonnull warnings. Also fix an outdated comment about the default -std mode. libstdc++-v3/ChangeLog: * acinclude.m4 (GLIBCXX_CHECK_C99_TR1): Use a non-null pointer to check for nan, nanf, and nanl. * configure: Regenerate. (cherry picked from commit 6190a74ebee69415b501996821c92f60d892fb81)
2023-06-01libstdc++: Require tzdb support for chrono::zoned_time printer testJonathan Wakely1-1/+2
libstdc++-v3/ChangeLog: * testsuite/libstdc++-prettyprinters/chrono.cc: Only test printer for chrono::zoned_time for cx11 ABI and tzdb effective target. (cherry picked from commit 151bad410218d266e16b90da0147d57f9d661c1a)
2023-06-01libstdc++: Fix <chrono> pretty printers and add testsJonathan Wakely2-18/+113
This fixes a couple of errors in the printers for chrono types, and adds tests to ensure they keep working. libstdc++-v3/ChangeLog: * python/libstdcxx/v6/printers.py (StdChronoDurationPrinter): Print floating-point durations correctly. (StdChronoTimePointPrinter): Support printing only the value, not the type name. Uncomment handling for known clocks. (StdChronoZonedTimePrinter): Remove type names from output. (StdChronoCalendarPrinter): Fix hh_mm_ss member access. (StdChronoTimeZonePrinter): Add equals sign to output. * testsuite/libstdc++-prettyprinters/chrono.cc: New test. (cherry picked from commit 7bd251ca751317385f7e2e4e031736a99f376012)
2023-06-01doc: Fix description of x86 -m32 option [PR109954]Jonathan Wakely1-1/+1
This option does not imply -march=i386 so it's incorrect to say it generates code that will run on "any i386 system". gcc/ChangeLog: PR target/109954 * doc/invoke.texi (x86 Options): Fix description of -m32 option. (cherry picked from commit eeb92704967875411416b0b9508aa6f49e8192fd)
2023-06-01OpenMP/Fortran: Permit pure directives inside PURETobias Burnus12-40/+322
Update permitted directives for directives marked in OpenMP's 5.2 as pure. To ensure that list is updated, unimplemented directives are placed into pure-2.f90 such the test FAILs once a known to be pure directive is implemented without handling its pureness. gcc/fortran/ChangeLog: * parse.cc (decode_omp_directive): Accept all pure directives inside a PURE procedures; handle 'error at(execution). libgomp/ChangeLog: * libgomp.texi (OpenMP 5.2): Mark pure-directive handling as 'Y'. gcc/testsuite/ChangeLog: * gfortran.dg/gomp/nothing-2.f90: Remove one dg-error. * gfortran.dg/gomp/pr79154-2.f90: Update expected dg-error wording. * gfortran.dg/gomp/pr79154-simd.f90: Likewise. * gfortran.dg/gomp/pure-1.f90: New test. * gfortran.dg/gomp/pure-2.f90: New test. * gfortran.dg/gomp/pure-3.f90: New test. * gfortran.dg/gomp/pure-4.f90: New test. (cherry picked from commit 2df7e45188f32e3c448e004af38d56eb9ab8d959) (Also marks unroll, tile and metadirectives as pure - and updated the pure-1.f90 + pure-2.f90 tests accordingly.)
2023-06-01Daily bump.GCC Administrator1-1/+1
2023-05-31Daily bump.GCC Administrator4-1/+64
2023-05-30[libstdc++] [testsuite] xfail double-prec from_chars for x86_64 ldblAlexandre Oliva2-2/+2
When long double is wider than double, but from_chars is implemented in terms of double, tests that involve the full precision of long double are expected to fail. Mark them as such on x86_64-*-vxworks*. for libstdc++-v3/ChangeLog * testsuite/20_util/from_chars/4.cc: Skip long double test06 on x86_64-vxworks. * testsuite/20_util/to_chars/long_double.cc: Xfail run on x86_64-vxworks. (cherry picked from commit 282e4e745981c5c6e3edaae315e1f499a45402df)
2023-05-30testsuite: make mve_intrinsic_type_overloads-int.c libc-agnosticChristophe Lyon1-13/+15
Glibc defines int32_t as 'int' while newlib defines it as 'long int'. Although these correspond to the same size, g++ complains when using the 'wrong' version: invalid conversion from 'long int*' to 'int32_t*' {aka 'int*'} [-fpermissive] or invalid conversion from 'int*' to 'int32_t*' {aka 'long int*'} [-fpermissive] when calling vst1q(int32*, int32x4_t) with a first parameter of type 'long int *' (resp. 'int *') To make this test pass with any type of toolchain, this patch defines 'word_type' according to which libc is in use. 2023-05-23 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Support both definitions of int32_t. (cherry picked from commit d12d2aa4fccc76a9a08c8120c5e37d9cab8683e8)
2023-05-30libstdc++: Correct NTTP and simd_mask ctor callMatthias Kretz2-3/+67
Signed-off-by: Matthias Kretz <m.kretz@gsi.de> libstdc++-v3/ChangeLog: PR libstdc++/109822 * include/experimental/bits/simd.h (to_native): Use int NTTP as specified in PTS2. (to_compatible): Likewise. Add missing tag to call mask generator ctor. * testsuite/experimental/simd/pr109822_cast_functions.cc: New test. (cherry picked from commit 668d43502f465d48adbc1fe2956b979f36657e5f)
2023-05-30libstdc++: Simplify calculation of expected value in simd testMatthias Kretz1-5/+4
This avoids a failure on PR109964. Signed-off-by: Matthias Kretz <m.kretz@gsi.de> libstdc++-v3/ChangeLog: * testsuite/experimental/simd/tests/integer_operators.cc: Compute expected value differently to avoid getting turned into a vector shift. (cherry picked from commit 3e2689e568425f14d6728504ad6f5d32b90320ad)
2023-05-30libstdc++: Fix test assumptions on long and long doubleMatthias Kretz1-6/+24
Expect that long might not fit into the long double mantissa bits. Signed-off-by: Matthias Kretz <m.kretz@gsi.de> libstdc++-v3/ChangeLog: * testsuite/experimental/simd/tests/operator_cvt.cc: Make long double <-> (u)long conversion tests conditional on sizeof(long double) and sizeof(long). (cherry picked from commit 291549d43e823f163fa9961e42a751b5ce0d57fb)
2023-05-30libstdc++: Resolve -Wsign-compare issueMatthias Kretz1-1/+1
Signed-off-by: Matthias Kretz <m.kretz@gsi.de> libstdc++-v3/ChangeLog: * include/experimental/bits/simd_ppc.h (_S_bit_shift_left): Negative __y is UB, so prefer signed compare. (cherry picked from commit 1a1abec1d618cde709c585fcce89330bb33b07ac)
2023-05-30riscv: update riscv_asan_shadow_offsetAndreas Schwab1-4/+3
gcc/ PR target/110036 * config/riscv/riscv.cc (riscv_asan_shadow_offset): Update to match libsanitizer.
2023-05-30OpenMP: Improve C/C++ parsing error message [PR109999]Tobias Burnus14-23/+57
Replace error: expected '#pragma omp' clause before ... by the the more readable/clearer error: expected an OpenMP clause before ... (And likewise for '#pragma acc' and OpenACC.) PR c/109999 gcc/c/ChangeLog: * c-parser.cc (c_parser_oacc_all_clauses, c_parser_omp_all_clauses): Improve error wording. gcc/cp/ChangeLog: * parser.cc (cp_parser_oacc_all_clauses, cp_parser_omp_all_clauses): Improve error wording. gcc/testsuite/ChangeLog: * c-c++-common/goacc/asyncwait-1.c: Update dg-error. * c-c++-common/goacc/clauses-fail.c: Likewise. * c-c++-common/goacc/data-2.c: Likewise. * c-c++-common/gomp/declare-target-2.c: Likewise. * c-c++-common/gomp/directive-1.c: Likewise. * c-c++-common/gomp/loop-transforms/tile-1.c: Likewise. * c-c++-common/gomp/loop-transforms/tile-2.c: Likewise. * c-c++-common/gomp/loop-transforms/unroll-2.c: Likewise. * g++.dg/goacc/data-1.C: Likewise. (cherry picked from commit a899401404186843f38462c8fc9de733f19ce864) (However, the tile-1.c, tile-2.c, and unroll-2.c change is only here.)
2023-05-30amdgcn: Update mxnack entry in invoke.texiTobias Burnus3-7/+15
This is a backport of fixes from r14-1299-g366e3d30b8d5dc to OG13, which already contains the other changes (and more) due to commit 0229066ecb2 amdgcn: Support XNACK mode gcc/ * config/gcn/gcn.opt (mxnack=): Fix default value in the description line. * doc/invoke.texi (mxnack): Update to the on/off/any version.
2023-05-30libgomp: Honor OpenMP's nteams-var ICV as upper limit on num teams [PR109875]Tobias Burnus7-2/+247
The nteams-var ICV exists per device and can be set either via the routine omp_set_num_teams or as environment variable (OMP_NUM_TEAMS with optional _ALL/_DEV/_DEV_<num> suffix); it is default-initialized to zero. The number of teams created is described under the num_teams clause. If the clause is absent, the number of teams is implementation defined but at least one team must exist and, if nteams-var is positive, at most nteams-var teams may exist. The latter condition was not honored in a target region before this commit, such that too many teams were created. Already before this commit, both the num_teams([lower:]upper) clause (on the host and in target regions) and, only on the host, the nteams-var ICV were honored. And as only one teams is created for host fallback, unless the clause specifies otherwise, the nteams-var ICV was and is effectively honored. libgomp/ChangeLog: PR libgomp/109875 * config/gcn/target.c (GOMP_teams4): Honor nteams-var ICV. * config/nvptx/target.c (GOMP_teams4): Likewise. * testsuite/libgomp.c-c++-common/teams-nteams-icv-1.c: New test. * testsuite/libgomp.c-c++-common/teams-nteams-icv-2.c: New test. * testsuite/libgomp.c-c++-common/teams-nteams-icv-3.c: New test. * testsuite/libgomp.c-c++-common/teams-nteams-icv-4.c: New test. (cherry picked from commit ad0f80d945cc36fbb60fd1e04d90681d4302de8b)
2023-05-30nvptx: Add suppport for __builtin_nvptx_brev instrinsic.Tobias Burnus8-0/+336
This patch adds support for (a pair of) bit reversal intrinsics __builtin_nvptx_brev and __builtin_nvptx_brevll which perform 32-bit and 64-bit bit reversal (using nvptx's brev instruction) matching the __brev and __brevll instrinsics provided by NVidia's nvcc compiler. https://docs.nvidia.com/cuda/cuda-math-api/group__CUDA__MATH__INTRINSIC__INT.html 2023-05-21 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * config/nvptx/nvptx.cc (nvptx_expand_brev): Expand target builtin for bit reversal using brev instruction. (enum nvptx_builtins): Add NVPTX_BUILTIN_BREV and NVPTX_BUILTIN_BREVLL. (nvptx_init_builtins): Define "brev" and "brevll". (nvptx_expand_builtin): Expand NVPTX_BUILTIN_BREV and NVPTX_BUILTIN_BREVLL via nvptx_expand_brev function. * doc/extend.texi (Nvidia PTX Builtin-in Functions): New section, document __builtin_nvptx_brev{,ll}. gcc/testsuite/ChangeLog * gcc.target/nvptx/brev-1.c: New 32-bit test case. * gcc.target/nvptx/brev-2.c: Likewise. * gcc.target/nvptx/brevll-1.c: New 64-bit test case. * gcc.target/nvptx/brevll-2.c: Likewise. (cherry picked from commit c09471fbc7588db2480f036aa56a2403d3c03ae5)
2023-05-30libgomp: Fix up -static -fopenmp linking [PR109904]Tobias Burnus3-4/+13
When an OpenMP program with target regions is linked statically, it fails to link on various arches (doesn't when using recent glibc because it has libdl stuff in libc), because libgomp.a(target.o) uses dlopen/dlsym/dlclose, but we aren't linking against -ldl (unless user asked for that). We already have libgomp.spec so that we can supply extra libraries to link against in the -static case, this patch adds -ldl to that if plugins are supported. 2023-05-19 Jakub Jelinek <jakub@redhat.com> PR libgomp/109904 * configure.ac (link_gomp): Include also $DL_LIBS. * configure: Regenerated. (cherry picked from commit 9abc830247e547186a48caadca43f5372eae1195)
2023-05-30GCN: Silence unused-variable warningTobias Burnus2-2/+8
gcc/ChangeLog: * config/gcn/gcn.cc (gcn_vectorize_builtin_vectorized_function): Remove unused in_mode/in_n variables. (cherry picked from commit 124bc77ba9868db07d284b4dea31797da1468515)
2023-05-30'omp scan' struct block seq update for OpenMP 5.xTobias Burnus20-51/+593
While OpenMP 5.0 required a single structured block before and after the 'omp scan' directive, OpenMP 5.1 changed this to a 'structured block sequence, denoting 2 or more executable statements in OpenMP 5.1 (whoops!) and zero or more in OpenMP 5.2. This commit updates C/C++ to accept zero statements (but till requires the '{' ... '}' for the final-loop-body) and updates Fortran to accept zero or more than one statements. If there is no preceeding or succeeding executable statement, a warning is shown. gcc/c/ChangeLog: * c-parser.cc (c_parser_omp_scan_loop_body): Handle zero exec statements before/after 'omp scan'. gcc/cp/ChangeLog: * parser.cc (cp_parser_omp_scan_loop_body): Handle zero exec statements before/after 'omp scan'. gcc/fortran/ChangeLog: * openmp.cc (gfc_resolve_omp_do_blocks): Handle zero or more than one exec statements before/after 'omp scan'. * trans-openmp.cc (gfc_trans_omp_do): Likewise. libgomp/ChangeLog: * testsuite/libgomp.c-c++-common/scan-1.c: New test. * testsuite/libgomp.c/scan-23.c: New test. * testsuite/libgomp.fortran/scan-2.f90: New test. gcc/testsuite/ChangeLog: * g++.dg/gomp/attrs-7.C: Update dg-error/dg-warning. * gfortran.dg/gomp/loop-2.f90: Likewise. * gfortran.dg/gomp/reduction5.f90: Likewise. * gfortran.dg/gomp/reduction6.f90: Likewise. * gfortran.dg/gomp/scan-1.f90: Likewise. * gfortran.dg/gomp/taskloop-2.f90: Likewise. * c-c++-common/gomp/scan-6.c: New test. * gfortran.dg/gomp/scan-8.f90: New test. (cherry picked from commit 1c101fcfaac8f609d618f83b124bd50aea012132)
2023-05-30Merge remote-tracking branch 'origin/releases/gcc-13' into devel/omp/gcc-13Tobias Burnus33-371/+1112
Merge up to r13-7388-g8f1e18c75e032c2e84c4a4bc51b734c36b11c7fd (30th May 2023)
2023-05-30Daily bump.GCC Administrator1-1/+1
2023-05-29Daily bump.GCC Administrator3-1/+64
2023-05-29RISC-V: Add local user vsetvl instruction elimination [PR109547]Juzhe-Zhong4-3/+85
This patch is to enhance optimization for auto-vectorization. Before this patch: Loop: vsetvl a5,a2... vsetvl zero,a5... vle After this patch: Loop: vsetvl a5,a2 vle gcc/ChangeLog: PR target/109547 * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): New function. (vector_insn_info::skip_avl_compatible_p): Ditto. (vector_insn_info::merge): Remove default value. (pass_vsetvl::compute_local_backward_infos): Ditto. (pass_vsetvl::cleanup_insns): Add local vsetvl elimination. * config/riscv/riscv-vsetvl.h: Ditto. gcc/testsuite/ChangeLog: PR target/109547 * gcc.target/riscv/rvv/vsetvl/pr109547.c: New. * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Update scan condition. (cherry picked from commit d51f2456ee51bd59a79b4725ca0e488c25260bbf)
2023-05-29RISC-V: Fix wrong select_kind in riscv_compute_multilibKito Cheng1-3/+3
Seems like I screw up bare-metal toolchian multi lib selection during finxing linux multi-lib selction... gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_compute_multilib): Fix wrong select_kind... (cherry picked from commit 008cbecf622a413ebcc8b41a737f30fd7e2a1abf)
2023-05-29RISC-V: Suppress unused parameter warning in riscv-common.ccKito Cheng1-9/+3
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): Drop unused parameter. (riscv_select_multilib): Ditto. (riscv_compute_multilib): Update call site of riscv_select_multilib_by_abi and riscv_select_multilib_by_abi. (cherry picked from commit 7a7f6b26259d22115ee4813ce130622ad1073d16)
2023-05-29RISC-V: Handle multi-lib path correclty for linuxKito Cheng4-41/+100
RISC-V Linux encodes the ABI into the path, so in theory, we can only use that to select multi-lib paths, and no way to use different multi-lib paths between `rv32i/ilp32` and `rv32ima/ilp32`, we'll mapping both to `/lib/ilp32`. It's hard to do that with GCC's builtin multi-lib selection mechanism; builtin mechanism did the option string compare and then enumerate all possible reuse rules during the build time. However, it's impossible to RISC-V; we have a huge number of combinations of `-march`, so implementing a customized multi-lib selection becomes the only solution. Multi-lib configuration is only used for determines which ISA should be used when compiling the corresponding ABI variant after this patch. During the multi-lib selection stage, only consider -mabi as the only key to select the multi-lib path. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): New. (riscv_select_multilib): New. (riscv_compute_multilib): Extract logic to riscv_select_multilib and also handle select_by_abi. * config/riscv/elf.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Change it to select_by_abi_arch_cmodel from 1. * config/riscv/linux.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Define. * config/riscv/riscv-opts.h (enum riscv_multilib_select_kind): New. (cherry picked from commit 17d683d4d3dc95d13096ec52ad9937a2b011f9a4)
2023-05-29RISC-V: Fix ternary instruction attribute bugJuzhe-Zhong1-1/+1
Fix bug of vector.md which generate incorrect information to VSETVL PASS when testing FMA auto vectorization ternop-3.c. Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai> gcc/ChangeLog: * config/riscv/vector.md: Fix vimuladd instruction bug. (cherry picked from commit f8af48d8755018272cdb0cf2f250cf278829d7be)
2023-05-28Daily bump.GCC Administrator1-1/+1
2023-05-27Daily bump.GCC Administrator1-1/+1
2023-05-26REVERT: gomp/openmp-simd-8.f90: Remove .ASSUME tree-dump checkTobias Burnus2-1/+10
This OG12 patch was accidentally ported to OG13. The proper support is in GCC 13 but was not backported to OG12, hence, the fully GCC 13 version can be used. REVERTED: gcc/testsuite/ * gfortran.dg/gomp/openmp-simd-8.f90: Remove dump test.
2023-05-26Daily bump.GCC Administrator4-1/+125
2023-05-25target/104327: Allow more inlining between different optimization levels.Georg-Johann Lay1-0/+16
avr-common.cc introduces the following options that are set depending on optimization level: -mgas-isr-prologues, -mmain-is-OS-task and -fsplit-wide-types-early. The inliner thinks that different options disallow cross-optimization inlining, so provide can_inline_p. gcc/ PR target/104327 * config/avr/avr.cc (avr_can_inline_p): New static function. (TARGET_CAN_INLINE_P): Define to that function.
2023-05-25target/82931: Make a pattern more generic to match more bit-transfers.Georg-Johann Lay3-10/+52
There is already a pattern in avr.md that matches single-bit transfers from one register to another one, but it only handled bit 0 of 8-bit registers. This change makes that pattern more generic so it matches more of similar single-bit transfers. gcc/ PR target/82931 * config/avr/avr.md (*movbitqi.0): Rename to *movbit<mode>.0-6. Handle any bit position and use mode QISI. * config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost of 2 insns for bit-transfer of respective style. gcc/testsuite/ PR target/82931 * gcc.target/avr/pr82931.c: New test.
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