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2024-08-19AVX10.2 ymm rounding: Support vfnmsub{132,231,213}p{s,d,h} intrinsHu, Lin19-1/+273
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (<avx512>_fnmsub_<mode>_mask3<round_name>): Add condition check. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vfmulcph and vfnmadd{132,231,213}p{s,d,h} intrinsHu, Lin18-0/+363
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vfm{sub,subadd}{132,231,213}p{s,d,h} intrinsHu, Lin19-1/+533
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (<avx512>_fmsub_<mode>_mask<round_name>): Add condition check. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vfmaddcph and vfmaddsub{132,231,213}p{s,d,h} ↵Hu, Lin19-2/+366
intrins gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (<avx512>_fmaddsub_<mode>_mask<round_name>): Add condition check. (<avx512>_fmaddsub_<mode>_mask3<round_name>): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vfmadd{132,231,213}p{s,d,h} intrinsHu, Lin19-1/+268
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (<avx512>_fmadd_<mode>_mask3<round_name>): Add condition check. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: New test.
2024-08-19AVX10.2 ymm rounding: Support vfc{madd,mul}cph, vfixupimmp{s,d} intrinsHu, Lin111-2/+374
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V16HF_FTYPE_V16HF_V16HF_INT, V16HF_FTYPE_V16HF_V16HF_V16HF_INT, V16HF_FTYPE_V16HF_V16HF_V16HF_UQI_INT, V4DF_FTYPE_V4DF_V4DF_V4DI_INT_UQI_INT, V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI_INT. * config/i386/sse.md: (<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>): Add condition check. (<avx512>_fixupimm<mode>_mask<round_saeonly_name>): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: New test.
2024-08-19AVX10.2 ymm rounding: Support vcvt{,u}w2ph and vdivp{s,d,h} intrinsHu, Lin110-0/+396
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V16HF_FTYPE_V16HI_V16HF_UHI_INT. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-3.c: New test.
2024-08-19AVX10.2 ymm rounding: Support vcvttps2{,u}{dq,qq} and vcvtu{dq,qq}2p{s,d,h} ↵Hu, Lin19-13/+670
intrins gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md (unspec_fix_truncv8sfv8si2<mask_name>): Extend rounding control. (<mask_codefor>fixuns_trunc<mode><sseintvecmodelower>2<mask_name>): Ditto. (<mask_codefor>floatuns<sseintvecmodelower><mode>2<mask_name><round_name>): Add condition check. (fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>): Remove round_saeonly_name. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-2.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vcvttph2{,u}{dq,qq,w} intrinsHu, Lin110-5/+447
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md (avx512fp16_fix<fixunssuffix>_trunc<mode>2<mask_name>): Extend round control for 256bit. (unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<mask_name>): Ditto. (avx512fp16_fix<fixunssuffix>_trunc<mode>2<mask_name><round_saeonly_name>): Add condition check. * config/i386/subst.md (round_saeonly_mode_condition): Add V16HI check for 256bit. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-2.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vcvtqq2p{s,d,h} and vcvttpd2{,u}{dq,qq} intrinsHu, Lin112-14/+569
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V4DF_FTYPE_V4DI_V4DF_UQI_INT, V4SF_FTYPE_V4DI_V4SF_UQI_INT, V8HF_FTYPE_V4DI_V8HF_UQI_INT. * config/i386/sse.md: (avx512fp16_vcvt<floatsuffix>qq2ph_v4di_mask_round): New expand. (*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask): Extend round control and add "_1" suffix. (float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>): Add condition check. (float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>): Ditto. (float<floatunssuffix><mode><ssePSmode2lower>2<mask_name><round_name>): Limit suffix output. (unspec_fix_truncv4dfv4si2<mask_name>): Extend round control. (unspec_fixuns_truncv4dfv4si2<mask_name>): Ditto. * config/i386/subst.md (round_qq2pssuff): New iterator. (round_saeonly_suff): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-2.c: New test.
2024-08-19AVX10.2 ymm rounding: Support vcvtps2{,u}{dq,qq} intrinsHu, Lin112-5/+308
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V8SI_FTYPE_V8SF_V8SI_UQI_INT, V4DI_FTYPE_V4SF_V4DI_UQI_INT. * config/i386/sse.md (<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>): Extend to round. (<mask_codefor><avx512>_fixuns_notrunc<sf2simodelower><mode><mask_name><round_name>): Add round condition check. * config/i386/subst.md (round_constraint4): New. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vcvtph2{,u}w and vcvtps2p{d,hx} intrinsHu, Lin112-1/+304
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V16HI_FTYPE_V16HF_V16HI_UHI_INT, V4DF_FTYPE_V4SF_V4DF_UQI_INT V8HF_FTYPE_V8SF_V8HF_UQI_INT. * config/i386/sse.md (avx512fp16_vcvt<castmode>2ph_<mode><mask_name><round_name>): Add round condition check. * config/i386/subst.md (round_mode_condition): Add V16HI check for 256bit. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vcvtph2p{s,d,sx} and vcvtph2{,u}{dq,qq} intrinsHu, Lin112-9/+529
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V8SF_FTYPE_V8HF_V8SF_UQI_INT, V8SI_FTYPE_V8HF_V8SI_UQI_INT, V4DF_FTYPE_V8HF_V4DF_UQI_INT, V4DI_FTYPE_V8HF_V4DI_UQI_INT. * config/i386/sse.md: (avx512fp16_float_extend_ph<mode>2<mask_name><round_saeonly_name>): Add condition check. (avx512fp16_vcvtph2<sseintconvertsignprefix><sseintconvert>_<mode> <mask_name><round_name>): Ditto. (avx512fp16_float_extend_ph<mode>2<mask_name>): Extend round saeonly. (vcvtph2ps256<mask_name>): Ditto. * config/i386/subst.md (round_saeonly_applied): New condition. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add new macro test. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vcvtpd2{,u}{dq,qq} intrinsHu, Lin112-6/+303
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: Add new intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V4DI_FTYPE_V4DF_V4DI_UQI_INT, V4SI_FTYPE_V4DF_V4SI_UQI_INT. * config/i386/sse.md: (avx_cvtpd2dq256<mask_name>): Change name to avx_cvtpd2dq256<mask_name><round_name> and extend pattern to generate 256bit insns. (fixuns_notrunc<mode><si2dfmodelower>2<mask_name><round_name>): Add round_mode_condition. * config/i386/subst.md (round_pd2udqsuff): New iterator. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/sse-14.c: Add new macro test. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vcvtdq2p{s,h} and vcvtpd2p{s,h} intrinsHu, Lin112-16/+322
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: Add new intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V8SF_FTYPE_V8SI_V8SF_UQI_INT, V4SF_FTYPE_V4DF_V4SF_UQI_INT, V8HF_FTYPE_V8SI_V8HF_UQI_INT, V8HF_FTYPE_V4DF_V8HF_UQI_INT. * config/i386/sse.md: (avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode><mask_name><round_name>): Add condition check. (avx512fp16_vcvtpd2ph_v4df_mask_round): New expand. (*avx512fp16_vcvt<castmode>2ph_<mode>_mask): Change name to avx512fp16_vcvt<castmode>2ph_<mode>_mask<round_name>_1 and extend pattern to generate 256bit insns. (avx_cvtpd2ps256<mask_name>): Change name to avx_cvtpd2ps256<mask_name><round_name> and extend pattern to generate 256bit insns. * config/i386/subst.md (round_applied): New condition. (round_suff): New iterator. (round_mode_condition): Add V32HI check for 512bit. (round_saeonly_mode_condition): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/sse-14.c: Add new macro test. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Add test.
2024-08-19AVX10.2 ymm rounding: Support vadd{s,d,h} and vcmp{s,d,h} intrinsHu, Lin115-63/+558
gcc/ChangeLog: * config.gcc: Add avx10_2roundingintrin.h. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT, V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT, V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT, UQI_FTYPE_V4DF_V4DF_INT_UQI_INT, UHI_FTYPE_V16HF_V16HF_INT_UHI_INT, UQI_FTYPE_V8SF_V8SF_INT_UQI_INT. * config/i386/immintrin.h: Include avx10_2roundingintrin.h. * config/i386/sse.md: Change subst_attr name due to renaming. * config/i386/subst.md: (<round_mode512bit_condition>): Add condition check for avx10.2 rounding control 256bit intrins and renamed to ... (<round_mode_condition>): ...this. (round_saeonly_mode512bit_condition): Add condition check for avx10.2 rounding control 256 bit intris and renamed to ... (round_saeonly_mode_condition): ...this. * config/i386/avx10_2roundingintrin.h: New file. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add -mavx10.2 and new builtin test. * gcc.target/i386/avx-2.c: Ditto. * gcc.target/i386/sse-13.c: Add new tests. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: New test.
2024-08-19Daily bump.GCC Administrator5-1/+147
2024-08-18[PR rtl-optimization/115876] Avoid ubsan in ext-dce.ccJeff Law1-5/+25
This fixes two general ubsan issues in ext-dce, both related to use-side processsing of modes > DImode. In ext_dce_process_uses we can be presented with something like this as a use (subreg:SI (reg:TF) 12) That will result in an out of range shift for a HOST_WIDE_INT object. Where this happens is safe to just break from the SET context and process the subjects. This will ultimately result in seeing (reg:TF) and we'll mark all bit groups as live. In carry_backpropagate we can be presented with a TImode shift (for example) and the shift count can be > 63 for such a shift. This naturally trips ubsan as well as we're operating on 64 bit objects. We can just return mmask in this case noting that every bit group is live. The combination of these two fixes eliminates all the reported ubsan issues in ext-dce seen in a bootstrap and regression test on x86. While I was in there I went ahead and fixed the various hardcoded 63/64 values to be HOST_BITS_PER_WIDE_INT based. Bootstrapped and regression tested on x86 with no regressions. Also built with ubsan enabled and verified the build logs and testsuite logs don't call out any issues in ext-dce anymore. Pushing to the trunk. PR rtl-optimization/115876 gcc * ext-dce.cc (ext_dce_process_sets): Replace hardcoded 63/64 instances with HOST_BITS_PER_WIDE_INT based values. (carry_backpropagate): Handle modes with more bits than HOST_BITS_PER_WIDE_INT gracefully, avoiding undefined behavior. (ext_dce_process_uses): Handle subreg offsets which would result in ubsan shifts gracefully, avoiding undefined behavior.
2024-08-18libstdc++: Remove note from the GCC 4.0.1 daysGerald Pfeifer2-8/+2
libstdc++-v3: * doc/xml/manual/prerequisites.xml: Remove note from the GCC 4.0.1 days. * doc/html/manual/setup.html: Regenerate.
2024-08-18doc: Tweak gm2 mailing list addressGerald Pfeifer1-1/+1
gcc: * doc/gm2.texi (Contributing): Tweak gm2 mailing list address.
2024-08-18PHIOPT: move factor_out_conditional_operation over to use gimple_match_opAndrew Pinski4-38/+49
To start working on more with expressions with more than one operand, converting over to use gimple_match_op is needed. The added side-effect here is factor_out_conditional_operation can now support builtins/internal calls that has one operand without any extra code added. Note on the changed testcases: * pr87007-5.c: the test was testing testing for avoiding partial register stalls for the sqrt and making sure there is only one zero of the register before the branch, the phiopt would now merge the sqrt's so disable phiopt. Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: * gimple-match-exports.cc (gimple_match_op::operands_occurs_in_abnormal_phi): New function. * gimple-match.h (gimple_match_op): Add operands_occurs_in_abnormal_phi. * tree-ssa-phiopt.cc (factor_out_conditional_operation): Use gimple_match_op instead of manually extracting from/creating the gimple. gcc/testsuite/ChangeLog: * gcc.target/i386/pr87007-5.c: Disable phi-opt. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-08-18libgfortran: implement fpu-macppc for Darwin, support IEEE arithmeticSergey Fedorov2-0/+422
This allows to build and use IEEE modules on Darwin PowerPC. libgfortran/ChangeLog: * config/fpu-macppc.h (new file): initial support for powerpc-darwin. * configure.host: enable ieee_support for powerpc-darwin case, set fpu_host='fpu-macppc'. Signed-off-by: Sergey Fedorov <vital.had@gmail.com>
2024-08-18AVR: Tweak 16-bit addition with const that didn't get a LD_REGS register.Georg-Johann Lay1-2/+18
The 16-bit additions like addhi3 have two forms: One with a scratch:QI and one without, where the latter is required because reload cannot deal with a scratch when spill code pops a 16-bit addition. Passes like combine and fwprop1 may come up with the non-scratch version, which is sub-optimal in the case when the addition is performed in a NO_LD_REGS register because the operands will be spilled to LD_REGS. Having a scratch:QI at disposal can lead to better code with less spills. gcc/ * config/avr/avr.md (*add<mode>3_split) [!reload_completed]: Add a scratch:QI to 16-bit additions with constant.
2024-08-18AVR: ad target/116407 - Fix linker error "relocation truncated to fit".Georg-Johann Lay1-1/+1
PR target/116407 gcc/ * config/avr/avr.md (*dec-and-branchhi!=-1.l.clobber): Increase the additional jump offset to 2 words.
2024-08-18AVR: target/116407 - Fix linker error "relocation truncated to fit".Georg-Johann Lay5-9/+80
Some text peepholes output extra instructions prior to a branch instruction and that increase the jump offset of backward branches. PR target/116407 gcc/ * config/avr/avr-protos.h (avr_jump_mode): Add an int argument. * config/avr/avr.cc (avr_jump_mode): Add an int argument to increase the computed jump offset of backwards branches. * config/avr/avr.md (*dec-and-branchhi!=-1, *dec-and-branchsi!=-1): Increase the jump offset used by avr_jump_mode() as needed. gcc/testsuite/ * gcc.target/avr/torture/pr116407-2.c: New test. * gcc.target/avr/torture/pr116407-4.c: New test.
2024-08-18forwprop: Also dce from added statements from gimple_simplifyAndrew Pinski3-10/+39
This extends r14-3982-g9ea74d235c7e78 to also include the newly added statements since some of them might be dead too (due to the way match and simplify works). This was noticed while working on adding a new match and simplify pattern where a new statement that got added was not being used. Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: * gimple-fold.cc (mark_lhs_in_seq_for_dce): New function. (replace_stmt_with_simplification): Call mark_lhs_in_seq_for_dce right before inserting the sequence. (fold_stmt_1): Add dce_worklist argument, update call to replace_stmt_with_simplification. (fold_stmt): Add dce_worklist argument, update call to fold_stmt_1. (fold_stmt_inplace): Update call to fold_stmt_1. * gimple-fold.h (fold_stmt): Add bitmap argument. * tree-ssa-forwprop.cc (pass_forwprop::execute): Update call to fold_stmt. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-08-18RISC-V: Implement the quad and oct .SAT_TRUNC for scalarPan Li11-2/+195
This patch would like to implement the quad and oct .SAT_TRUNC pattern in the riscv backend. Aka: Form 1: #define DEF_SAT_U_TRUC_FMT_1(NT, WT) \ NT __attribute__((noinline)) \ sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \ { \ bool overflow = x > (WT)(NT)(-1); \ return ((NT)x) | (NT)-overflow; \ } DEF_SAT_U_TRUC_FMT_1(uint16_t, uint64_t) Before this patch: 4 │ __attribute__((noinline)) 5 │ uint16_t sat_u_truc_uint64_t_to_uint16_t_fmt_1 (uint64_t x) 6 │ { 7 │ _Bool overflow; 8 │ short unsigned int _1; 9 │ short unsigned int _2; 10 │ short unsigned int _3; 11 │ uint16_t _6; 12 │ 13 │ ;; basic block 2, loop depth 0 14 │ ;; pred: ENTRY 15 │ overflow_5 = x_4(D) > 65535; 16 │ _1 = (short unsigned int) x_4(D); 17 │ _2 = (short unsigned int) overflow_5; 18 │ _3 = -_2; 19 │ _6 = _1 | _3; 20 │ return _6; 21 │ ;; succ: EXIT 22 │ 23 │ } After this patch: 3 │ 4 │ __attribute__((noinline)) 5 │ uint16_t sat_u_truc_uint64_t_to_uint16_t_fmt_1 (uint64_t x) 6 │ { 7 │ uint16_t _6; 8 │ 9 │ ;; basic block 2, loop depth 0 10 │ ;; pred: ENTRY 11 │ _6 = .SAT_TRUNC (x_4(D)); [tail call] 12 │ return _6; 13 │ ;; succ: EXIT 14 │ 15 │ } The below tests suites are passed for this patch 1. The rv64gcv fully regression test. 2. The rv64gcv build with glibc gcc/ChangeLog: * config/riscv/iterators.md (ANYI_QUAD_TRUNC): New iterator for quad truncation. (ANYI_OCT_TRUNC): New iterator for oct truncation. (ANYI_QUAD_TRUNCATED): New attr for truncated quad modes. (ANYI_OCT_TRUNCATED): New attr for truncated oct modes. (anyi_quad_truncated): Ditto but for lower case. (anyi_oct_truncated): Ditto but for lower case. * config/riscv/riscv.md (ustrunc<mode><anyi_quad_truncated>2): Add new pattern for quad truncation. (ustrunc<mode><anyi_oct_truncated>2): Ditto but for oct. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Adjust the expand dump check times. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto. * gcc.target/riscv/sat_arith_data.h: Add test helper macros. * gcc.target/riscv/sat_u_trunc-4.c: New test. * gcc.target/riscv/sat_u_trunc-5.c: New test. * gcc.target/riscv/sat_u_trunc-6.c: New test. * gcc.target/riscv/sat_u_trunc-run-4.c: New test. * gcc.target/riscv/sat_u_trunc-run-5.c: New test. * gcc.target/riscv/sat_u_trunc-run-6.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-08-18RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]Pan Li13-22/+112
For QI/HImode of .SAT_ADD, the operands may be sign-extended and the high bits of Xmode may be all 1 which is not expected. For example as below code. signed char b[1]; unsigned short c; signed char *d = b; int main() { b[0] = -40; c = ({ (unsigned short)d[0] < 0xFFF6 ? (unsigned short)d[0] : 0xFFF6; }) + 9; __builtin_printf("%d\n", c); } After expanding we have: ;; _6 = .SAT_ADD (_3, 9); (insn 8 7 9 (set (reg:DI 143) (high:DI (symbol_ref:DI ("d") [flags 0x86] <var_decl d>))) (nil)) (insn 9 8 10 (set (reg/f:DI 142) (mem/f/c:DI (lo_sum:DI (reg:DI 143) (symbol_ref:DI ("d") [flags 0x86] <var_decl d>)) [1 d+0 S8 A64])) (nil)) (insn 10 9 11 (set (reg:HI 144 [ _3 ]) (sign_extend:HI (mem:QI (reg/f:DI 142) [0 *d.0_1+0 S1 A8]))) "test.c":7:10 -1 (nil)) The convert from signed char to unsigned short will have sign_extend rtl as above. And finally become the lb insn as below: lb a1,0(a5) // a1 is -40, aka 0xffffffffffffffd8 lui a0,0x1a addi a5,a1,9 slli a5,a5,0x30 srli a5,a5,0x30 // a5 is 65505 sltu a1,a5,a1 // compare 65505 and 0xffffffffffffffd8 => TRUE The sltu try to compare 65505 and 0xffffffffffffffd8 here, but we actually want to compare 65505 and 65496 (0xffd8). Thus we need to clean up the high bits to ensure this. The below test suites are passed for this patch: * The rv64gcv fully regression test. PR target/116278 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Add new func impl to zero extend rtx. (riscv_expand_usadd): Leverage above func to cleanup operands 0 and remove the special handing for SImode in RV64. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_u_add-11.c: Adjust asm check body. * gcc.target/riscv/sat_u_add-15.c: Ditto. * gcc.target/riscv/sat_u_add-19.c: Ditto. * gcc.target/riscv/sat_u_add-23.c: Ditto. * gcc.target/riscv/sat_u_add-3.c: Ditto. * gcc.target/riscv/sat_u_add-7.c: Ditto. * gcc.target/riscv/sat_u_add_imm-11.c: Ditto. * gcc.target/riscv/sat_u_add_imm-15.c: Ditto. * gcc.target/riscv/sat_u_add_imm-3.c: Ditto. * gcc.target/riscv/sat_u_add_imm-7.c: Ditto. * gcc.target/riscv/pr116278-run-1.c: New test. * gcc.target/riscv/pr116278-run-2.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-08-18RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3Pan Li7-0/+116
This patch would like to add test cases for the unsigned scalar .SAT_TRUNC form 3. Aka: Form 3: #define DEF_SAT_U_TRUC_FMT_3(NT, WT) \ NT __attribute__((noinline)) \ sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \ { \ WT max = (WT)(NT)-1; \ return x <= max ? (NT)x : (NT) max; \ } DEF_SAT_U_TRUC_FMT_3 (uint32_t, uint64_t) The below test is passed for this patch. * The rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add test helper macros. * gcc.target/riscv/sat_u_trunc-13.c: New test. * gcc.target/riscv/sat_u_trunc-14.c: New test. * gcc.target/riscv/sat_u_trunc-15.c: New test. * gcc.target/riscv/sat_u_trunc-run-13.c: New test. * gcc.target/riscv/sat_u_trunc-run-14.c: New test. * gcc.target/riscv/sat_u_trunc-run-15.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-08-18RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2Pan Li7-0/+116
This patch would like to add test cases for the unsigned scalar .SAT_TRUNC form 2. Aka: Form 2: #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \ NT __attribute__((noinline)) \ sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \ { \ WT max = (WT)(NT)-1; \ return x > max ? (NT) max : (NT)x; \ } DEF_SAT_U_TRUC_FMT_2 (uint32_t, uint64_t) The below test is passed for this patch. * The rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add test helper macros. * gcc.target/riscv/sat_u_trunc-7.c: New test. * gcc.target/riscv/sat_u_trunc-8.c: New test. * gcc.target/riscv/sat_u_trunc-9.c: New test. * gcc.target/riscv/sat_u_trunc-run-7.c: New test. * gcc.target/riscv/sat_u_trunc-run-8.c: New test. * gcc.target/riscv/sat_u_trunc-run-9.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-08-18Daily bump.GCC Administrator4-1/+137
2024-08-17[committed] Avoid right shifting signed value on ext-dce.ccJeff Law1-1/+1
This is analogous to a prior patch to ext-dce which fixes propagation of sign bits, but this time for the saturating variants. I'd held off fixing those because I wanted the time to look at that code (since we don't have a testcase for it as far as I know). Not surprisingly, putting an abort on that path and running an x86 bootstrap and testsuite run, it never triggers. Of course not a lot of code tries to do saturating shifts. Anyway, bootstrapped and regression tested on x86_64. Pushing to the trunk. Thanks for everyone's patience. gcc/ * ext-dce.cc (carry_backpropagate): Cast mask to HOST_WIDE_INT before shifting.
2024-08-17t-rtems: add rv32imf architecture to the RTEMS multilib for RISC-VKevin Kirspel1-2/+3
The attach patch is specific to the RTEMS RISC-V architecture multilib which is controlled by the t-rtems file in the gcc/config/riscv/ directory. The patch file was created from the gcc-13.3.0 branch. It was successfully tested within RTEMS Source Builder. gcc/ * config/riscv/t-rtems: Add ilp32f multilib.
2024-08-17Adjust v850 rotate expander to allow more cases for V850E3V5Jeff Law1-1/+3
The recent if-conversion changes tripped a failure on the v850 port. The core underlying issue is that while the if-conversion code tries to do the right thing with noce_can_force_operand to determine if it can force an arbitrary operand into a register, it's not really a sufficient check. Essentially for arithmetic codes, it checks the operands. If the operands are force-able and there's a code_to_optab mapping, then it returns true. code_to_optab doesn't actually check anything other than the existence of a mapping in the target. If the target pattern has restrictions enforced by the condition or it's an expander that is allowed to FAIL, then noce_can_force_operand to be true, even though we may not be able to directly force the operand into a register. This came up on the v850 when we had an operand that was a rotate by a constant number of bits (I don't remember the count, all that's important about it was the count was not 8 or 16). The v850 port has this define_expand: > (define_expand "rotlsi3" > [(parallel [(set (match_operand:SI 0 "register_operand" "") > (rotate:SI (match_operand:SI 1 "register_operand" "") > (match_operand:SI 2 "const_int_operand" ""))) > (clobber (reg:CC CC_REGNUM))])] > "(TARGET_V850E_UP)" > { > if (INTVAL (operands[2]) != 16) > FAIL; > }) So the only rotate count allowed is 16 (there's a similar HI rotate with a count of 8). AFAICT the rotate patterns are allowed to FAIL. So naturally the expander fails and we get a testsuite regression: > Tests that now fail, but worked before (4 tests): > > v850-sim/-mgcc-abi/-msoft-float/-mv850e3v5: gcc: gcc.c-torture/execute/20100805-1.c -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions (test for excess errors) > v850-sim/-mgcc-abi/-msoft-float/-mv850e3v5: gcc: gcc.c-torture/execute/20100805-1.c -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions (test for excess errors) > v850-sim/-msoft-float/-mv850e3v5: gcc: gcc.c-torture/execute/20100805-1.c -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions (test for excess errors) > v850-sim/-mv850e3v5: gcc: gcc.c-torture/execute/20100805-1.c -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions (test for excess errors) This patch works around the problem by allowing the rotates in additional cases, particularly for the V850E3V5+ variants which have a general rotate capability. But let's be clear, this is just a workaround and I expect we're going to have to revisit the code to test if an operand can be forced into a register. gcc/ * config/v850/v850.md (rotlsi3): Allow more cases for V850E3V5+.
2024-08-17RISC-V: Fix ICE for vector single-width integer multiply-add intrinsicsJin Ma3-40/+92
When rs1 is the immediate 0, the following ICE occurs: error: unrecognizable insn: (insn 8 5 12 2 (set (reg:RVVM1DI 134 [ <retval> ]) (if_then_else:RVVM1DI (unspec:RVVMF64BI [ (const_vector:RVVMF64BI repeat [ (const_int 1 [0x1]) ]) (reg/v:DI 137 [ vl ]) (const_int 2 [0x2]) repeated x2 (const_int 0 [0]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (plus:RVVM1DI (mult:RVVM1DI (vec_duplicate:RVVM1DI (const_int 0 [0])) (reg/v:RVVM1DI 136 [ vs2 ])) (reg/v:RVVM1DI 135 [ vd ])) (reg/v:RVVM1DI 135 [ vd ]))) gcc/ChangeLog: * config/riscv/vector.md: Allow scalar operand to be 0. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-7.c: New test. * gcc.target/riscv/rvv/base/bug-8.c: New test.
2024-08-17[RISC-V][PR target/116282] Stabilize pattern conditionsJeff Law5-31/+71
So as expected the core problem with target/116282 is that the cost of certain constant synthesis cases varied depending on whether or not we're allowed to generate new pseudos or not. That in turn meant that in obscure cases an insn might change from recognizable to unrecognizable and triggers the observed failure. So we need to keep the cost stable, at least when called from a pattern's condition. So we pass another boolean down when necessary. I've tried to keep API fallout minimized. Built and tested on rv32 in my tester. Let's see what pre-commit testing has to say though 🙂 Note this will also require a minor change to the in-flight constant synthesis work. PR target/116282 gcc/ * config/riscv/riscv-protos.h (riscv_const_insns): Add new argument. * config/riscv/riscv.cc (riscv_build_integer): Add new argument ALLOW_NEW_PSEUDOS. Pass it down to recursive calls and check it before using synthesis which allows new registers to be created. (riscv_split_integer_cost): Pass new argument to riscv_build_integer. (riscv_integer_cost): Add ALLOW_NEW_PSEUDOS argument, pass it down to riscv_build_integer. (riscv_legitimate_constant_p): Pass new argument to riscv_const_insns. (riscv_const_insns): New argment ALLOW_NEW_PSEUDOS. Pass it down to riscv_integer_cost and riscv_const_insns. (riscv_split_const_insns): Pass new argument to riscv_const_insns. (riscv_move_integer, riscv_rtx_costs): Similarly. * config/riscv/riscv.md (shadd with costly constant): Pass new argument to riscv_const_insns. * config/riscv/bitmanip.md (and with costly constant): Pass new argument to riscv_const_insns. gcc/testsuite/ * gcc.target/riscv/pr116282.c: New test.
2024-08-17RISC-V: Bugfix for RVV rounding intrinsic ICE in function checkerJin Ma4-3/+20
When compiling an interface for rounding of type 'vfloat16*' without using zvfh or zvfhmin, it is not enough to use FLOAT_MODE_P because the type does not support it. Although the subsequent riscv_validate_vector_type checks will still fail and throw exceptions, I don't think we should have ICE here. internal compiler error: in check, at config/riscv/riscv-vector-builtins-shapes.cc:444 10 | return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl); | ^~~~~~ 0x4191794 internal_error(char const*, ...) /iothome/jin.ma/code/master/gcc/gcc/diagnostic-global-context.cc:491 0x416ebf5 fancy_abort(char const*, int, char const*) /iothome/jin.ma/code/master/gcc/gcc/diagnostic.cc:1772 0x220aae6 riscv_vector::build_frm_base::check(riscv_vector::function_checker&) const /iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins-shapes.cc:444 0x2205323 riscv_vector::function_checker::check() /iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins.cc:4414 gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_vector_float_type_p): New. * config/riscv/riscv-vector-builtins.cc (function_instance::any_type_float_p): Use riscv_vector_float_type_p instead of FLOAT_MODE_P for judgment. * config/riscv/riscv.cc (riscv_vector_int_type_p): Change static to extern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-9.c: New test.
2024-08-17RISC-V: Bugfix incorrect operand for vwsll auto-vectPan Li3-0/+28
This patch would like to fix one ICE when rv64gcv_zvbb for vwsll. Consider below example. void vwsll_vv_test (short *restrict dst, char *restrict a, int *restrict b, int n) { for (int i = 0; i < n; i++) dst[i] = a[i] << b[i]; } It will hit the vwsll pattern with following operands. operand 0 -> (reg:RVVMF2HI 146 [ vect__7.13 ]) operand 1 -> (reg:RVVMF4QI 165 [ vect_cst__33 ]) operand 2 -> (reg:RVVM1SI 171 [ vect_cst__36 ]) According to the ISA, operand 2 should be the same as operand 1. Aka operand 2 should have RVVMF4QI mode as above. Thus, add quad truncation for operand 2 before emit vwsll. The below test suites are passed for this patch. * The rv64gcv fully regression test. PR target/116280 gcc/ChangeLog: * config/riscv/autovec-opt.md: Add quad truncation to align the mode requirement for vwsll. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr116280-1.c: New test. * gcc.target/riscv/rvv/base/pr116280-2.c: New test.
2024-08-17RISC-V: Add auto-vect pattern for vector rotate shiftFeng Wang4-0/+142
This patch add the vector rotate shift pattern for auto-vect. With this patch, the scalar rotate shift can be automatically vectorized into vector rotate shift. gcc/ChangeLog: * config/riscv/autovec.md (v<bitmanip_optab><mode>3): Add new define_expand pattern for vector rotate shift. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: New test. * gcc.target/riscv/rvv/autovec/binop/vrolr-run.c: New test. * gcc.target/riscv/rvv/autovec/binop/vrolr-template.h: New test.
2024-08-17libstdc++: Update references to gcc.gnu.org/onlinedocsGerald Pfeifer13-17/+17
libstdc++-v3: * doc/xml/manual/abi.xml: Update reference to gcc.gnu.org/onlinedocs. * doc/xml/manual/concurrency_extensions.xml (interface): Ditto. * doc/xml/manual/extensions.xml: Ditto. * doc/xml/manual/parallel_mode.xml: Ditto. * doc/xml/manual/shared_ptr.xml: Ditto. * doc/xml/manual/using_exceptions.xml: Ditto. And change GNU GCC to GCC. * doc/html/manual/abi.html: Regenerate. * doc/html/manual/ext_concurrency_impl.html: Ditto. * doc/html/manual/ext_demangling.html: Ditto. * doc/html/manual/memory.html: Ditto. * doc/html/manual/parallel_mode_design.html: Ditto. * doc/html/manual/parallel_mode_using.html: Ditto. * doc/html/manual/using_exceptions.html: Ditto.
2024-08-17doc: Tweak PIM4 linkGerald Pfeifer1-1/+1
gcc: * doc/gm2.texi (What is GNU Modula-2): Tweak PIM4 link.
2024-08-17libstdc++: Tweak links to installation docsGerald Pfeifer2-5/+6
libstdc++v-3: * doc/xml/manual/prerequisites.xml: Tweak two links to installation docs. Fix grammar. * doc/html/manual/setup.html: Regenerate.
2024-08-17doc: Tweak link to gm2 list archiveGerald Pfeifer1-1/+1
Without the trailing slash we incur a "301 Moved Permanently". gcc: * doc/gm2.texi (Community): Tweak link to gm2 list archive.
2024-08-17AVR: target/116390 - Fix an avrtiny asm out template.Georg-Johann Lay2-15/+86
PR target/116390 gcc/ * config/avr/avr.cc (avr_out_movsi_mr_r_reg_disp_tiny): Fix output templates for the reg_base == reg_src and reg_src == reg_base - 2 cases. gcc/testsuite/ * gcc.target/avr/torture/pr116390.c: New test.
2024-08-17RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]曾治金2-2/+34
This patch is to fix the bug (BugId:116305) introduced by the commit bd93ef for risc-v target. The commit bd93ef changes the chunk_num from 1 to TARGET_MIN_VLEN/128 if TARGET_MIN_VLEN is larger than 128 in riscv_convert_vector_bits. So it changes the value of BYTES_PER_RISCV_VECTOR. For example, before merging the commit bd93ef and if TARGET_MIN_VLEN is 256, the value of BYTES_PER_RISCV_VECTOR should be [8, 8], but now [16, 16]. The value of riscv_bytes_per_vector_chunk and BYTES_PER_RISCV_VECTOR are no longer equal. Prologue will use BYTES_PER_RISCV_VECTOR.coeffs[1] to estimate the vlenb register value in riscv_legitimize_poly_move, and dwarf2cfi will also get the estimated vlenb register value in riscv_dwarf_poly_indeterminate_value to calculate the number of times to multiply the vlenb register value. So need to change the factor from riscv_bytes_per_vector_chunk to BYTES_PER_RISCV_VECTOR, otherwise we will get the incorrect dwarf information. The incorrect example as follow: ``` csrr    t0,vlenb slli    t1,t0,1 sub     sp,sp,t1 .cfi_escape 0xf,0xb,0x72,0,0x92,0xa2,0x38,0,0x34,0x1e,0x23,0x50,0x22 ``` The sequence '0x92,0xa2,0x38,0' means the vlenb register, '0x34' means the literal 4, '0x1e' means the multiply operation. But in fact, the vlenb register value just need to multiply the literal 2. PR target/116305 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Take BYTES_PER_RISCV_VECTOR for *factor instead of riscv_bytes_per_vector_chunk. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/scalable_vector_cfi.c: New test. Signed-off-by: Zhijin Zeng <zhijin.zeng@spacemit.com>
2024-08-17Daily bump.GCC Administrator7-1/+155
2024-08-16Write CodeView information about stack variablesMark Harmstone2-6/+122
Outputs CodeView S_REGREL32 symbols for unoptimized local variables that are stored on the stack. This includes a change to dwarf2out.cc to make it easier to extract the function frame base without having to worry about the function prologue or epilogue. gcc/ * dwarf2codeview.cc (enum cv_sym_type): Add S_REGREL32. (write_fbreg_variable): New function. (write_unoptimized_local_variable): Add fblock parameter, and handle DW_OP_fbreg locations. (write_unoptimized_function_vars): Add fbloc parameter. (write_function): Extract frame base from DWARF. * dwarf2out.cc (convert_cfa_to_fb_loc_list): Output simplified frame base information for CodeView.
2024-08-16Write CodeView information about enregistered variablesMark Harmstone1-0/+1188
Outputs CodeView S_REGISTER symbols, representing local variables or parameters that are held in a register. gcc/ * dwarf2codeview.cc (enum cv_sym_type): Add S_REGISTER. (enum cv_x86_register): New type. (enum cv_amd64_register): New type. (dwarf_reg_to_cv): New function. (write_s_register): New function. (write_unoptimized_local_variable): Handle parameters and DW_OP_reg* location types.
2024-08-16Write CodeView information about local static variablesMark Harmstone1-0/+258
Outputs CodeView S_LDATA32 symbols, for static variables within functions, along with S_BLOCK32 and S_END for the beginning and end of lexical blocks. gcc/ * dwarf2codeview.cc (enum cv_sym_type): Add S_END and S_BLOCK32. (write_local_s_ldata32): New function. (write_unoptimized_local_variable): New function. (write_s_block32): New function. (write_s_end): New function. (write_unoptimized_function_vars): New function. (write_function): Call write_unoptimized_function_vars.
2024-08-16Fix maybe-uninitialized CodeView LF_INDEX warningMark Harmstone1-2/+2
Initialize last_type to 0 to silence two spurious maybe-uninitialized warnings. We issue an LF_INDEX continuation subtype for any LF_FIELDLISTs that overflow, so LF_INDEXes will always have a subtype preceding them (and thus last_type will always be set). gcc/ * dwarf2codeview.cc (get_type_num_enumeration_type): Initialize last_type to 0. (get_type_num_struct): Likewise.
generated by cgit v1.1 at 2025-09-23 12:58:03 +0000