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2023-09-15ada: Generate runtime restrictions list when the standard library is suppressedPatrick Bernardi1-6/+4
With the introduction of Jorvik support into the light-tasking runtime comes the requirement to detect voliations of runtime restrictions (for example Max_Entry_Queue_Length) where previously they could be hard coded in the runtime. This means we now need the binder to populate System.System.Restrictions.Run_Time_Restrictions when the standard library is suppressed. gcc/ada/ * bindgen.adb (Gen_Adainit): Generate restrictions when standard library is suppressed. (Gen_Output_File_Ada): Ditto. (Gen_Restrictions): Ditto.
2023-09-15ada: Fix internal error on misaligned component with variable nominal sizeEric Botcazou1-3/+6
The back-end cannot handle this kind of components even when they are small. gcc/ada/ * exp_util.adb (Component_May_Be_Bit_Aligned): Do not return false for a small component of a record type with a variant part.
2023-09-15ada: Fix internal error on aggregate nested in container aggregateEric Botcazou1-7/+9
This handles the case where a component association is present. gcc/ada/ * exp_aggr.adb (Convert_To_Assignments): In the case of a component association, call Is_Container_Aggregate on the parent's parent. (Expand_Array_Aggregate): Likewise.
2023-09-15ada: Remove GNAT Pro details regarding moldKévin Le Gouguec1-22/+0
gcc/ada/ * doc/gnat_ugn/building_executable_programs_with_gnat.rst: Remove extended discussion regarding mold run-time dependencies; packaging changes in GNAT Pro have made them obsolete.
2023-09-15ada: Fix internal error on expression function with Refined_Post aspectEric Botcazou1-0/+3
This occurs when the expression function calls a protected function and the -gnata switch is specified, because the compiler wrongly freezes the called function when analyzing the expression function, a fallout of the wrapping scheme used for the Post and Refined_Post aspects. gcc/ada/ * sem_res.adb (Resolve_Call): When the target is an entity, do not freeze it if the current scope is the inner wrapper function built for an expression function with a Post or Refined_Post aspect.
2023-09-15ada: Clean up scope depth and related code (tech debt)Bob Duff13-84/+231
The main point of this patch is to remove the special case for Atree.F_Scope_Depth_Value in the Assert that Field_Present in Get_Field_Value. Pulling on that thread leads to lots of related cleanup. gcc/ada/ChangeLog: * atree.adb (Node_Kind_Table): Specify parameter explicitly in GNAT.Table instantiations. Use fully qualified references instead of relying on use clauses. (Get_Field_Value): Remove special case for F_Scope_Depth_Value. That is, enable the Field_Present check in that case. (It was already enabled for all other fields.) Violations of this check were already fixed. (Print_Node_Statistics): Sort the output in decreasing order of frequencies. (Print_Field_Statistics): Likewise (sort). * accessibility.adb (Accessibility_Level): Pass Allow_Alt_Model in recursive calls. Apparently, an oversight. (Innermost_Master_Scope_Depth): Need to special-case the 'Old attribute and allocators. * einfo-utils.ads (Scope_Depth): Use Scope_Kind_Id to get predicate checks. (Scope_Depth_Set): Likewise. (Scope_Depth_Default_0): Likewise. * einfo-utils.adb: As for spec. * frontend.adb (Frontend): Remove unnecessary "return;". * gen_il-types.ads (Scope_Kind): New union type. * gen_il-gen-gen_entities.adb (Scope_Kind): New union type. * sem.ads: Move "with Einfo.Entities;" from body to spec. (Scope_Stack_Entry): Declare Entity to be of Scope_Kind_Id to get predicate checks. We had previously been putting non-scopes on the scope stack; this prevents such anomalies. * sem.adb: Move "with Einfo.Entities;" from body to spec. * sem_ch8.ads: Move "with Einfo.Entities;" from body to spec. Add "with Types;". (Push_Scope): Use Scope_Kind_Id to get predicate checks. * sem_ch8.adb: Move "with Einfo.Entities;" from body to spec. Add "with Types;". (Push_Scope): Use Scope_Kind_Id to get predicate checks. (Pop_Scope): Use Scope_Kind_Id on popped entity to get predicate checks. This prevents anomalies where a scope pushed onto the stack is later mutated to a nonscope before being popped. * sem_util.ads (Find_Enclosing_Scope): Add postcondition to ensure that the enclosing scope of a node N is not the same node N. Clearly, N does not enclose itself. * sem_util.adb (Find_Enclosing_Scope): There were several bugs where Find_Enclosing_Scope(N) = N. For example, if N is an entity, then we would typically go up to its declaration, and then back down to the Defining_Entity of the declaration, which is N itself. There were other cases where Find_Enclosing_Scope of an entity disagreed with Scope. Clearly, Find_Enclosing_Scope and Scope should agree (when both are defined). Such bugs caused latent bugs in accessibility.adb related to 'Old, and fixing bugs here caused such bugs to be revealed. These are fixed by calling Scope when N is an entity. Co-authored-by: Ronan Desplanques <desplanques@adacore.com>
2023-09-15ada: Crash on creation of extra formals on type extensionJavier Miranda3-66/+24
Revert previous patch and fix the pending issue. gcc/ada/ * accessibility.ads (Needs_Result_Accessibility_Extra_Formal): Removed. * accessibility.adb (Needs_Result_Accessibility_Level_Param): Removed. (Needs_Result_Accessibility_Extra_Formal): Removed. (Needs_Result_Accessibility_Level): Revert previous patch. * sem_ch6.adb (Parent_Subprogram): Handle function overriding an enumeration literal. (Create_Extra_Formals): Ensure that the parent subprogram has all its extra formals.
2023-09-15RISC-V: Fix using wrong mode to get reduction insn vlmaxLehua Ding3-54/+60
This patch fix using wrong mode when emit vlmax reduction insn. We should use src operand instead dest operand (which always LMUL=m1) to get the vlmax length. This patch alse remove dest_mode and mask_mode from insn_expander constructor, which can be geted by insn_flags. gcc/ChangeLog: * config/riscv/riscv-protos.h (enum insn_flags): Change name. (enum insn_type): Ditto. * config/riscv/riscv-v.cc (get_mask_mode_from_insn_flags): Removed. (emit_vlmax_insn): Adjust. (emit_nonvlmax_insn): Adjust. (emit_vlmax_insn_lra): Adjust. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: New test.
2023-09-15fortran: Remove reference count update [PR108957]Mikael Morin2-3/+20
Remove one reference count incrementation following the assignment of a symbol pointer to a local variable. Most symbol pointers are "weak" pointer and don't need any reference count update when they are assigned, and it is especially the case of local variables. This fixes a memory leak with the testcase from the PR (not included). PR fortran/108957 gcc/fortran/ChangeLog: * gfortran.h (gfc_symbol): Add comment documenting reference counting. * parse.cc (parse_interface): Remove reference count incrementation.
2023-09-15test: Block SLP check of slp-35.c for vect_strided5Juzhe-Zhong1-1/+1
gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-35.c: Block SLP check for vect_strided5 targets.
2023-09-15test: Block SLP check of slp-34.c for vect_strided5Juzhe-Zhong1-1/+1
Since RISC-V use vsseg5 which is the vect_store_lanes with stride 5 if failed on RISC-V. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-34.c: Block check for vect_strided5.
2023-09-15test: Block vect_strided5 for slp-34-big-array.c SLP checkJuzhe-Zhong1-1/+1
If failed on RISC-V since it use vect_store_lanes with array 5. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-34-big-array.c: Block SLP check for vect_strided5.
2023-09-15test: Block slp-16.c check for target support vect_strided6Juzhe-Zhong2-2/+2
This testcase FAIL in RISC-V because RISC-V support vect_load_lanes with 6. FAIL: gcc.dg/vect/slp-16.c -flto -ffat-lto-objects scan-tree-dump-times vect "vectorizing stmts using SLP" 2 FAIL: gcc.dg/vect/slp-16.c scan-tree-dump-times vect "vectorizing stmts using SLP" 2 Since it use vlseg6 (vect_load_lanes with array size = 6) gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-16.c: Block vect_strided6. * lib/target-supports.exp: Add strided type.
2023-09-15test: Isolate slp-1.c check of target supports vect_strided5Juzhe-Zhong1-2/+2
This test failed in RISC-V: FAIL: gcc.dg/vect/slp-1.c -flto -ffat-lto-objects scan-tree-dump-times vect "vectorizing stmts using SLP" 4 FAIL: gcc.dg/vect/slp-1.c scan-tree-dump-times vect "vectorizing stmts using SLP" 4 Because this loop: /* SLP with unrolling by 8. */ for (i = 0; i < N; i++) { out[i*5] = 8; out[i*5 + 1] = 7; out[i*5 + 2] = 81; out[i*5 + 3] = 28; out[i*5 + 4] = 18; } is using vect_load_lanes with array size = 5. instead of SLP. When we adjust the COST of LANES load store, then it will use SLP. gcc/testsuite/ChangeLog: * gcc.dg/vect/slp-1.c: Add vect_stried5.
2023-09-15test: Remove XPASS for RISCVJuzhe-Zhong1-3/+3
Like ARM SVE, this test cause FAILs of XPASS: XPASS: gcc.dg/Wstringop-overflow-47.c pr97027 (test for warnings, line 72) XPASS: gcc.dg/Wstringop-overflow-47.c pr97027 (test for warnings, line 77) XPASS: gcc.dg/Wstringop-overflow-47.c pr97027 note (test for warnings, line 68) on RISC-V gcc/testsuite/ChangeLog: * gcc.dg/Wstringop-overflow-47.c: Add riscv.
2023-09-15RISC-V: Refactor expand_reduction and cleanup enum reduction_typeLehua Ding4-63/+79
This patch refactors expand_reduction, remove the reduction_type argument and add insn_flags argument to determine the passing of the operands. ops has also been modified to restrict it to only two cases and to remove operand that are not in use. gcc/ChangeLog: * config/riscv/autovec-opt.md: Adjust. * config/riscv/autovec.md: Ditto. * config/riscv/riscv-protos.h (enum class): Delete enum reduction_type. (expand_reduction): Adjust expand_reduction prototype. * config/riscv/riscv-v.cc (need_mask_operand_p): New helper function. (expand_reduction): Refactor expand_reduction.
2023-09-15libstdc++: Fix constraints for std::variant default constructorJonathan Wakely2-12/+23
The standard says the default ctor should be constrained, not deleted. Our use of a defaulted default ctor and _Enable_default_constructor base class results in it being deleted. libstdc++-v3/ChangeLog: * include/std/variant (variant): Remove derivation from _Enable_default_constructor base class. (variant::variant()): Constrain. * testsuite/20_util/variant/default_ctor.cc: New test.
2023-09-15libstdc++: Remove non-void static assertions in variant's std::get [PR111172]Jonathan Wakely1-4/+0
A void template argument would cause a substitution failure when trying to form a reference for the return type, so the function body would never be instantiated. libstdc++-v3/ChangeLog: PR libstdc++/111172 * include/std/variant (get<T>): Remove !is_void static assertions.
2023-09-15libstdc++: Add operator bool to <charconv> result types (P2497R0)Jonathan Wakely6-148/+212
C++26 adds these convenience conversions. libstdc++-v3/ChangeLog: * include/bits/version.def (to_chars): Define new value for C++26. * include/bits/version.h: Regenerate. * include/std/charconv (to_chars_result::operator bool): New function. (from_chars_result::operator bool): New function. * testsuite/20_util/to_chars/version.cc: Update expected value. * testsuite/20_util/from_chars/result.cc: New test. * testsuite/20_util/to_chars/result.cc: New test.
2023-09-15aarch64: Fix loose ldpstp check [PR111411]Richard Sandiford2-5/+60
aarch64_operands_ok_for_ldpstp contained the code: /* One of the memory accesses must be a mempair operand. If it is not the first one, they need to be swapped by the peephole. */ if (!aarch64_mem_pair_operand (mem_1, GET_MODE (mem_1)) && !aarch64_mem_pair_operand (mem_2, GET_MODE (mem_2))) return false; But the requirement isn't just that one of the accesses must be a valid mempair operand. It's that the lower access must be, since that's the access that will be used for the instruction operand. gcc/ PR target/111411 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp): Require the lower memory access to a mem-pair operand. gcc/testsuite/ PR target/111411 * gcc.dg/rtl/aarch64/pr111411.c: New test.
2023-09-15LoongArch: Reimplement multilib build option handling.Yang Yujie12-123/+137
Library build options from --with-multilib-list used to be processed with *self_spec, which missed the driver's initial canonicalization. This caused limitations on CFLAGS override and the use of driver-only options like -m[no]-lsx. The problem is solved by promoting the injection rules of --with-multilib-list options to the first element of DRIVER_SELF_SPECS, to make them execute before the canonialization. The library-build options are also hard-coded in the driver and can be used conveniently by the builders of other non-gcc libraries via the use of -fmultiflags. Bootstrapped and tested on loongarch64-linux-gnu. ChangeLog: * config-ml.in: Remove unneeded loongarch clause. * configure.ac: Register custom makefile fragments mt-loongarch-* for loongarch targets. * configure: Regenerate. config/ChangeLog: * mt-loongarch-mlib: New file. Pass -fmultiflags when building target libraries (FLAGS_FOR_TARGET). * mt-loongarch-elf: New file. * mt-loongarch-gnu: New file. gcc/ChangeLog: * config.gcc: Pass the default ABI via TM_MULTILIB_CONFIG. * config/loongarch/loongarch-driver.h: Invoke MLIB_SELF_SPECS before the driver canonicalization routines. * config/loongarch/loongarch.h: Move definitions of CC1_SPEC etc. to loongarch-driver.h * config/loongarch/t-linux: Move multilib-related definitions to t-multilib. * config/loongarch/t-multilib: New file. Inject library build options obtained from --with-multilib-list. * config/loongarch/t-loongarch: Same.
2023-09-15RISC-V: Support combine extend and reduce sum to widen reduce sumLehua Ding10-27/+321
This patch add combine pattern to combine extend and reduce sum to widen reduce sum. The pattern in autovec.md was adjusted as needed. Note that the current vectorization cannot generate reduce operand which is LMUL=M8, because this means that we need an LMUL=M16 for the extended operand, which is currently not possible. So I've added VI_QHS_NO_M8 and VF_HS_NO_M8 mode iterator, which exclude mode which is LMUL=M8. PR target/111381 gcc/ChangeLog: * config/riscv/autovec-opt.md (*reduc_plus_scal_<mode>): New combine pattern. (*fold_left_widen_plus_<mode>): Ditto. (*mask_len_fold_left_widen_plus_<mode>): Ditto. * config/riscv/autovec.md (reduc_plus_scal_<mode>): Change from define_expand to define_insn_and_split. (fold_left_plus_<mode>): Ditto. (mask_len_fold_left_plus_<mode>): Ditto. * config/riscv/riscv-v.cc (expand_reduction): Support widen reduction. * config/riscv/vector-iterators.md (UNSPEC_WREDUC_SUM): Add new iterators and attrs. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: New test.
2023-09-15Daily bump.GCC Administrator7-1/+1000
2023-09-14diagnostics: support multithreaded diagnostic pathsDavid Malcolm14-184/+734
This patch extends the existing diagnostic_path class so that as well as list of events, there is a list of named threads, with each event being associated with one of the threads. No GCC diagnostics take advantage of this, but GCC plugins may find a use for this; an example is provided in the testsuite. Given that there is still a single list of events within a diagnostic_path, the events in a diagnostic_path have a specific global ordering even if they are in multiple threads. Within the SARIF serialization, the patch adds the "executionOrder" property to threadFlowLocation objects (SARIF v2.1.0 3.38.11). This is 1-based in order to match the human-readable numbering of events shown in messages emitted by pretty-printer.cc's "%@". With -fdiagnostics-path-format=separate-events, the threads are not shown. With -fdiagnostics-path-format=inline-events, the threads and the per-thread stack activity are tracked and visalized separately. An example can be seen in the testsuite. gcc/analyzer/ChangeLog: * checker-event.h (checker_event::get_thread_id): New. * checker-path.h (class checker_path): Implement thread-related vfuncs via a single simple_diagnostic_thread instance named "main". gcc/ChangeLog: * diagnostic-event-id.h (diagnostic_thread_id_t): New typedef. * diagnostic-format-sarif.cc (class sarif_thread_flow): New. (sarif_thread_flow::sarif_thread_flow): New. (sarif_builder::make_code_flow_object): Reimplement, creating per-thread threadFlow objects, populating them with the relevant events. (sarif_builder::make_thread_flow_object): Delete, moving the code into sarif_builder::make_code_flow_object. (sarif_builder::make_thread_flow_location_object): Add "path_event_idx" param. Use it to set "executionOrder" property. * diagnostic-path.h (diagnostic_event::get_thread_id): New pure-virtual vfunc. (class diagnostic_thread): New. (diagnostic_path::num_threads): New pure-virtual vfunc. (diagnostic_path::get_thread): New pure-virtual vfunc. (diagnostic_path::multithreaded_p): New decl. (simple_diagnostic_event::simple_diagnostic_event): Add optional thread_id param. (simple_diagnostic_event::get_thread_id): New accessor. (simple_diagnostic_event::m_thread_id): New. (class simple_diagnostic_thread): New. (simple_diagnostic_path::simple_diagnostic_path): Move definition to diagnostic.cc. (simple_diagnostic_path::num_threads): New. (simple_diagnostic_path::get_thread): New. (simple_diagnostic_path::add_thread): New. (simple_diagnostic_path::add_thread_event): New. (simple_diagnostic_path::m_threads): New. * diagnostic-show-locus.cc (layout::layout): Add pretty_printer param for overriding the context's printer. (diagnostic_show_locus): Likwise. * diagnostic.cc (simple_diagnostic_path::simple_diagnostic_path): Move here from diagnostic-path.h. Add main thread. (simple_diagnostic_path::num_threads): New. (simple_diagnostic_path::get_thread): New. (simple_diagnostic_path::add_thread): New. (simple_diagnostic_path::add_thread_event): New. (simple_diagnostic_event::simple_diagnostic_event): Add thread_id param and use it to initialize m_thread_id. Reformat. * diagnostic.h: Add pretty_printer param for overriding the context's printer. * tree-diagnostic-path.cc: Add #define INCLUDE_VECTOR. (can_consolidate_events): Compare thread ids. (class per_thread_summary): New. (event_range::event_range): Add per_thread_summary arg. (event_range::print): Add "pp" param and use it rather than dc's printer. (event_range::m_thread_id): New field. (event_range::m_per_thread_summary): New field. (path_summary::multithreaded_p): New. (path_summary::get_events_for_thread_id): New. (path_summary::m_per_thread_summary): New field. (path_summary::m_thread_id_to_events): New field. (path_summary::get_or_create_events_for_thread_id): New. (path_summary::path_summary): Create per_thread_summary instances as needed and associate the event_range instances with them. (base_indent): Move here from print_path_summary_as_text. (per_frame_indent): Likewise. (class thread_event_printer): New, adapted from parts of print_path_summary_as_text. (print_path_summary_as_text): Make static. Reimplement to moving most of existing code to class thread_event_printer, capturing state as per-thread as appropriate. (default_tree_diagnostic_path_printer): Add missing 'break' on final case. gcc/testsuite/ChangeLog: * gcc.dg/plugin/diagnostic-test-paths-multithreaded-inline-events.c: New test. * gcc.dg/plugin/diagnostic-test-paths-multithreaded-sarif.c: New test. * gcc.dg/plugin/diagnostic-test-paths-multithreaded-separate-events.c: New test. * gcc.dg/plugin/diagnostic_plugin_test_paths.c: Add support for generating multithreaded paths. * gcc.dg/plugin/plugin.exp: Add the new tests. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-09-14analyzer: fix missing return in compatible_epath_pDavid Malcolm1-0/+8
gcc/analyzer/ChangeLog: * diagnostic-manager.cc (compatible_epath_p): Fix missing return. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-09-14analyzer: use unique_ptr for rejected_constraintDavid Malcolm7-45/+45
gcc/analyzer/ChangeLog: * diagnostic-manager.cc (process_worklist_item): Use std::unique_ptr rather than plain rejected_constraint *. * engine.cc (exploded_path::feasible_p): Likewise. (feasibility_state::maybe_update_for_edge): Likewise. * exploded-graph.h (feasibility_problem::feasibility_problem): Likewise. (feasibility_problem::~feasibility_problem): Delete. (feasibility_problem::m_rc): Use std::unique_ptr. (feasibility_state::maybe_update_for_edge): Likewise. * feasible-graph.cc (feasible_graph::add_feasibility_problem): Likewise. * feasible-graph.h (class infeasible_node): Likewise. (feasible_graph::add_feasibility_problem): Likewise. * region-model.cc (region_model::add_constraint): Likewise. (region_model::maybe_update_for_edge): Likewise. (region_model::apply_constraints_for_gcond): Likewise. (region_model::apply_constraints_for_gswitch): Likewise. (region_model::apply_constraints_for_exception): Likewise. * region-model.h (class region_model): Likewise for decls. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-09-14ggc, jit: forcibly clear GTY roots in jitDavid Malcolm5-1/+37
As part of Antoyo's work on supporting LTO in rustc_codegen_gcc, he noticed an ICE inside libgccjit when compiling certain rust files. Debugging libgccjit showed that outdated information from a previous in-memory compile was referring to ad-hoc locations in the previous compile's line_table. The issue turned out to be the function decls in internal_fn_fnspec_array from the previous compile keeping alive the symtab nodes for these functions, and from this finding other functions in the previous compile, walking their CFGs, and finding ad-hoc data pointers in an edge with a location_t using ad-hoc data from the previous line_table instance, and thus a use-after-free ICE attempting to use this ad-hoc data. Previously in toplev::finalize we've fixed global state "piecemeal" by calling out to individual source_name_cc_finalize functions. However, it occurred to me that we have run-time information on where the GTY-marked pointers are. Hence this patch takes something of a "big hammer" approach by adding a new ggc_common_finalize that walks the GC roots, zeroing all of the pointers. I stepped through this in the debugger and observed that, in particular, this correctly zeroes the internal_fn_fnspec_array at the end of a libgccjit compile. Antoyo reports that this fixes the ICE for him. Doing so uncovered an ICE with libgccjit in dwarf2cfi.cc due to reuse of global variables from the previous compile, which this patch also fixes. I noticed that in ggc_mark_roots when clearing deletable roots we only clear the initial element in each gcc_root_tab_t. This looks like a latent bug to me, which the patch fixes. That said, there don't seem to be any deletable roots where the number of elements != 1. gcc/ChangeLog: * dwarf2cfi.cc (dwarf2cfi_cc_finalize): New. * dwarf2out.h (dwarf2cfi_cc_finalize): New decl. * ggc-common.cc (ggc_mark_roots): Multiply by rti->nelt when clearing the deletable gcc_root_tab_t. (ggc_common_finalize): New. * ggc.h (ggc_common_finalize): New decl. * toplev.cc (toplev::finalize): Call dwarf2cfi_cc_finalize and ggc_common_finalize. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-09-14modula2: Add missing comments to M2CaseList.mod and add testcasesGaius Mulley10-32/+58
This patch adds procedure block comments to M2CaseList.mod, changes date values to use unique digits and add a new test case. gcc/m2/ChangeLog: * gm2-compiler/M2CaseList.mod (NewRanges): Add block comment. (NewSet): Add block comment. (DisplayRanges): Add block comment. (IncludeElement): Add block comment. (IncludeElements): Add block comment. (appendString): Add block comment. (appendEnum): Add block comment. (appendTree): Add block comment. (SubrangeErrors): Add block comment. gcc/testsuite/ChangeLog: * gm2/switches/case/fail/subrangecase.mod: Replace 19 with 17. * gm2/switches/case/fail/subrangecase2.mod: Ditto. * gm2/switches/case/fail/subrangecase3.mod: Ditto. * gm2/switches/case/fail/subrangecase4.mod: Ditto. * gm2/switches/case/pass/subrangecase.mod: Ditto. * gm2/switches/case/pass/subrangecase2.mod: Ditto. * gm2/switches/case/pass/subrangecase3.mod: Ditto. * gm2/switches/case/pass/subrangecase4.mod: Ditto. * gm2/switches/case/fail/calendar.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-09-14gcc: xtensa: use salt/saltu in xtensa_expand_sccMax Filippov4-1/+77
gcc/ * config/xtensa/predicates.md (xtensa_cstoresi_operator): Add unsigned comparisons. * config/xtensa/xtensa.cc (xtensa_expand_scc): Add code generation of salt/saltu instructions. * config/xtensa/xtensa.h (TARGET_SALT): New macro. * config/xtensa/xtensa.md (salt, saltu): New instruction patterns.
2023-09-14modula2: introduce case checking when switching on subrangesGaius Mulley15-78/+506
This patch extends the -Wcase-enum warning to catch missing elements from subranges. The patch also includes removal of unused parameters from M2SymInit.mod and M2CaseList.mod. gcc/m2/ChangeLog: * gm2-compiler/M2CaseList.mod (appendString): New procedure. (appendEnum): Re-implement. (NoOfSetElements): New procedure function. (isPrintableChar): New procedure function. (appendTree): New procedure. (SubrangeErrors): New procedure. (EmitMissingRangeErrors): Call SubrangeErrors if appropriate. * gm2-compiler/M2SymInit.mod (SetFieldInitializedNo): Avoid using a temporary variable once. (IsLocalVar): Comment out. (RecordContainsVarient): Remove fieldtype. (GenerateNoteFlow): Remove lst parameter. (CheckDeferredRecordAccess): Remove lst parameter. (CheckUnary): Remove lst parameter. Remove procSym. (CheckBinary): Remove lst parameter. Remove procSym. (CheckIndrX): Remove lst parameter. Remove procSym. (CheckXIndr): Remove bblst and procSym parameters. (CheckRecordField): Remove procSym, op1tok, op2tok and op2. (CheckBecomes): Remove procSym and bblst. (CheckComparison): Remove procSym and bblst. (CheckAddr): Remove procSym parameter. * gm2-gcc/m2expr.cc (m2expr_CSTIntToString): New function. (m2expr_CSTIntToChar): New function. * gm2-gcc/m2expr.def (CSTIntToString): New procedure function declaration. (CSTIntToChar): New procedure function declaration. * gm2-gcc/m2expr.h (m2expr_CSTIntToChar): New prototype. (m2expr_CSTIntToString): New prototype. gcc/testsuite/ChangeLog: * gm2/switches/case/fail/subrangecase.mod: New test. * gm2/switches/case/fail/subrangecase2.mod: New test. * gm2/switches/case/fail/subrangecase3.mod: New test. * gm2/switches/case/fail/subrangecase4.mod: New test. * gm2/switches/case/fail/subrangecase5.mod: New test. * gm2/switches/case/fail/subrangecase6.mod: New test. * gm2/switches/case/pass/subrangecase.mod: New test. * gm2/switches/case/pass/subrangecase2.mod: New test. * gm2/switches/case/pass/subrangecase3.mod: New test. * gm2/switches/case/pass/subrangecase4.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-09-14[RA]: Improve cost calculation of pseudos with equivalencesVladimir N. Makarov1-9/+2
RISCV target developers reported that RA can spill pseudo used in a loop although there are enough registers to assign. It happens when the pseudo has an equivalence outside the loop and the equivalence is not merged into insns using the pseudo. IRA sets up that memory cost to zero when the pseudo has an equivalence and it means that the pseudo will be probably spilled. This approach worked well for i686 (different approaches were benchmarked long time ago on spec2k). Although common sense says that the code is wrong and this was confirmed by RISCV developers. I've tried the following patch on I7-9700k and it improved spec17 fp by 1.5% (21.1 vs 20.8) although spec17 int is a bit worse by 0.45% (8.54 vs 8.58). The average generated code size is practically the same (0.001% difference). In the future we probably need to try more sophisticated cost calculation which should take into account that the equiv can not be combined in usage insns and the costs of reloads because of this. gcc/ChangeLog: * ira-costs.cc (find_costs_and_classes): Decrease memory cost by equiv savings.
2023-09-14RISC-V: Refactor vector reduction patternsLehua Ding6-152/+152
This patch adjust reduction patterns struct, change it from: (any_reduc:VI (vec_duplicate:VI (vec_select:<VEL> (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) (match_operand:VI 3 "register_operand" " vr, vr")) to: (unspec:<V_LMUL1> [ (match_operand:VI 3 "register_operand" " vr, vr") (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr") ] ANY_REDUC) The reason for the change is that the semantics of the previous pattern is incorrect. GCC does not have a standard rtx code to express the reduction calculation process. It makes more sense to use UNSPEC. Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred (unspec, mode)), so that all reduction patterns can have a uniform icode name. After this adjust, widen_reducop and widen_freducop are redundant. gcc/ChangeLog: * config/riscv/autovec.md: Change rtx code to unspec. * config/riscv/riscv-protos.h (expand_reduction): Change prototype. * config/riscv/riscv-v.cc (expand_reduction): Change prototype. * config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop): Removed. (class widen_freducop): Removed. * config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs. * config/riscv/vector.md (@pred_reduc_<reduc><mode>): Change name. (@pred_<reduc_op><mode>): New name. (@pred_widen_reduc_plus<v_su><mode>): Change name. (@pred_reduc_plus<order><mode>): Change name. (@pred_widen_reduc_plus<order><mode>): Change name.
2023-09-14RISC-V: Cleanup redundant reduction patterns after refactor vector modeLehua Ding4-334/+101
This patch cleanups redundant reduction patterns after Juzhe change vector mode from fixed-size to scalable-size. For example, whether it is zvl32b, zvl64b, zvl128b, RVVM1SI indicates that it occupies a vector register. Therefore, it is easy to map vector modes to LMUL1 vector modes with define_mode_attr without creating a separate pattern for each LMUL1 Mode. For example, this patch can combine four patterns (@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>, @pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode> @pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>, @pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>) to a single pattern @pred_reduc_<reduc><mode>. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_reduction): Adjust call. * config/riscv/riscv-vector-builtins-bases.cc: Adjust call. * config/riscv/vector-iterators.md: New iterators and attrs. * config/riscv/vector.md (@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>): Removed. (@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>): Removed. (@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>): Removed. (@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>): Removed. (@pred_reduc_<reduc><mode>): Added. (@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>): Removed. (@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>): Removed. (@pred_widen_reduc_plus<v_su><mode>): Added. (@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>): Removed. (@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>): Removed. (@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>): Removed. (@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>): Removed. (@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>): Removed. (@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>): Removed. (@pred_reduc_plus<order><mode>): Added. (@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>): Removed. (@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>): Removed. (@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>): Removed. (@pred_widen_reduc_plus<order><mode>): Added.
2023-09-14aarch64: Restore SVE WHILE costingRichard Sandiford2-17/+32
AArch64 previously costed WHILELO instructions on the first call to add_stmt_cost. This was because, at the time, only add_stmt_cost had access to the loop_vec_info. However, after the AVX512 changes, we only calculate the masks later. This patch moves the WHILELO costing to finish_cost, which is in any case a more logical place for it to be. It also means that we can check the final decision about whether to use predicated loops. gcc/ * config/aarch64/aarch64.cc (aarch64_vector_costs::analyze_loop_info): Move WHILELO handling to... (aarch64_vector_costs::finish_cost): ...here. Check whether the vectorizer has decided to use a predicated loop. gcc/testsuite/ * gcc.target/aarch64/sve/cost_model_15.c: New test.
2023-09-14MATCH: Support `(a != (CST+1)) & (a > CST)` optimizationsAndrew Pinski4-3/+111
Even though this is done via reassocation, match can support these with a simple change to detect that the difference is just one. This allows to optimize these earlier and even during phiopt for an example. This patch adds the following cases: (a != (CST+1)) & (a > CST) -> a > (CST+1) (a != (CST-1)) & (a < CST) -> a < (CST-1) (a == (CST-1)) | (a >= CST) -> a >= (CST-1) (a == (CST+1)) | (a <= CST) -> a <= (CST+1) Canonicalizations of comparisons causes this case to show up more. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. PR tree-optimization/106164 gcc/ChangeLog: * match.pd (`(X CMP1 CST1) AND/IOR (X CMP2 CST2)`): Expand to support constants that are off by one. gcc/testsuite/ChangeLog: * gcc.dg/pr21643.c: Update test now that match does the combing of the comparisons. * gcc.dg/tree-ssa/cmpbit-5.c: New test. * gcc.dg/tree-ssa/phi-opt-35.c: New test.
2023-09-14Improve error message for if with an else part while in switchAndrew Pinski1-0/+2
While writing some match.pd code, I was trying to figure out why I was getting an `expected ), got (` error message while writing an if statement with an else clause. For switch statements, the if statements cannot have an else clause so it would be better to have a decent error message saying that explictly. OK? Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * genmatch.cc (parser::parse_result): For an else clause of an if statement inside a switch, error out explictly.
2023-09-14RISC-V: Support VLS modes mask operationsJuzhe-Zhong13-55/+907
This patch support mask operations (comparison and logical). This patch reduce these FAILs of "vect" testsuite: FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects scan-tree-dump dce7 "<=\\s*.+{ 255,.+}" FAIL: gcc.dg/vect/vect-bic-bitmask-12.c scan-tree-dump dce7 "<=\\s*.+{ 255,.+}" FAIL: gcc.dg/vect/vect-bic-bitmask-23.c -flto -ffat-lto-objects scan-tree-dump dce7 "<=\\s*.+{ 255, 15, 1, 65535 }" FAIL: gcc.dg/vect/vect-bic-bitmask-23.c scan-tree-dump dce7 "<=\\s*.+{ 255, 15, 1, 65535 }" Full regression passed (with reducing 4 FAILs). gcc/ChangeLog: * config/riscv/autovec-opt.md: Add VLS mask modes. * config/riscv/autovec.md (@vcond_mask_<mode><vm>): Remove @. (vcond_mask_<mode><vm>): Add VLS mask modes. * config/riscv/vector.md: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS tests. * gcc.target/riscv/rvv/autovec/vls/cmp-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/cmp-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/cmp-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/cmp-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/cmp-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/cmp-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/mask-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/mask-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/mask-3.c: New test.
2023-09-14libstdc++: Add testcase for std::make_integer_sequence bug [PR111357]Jonathan Wakely1-0/+34
The compiler bug has been fixed on trunk, but this adds a regression test for the library component. libstdc++-v3/ChangeLog: PR c++/111357 * testsuite/20_util/integer_sequence/pr111357.cc: New test.
2023-09-14libstdc++: Support dg-additional-files in testsJonathan Wakely6-13/+20
Some tests rely on text files with specific content being present in the test directory. This has historically been done by copying testsuite/data/*.tst and testsuite/data/*.txt to the test dir at the start, in the libstdc++_init procedure. Some tests modify their data files, so if the same test runs more than once in the same directory the second and subsequent tests will see the modified files, and FAIL because the content of the file is not in the expected state. This change adds support for the dg-additional-files directive from the main compiler testsuite and changes v3_target_compile to copy the specified files to the directory where the test will run. This ensures that a fresh copy of the files is present each time the test runs. Eventually all tests could be transitioned to use dg-additional-files and then libstdc++_init could be changed to remove the initial copy of all files. This change only adds dg-additional-files to the tests that modify their files and FAIL when re-run in the same directory. The tests that rely on additional data files have comments containing the strings "@require@" and "@diff@" which seem to be related to the libstdc++-v3/mkcheck.in testing script that was removed in 2003. Those comments can be used to find tests that should be migrated to use the new dg-additional-files support, and then the comments can be removed. libstdc++-v3/ChangeLog: * testsuite/27_io/basic_filebuf/seekoff/char/1-io.cc: Use dg-additional-files. Remove @require@ and @diff@ comments. * testsuite/27_io/basic_filebuf/seekoff/char/2-io.cc: Likewise. * testsuite/27_io/basic_filebuf/seekpos/char/1-io.cc: Likewise. * testsuite/27_io/basic_filebuf/seekpos/char/2-io.cc: Likewise. * testsuite/lib/dg-options.exp (v3_additional_files): New global variable. (dg-additional-files): New proc. * testsuite/lib/libstdc++.exp (v3_target_compile): Copy additional files to test directory.
2023-09-14libstdc++: Remove some more unconditional uses of atomicsJonathan Wakely4-19/+38
These atomics cause linker errors on arm4t where __sync_synchronize is not defined. For single-threaded targets we don't need the atomics. libstdc++-v3/ChangeLog: * include/experimental/io_context (io_context) [!_GLIBCXX_HAS_GTHREADS]: Use a plain integer for _M_work_count for single-threaded targets. * include/experimental/memory_resource (__get_default_resource) [!_GLIBCXX_HAS_GTHREADS]: Use unsynchronized type for single-threaded targets. * src/c++17/default_resource.h: Adjust preprocessor conditions to match memory_resource.cc. * src/c++17/memory_resource.cc [!_GLIBCXX_HAS_GTHREADS] (atomic_mem_res): Use unsynchronized type for single-threaded targets.
2023-09-14ada: Improve detection of deactivated code for warnings with -gnatwtYannick Moy2-9/+167
Switch -gnatwt is used in GNAT to track deleted code. It can be emitted by GNAT on code that is intentionally deactivated for a given configuration. The current test to suppress spurious warnings is not complex enough to detect all such cases. Now improved, by using the same test as used in GNATprove to suppress warnings related to a "statically disabled condition which evaluates to a given value", as described in SPARK UG 7.3.2. gcc/ada/ * exp_util.adb (Is_Statically_Disabled): New function to detect a "statically disabled condition which evaluates to a given value", as described in SPARK UG 7.3.2. (Kill_Dead_Code): Call the new function Is_Statically_Disabled for conditions of if statements. * exp_util.ads (Is_Statically_Disabled): New function spec.
2023-09-14ada: Assertion failure on expansion of record with invariantJavier Miranda1-2/+10
gcc/ada/ * exp_util.adb (Process_Record_Component): Adjust assertion on the availablity of the invariant procedure; required because the invariant procedure is built by the expander, and hence it is not available compiling generic units or when the sources have errors, since expansion is then disabled.
2023-09-14ada: Assertion failure on calculation of Large_Max_Size_MutableJavier Miranda1-1/+3
gcc/ada/ * sem_util.adb (Large_Max_Size_Mutable): Protect access to attribute Is_Array_Type.
2023-09-14ada: Assertion failure on for-of loop iterating on selected componentJavier Miranda1-2/+7
gcc/ada/ * sem_util.adb (Is_Dependent_Component_Of_Mutable_Object): Protect access to Entity attribute and add missing code to check function selector in a prefix form call.
2023-09-14ada: Fix late finalization for function call in delta aggregateEric Botcazou1-2/+6
The problem occurs at library level because the temporary created for the function call lives in the elaboration routine but is finalized only when the package itself is. It turns out that there is no need for this temporary, since the expansion of delta aggregates already creates a (properly finalized) temporary. gcc/ada/ * exp_ch6.adb (Expand_Ctrl_Function_Call): Also do nothing for the expression of a delta aggregate.
2023-09-14ada: Fix premature finalization in loop over limited iterable containerEric Botcazou1-40/+48
This happens when the iterable container is obtained as the result of a call to a function that is a subprogram parameter of a generic construct. gcc/ada/ * exp_util.adb (Initialized_By_Aliased_BIP_Func_Call): Make the name matching more robust.
2023-09-14ada: Assertion failure adding extra formals to late overriding subp.Javier Miranda1-1/+2
gcc/ada/ * sem_ch6.adb (Parent_Subprogram): Complete assertion.
2023-09-14tree-optimization/111294 - better DCE after forwpropRichard Biener5-13/+28
The following adds more aggressive DCE to forwprop to clean up dead stmts when folding a stmt leaves some operands unused. The patch uses simple_dce_from_worklist for this purpose, queueing original operands before substitution and folding, but only if we folded the stmt. This removes one dead stmt biasing threading costs in a later pass but it doesn't resolve the optimization issue in the PR yet. PR tree-optimization/111294 * tree-ssa-forwprop.cc (pass_forwprop::execute): Track operands that eventually become dead and use simple_dce_from_worklist to remove their definitions if they did so. * gcc.dg/tree-ssa/evrp10.c: Adjust. * gcc.dg/tree-ssa/evrp6.c: Likewise. * gcc.dg/tree-ssa/forwprop-31.c: Likewise. * gcc.dg/tree-ssa/neg-cast-3.c: Likewise.
2023-09-14aarch64: Coerce addresses to be suitable for LD1RQRichard Sandiford3-5/+47
In the following test: svuint8_t ld(uint8_t *ptr) { return svld1rq(svptrue_b8(), ptr + 2); } ptr + 2 is a valid address for an Advanced SIMD load, but not for an SVE load. We therefore ended up generating: ldr q0, [x0, 2] dup z0.q, z0.q[0] This patch makes us generate LD1RQ for that case too. It takes the slightly old-school approach of making the predicate broader than the constraint. That is: any valid memory address is accepted as an operand before RA. If the instruction remains during RA, LRA will coerce the address to match the constraint. If the instruction gets split before RA, the splitter will load invalid addresses into a scratch register. gcc/ * config/aarch64/aarch64-sve.md (@aarch64_vec_duplicate_vq<mode>_le): Accept all nonimmediate_operands, but keep the existing constraints. If the instruction is split before RA, load invalid addresses into a temporary register. * config/aarch64/predicates.md (aarch64_sve_dup_ld1rq_operand): Delete. gcc/testsuite/ * gcc.target/aarch64/sve/acle/general/ld1rq_1.c: New test.
2023-09-14libstdc++: Add dg-require-thread-fence in several testsChristophe Lyon8-0/+8
Some targets like arm-eabi with newlib and default settings rely on __sync_synchronize() to ensure synchronization. Newlib does not implement it by default, to make users aware they have to take special care. This makes a few tests fail to link. This patch requires the missing thread-fence effective target in the tests that need it, making them UNSUPPORTED instead of FAIL and UNRESOLVED. 2023-09-10 Christophe Lyon <christophe.lyon@linaro.org> libstdc++-v3/ * testsuite/29_atomics/atomic/compare_exchange_padding.cc: Likewise. * testsuite/29_atomics/atomic/cons/value_init.cc: Likewise. * testsuite/29_atomics/atomic_float/value_init.cc: Likewise. * testsuite/29_atomics/atomic_integral/cons/value_init.cc: Likewise. * testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc: Likewise. * testsuite/29_atomics/atomic_ref/generic.cc: Likewise. * testsuite/29_atomics/atomic_ref/integral.cc: Likewise. * testsuite/29_atomics/atomic_ref/pointer.cc: Likewise.
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