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2023-08-10Fix undefined behaviour in profile_count::differs_from_pJan Hubicka1-2/+3
This patch avoid overflow in profile_count::differs_from_p and also makes it to return false from one of the values is undefined while other is defined. gcc/ChangeLog: * profile-count.cc (profile_count::differs_from_p): Fix overflow and handling of undefined values.
2023-08-10phiopt: Fix phiopt ICE on vops [PR102989]Jakub Jelinek1-1/+11
I've ran into ICE on gcc.dg/torture/bitint-42.c with -O1 or -Os when enabling expensive tests, and unfortunately I can't reproduce without _BitInt. The IL before phiopt3 has: <bb 87> [local count: 203190070]: # .MEM_428 = VDEF <.MEM_367> bitint.159 = VIEW_CONVERT_EXPR<unsigned long[8]>(*.LC3); goto <bb 89>; [100.00%] <bb 88> [local count: 203190070]: # .MEM_427 = VDEF <.MEM_367> bitint.159 = VIEW_CONVERT_EXPR<unsigned long[8]>(*.LC4); <bb 89> [local count: 406380139]: # .MEM_368 = PHI <.MEM_428(87), .MEM_427(88)> # VUSE <.MEM_368> _123 = VIEW_CONVERT_EXPR<unsigned long[8]>(r495[i_107].D.2780)[0]; and factor_out_conditional_operation is called on the vop PHI, it sees it has exactly two operands and defining statements of both PHI arguments are converts (VCEs in this case), so it thinks it is a good idea to try to optimize that and while doing that it constructs void type SSA_NAMEs and the like. 2023-08-10 Jakub Jelinek <jakub@redhat.com> PR c/102989 * tree-ssa-phiopt.cc (single_non_singleton_phi_for_edges): Never return virtual phis and return NULL if there is a virtual phi where the arguments from E0 and E1 edges aren't equal.
2023-08-10Make ISEL used internal functions const/nothrow where appropriateRichard Biener1-7/+9
Both .VEC_SET and .VEC_EXTACT and the various .VCOND internal functions are operating on registers only and they are not supposed to raise any exceptions. The following makes them const/nothrow. I've verified this avoids useless SSA updates in ISEL. * internal-fn.def (VCOND, VCONDU, VCONDEQ, VCOND_MASK, VEC_SET, VEC_EXTRACT): Make ECF_CONST | ECF_NOTHROW.
2023-08-10RISC-V: Add MASK vec_duplicate pattern[PR110962]Juzhe-Zhong1-0/+21
This patch fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110962 SUBROUTINE a(b,c,d) LOGICAL,DIMENSION(INOUT) :: b LOGICAL e REAL, DIMENSION(IN) :: c REAL, DIMENSION(INOUT) :: d REAL, DIMENSION(SIZE(c)) :: f WHERE (b.AND.e) WHERE (f>=0.) d = g ENDWHERE ENDWHERE END SUBROUTINE a PR target/110962 gcc/ChangeLog: PR target/110962 * config/riscv/autovec.md (vec_duplicate<mode>): New pattern.
2023-08-10RISC-V: Support RVV VFNMACC rounding mode intrinsic APIPan Li4-0/+74
This patch would like to support the rounding mode API for the VFNMACC for the below samples. * __riscv_vfnmacc_vv_f32m1_rm * __riscv_vfnmacc_vv_f32m1_rm_m * __riscv_vfnmacc_vf_f32m1_rm * __riscv_vfnmacc_vf_f32m1_rm_m Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfnmacc_frm): New class for vfnmacc. (vfnmacc_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfnmacc_frm): New function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-nmacc.c: New test.
2023-08-10RISC-V: Support RVV VFMACC rounding mode intrinsic APIPan Li4-0/+76
This patch would like to support the rounding mode API for the VFMACC for the below samples. * __riscv_vfmacc_vv_f32m1_rm * __riscv_vfmacc_vv_f32m1_rm_m * __riscv_vfmacc_vf_f32m1_rm * __riscv_vfmacc_vf_f32m1_rm_m Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfmacc_frm): New class for vfmacc frm. (vfmacc_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfmacc_frm): New function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-macc.c: New test.
2023-08-10RISC-V: Support TU for integer ternary OP[PR110964]Juzhe-Zhong2-2/+14
PR target/110964 gcc/ChangeLog: PR target/110964 * config/riscv/riscv-v.cc (expand_cond_len_ternop): Add integer ternary. gcc/testsuite/ChangeLog: PR target/110964 * gcc.target/riscv/rvv/autovec/pr110964.c: New test.
2023-08-10Remove insert location argument from vectorizable_live_operationRichard Biener4-21/+16
The insert location argument isn't actually used but we compute that ourselves. There's a single spot, namely when asking for the loop mask via vect_get_loop_mask that the passed argument is used but that looks like an oversight. The following fixes that and adjusts vectorizable_live_operation and can_vectorize_live_stmts to no longer take a stmt iterator argument. * tree-vectorizer.h (vectorizable_live_operation): Remove gimple_stmt_iterator * argument. * tree-vect-loop.cc (vectorizable_live_operation): Likewise. Adjust plumbing around vect_get_loop_mask. (vect_analyze_loop_operations): Adjust. * tree-vect-slp.cc (vect_slp_analyze_node_operations_1): Likewise. (vect_bb_slp_mark_live_stmts): Likewise. (vect_schedule_slp_node): Likewise. * tree-vect-stmts.cc (can_vectorize_live_stmts): Likewise. Remove gimple_stmt_iterator * argument. (vect_transform_stmt): Adjust.
2023-08-10RISC-V: Add missing modes to the iteratorsJuzhe-Zhong1-0/+3
gcc/ChangeLog: * config/riscv/vector-iterators.md: Add missing modes.
2023-08-10lto-streamer-in: Adjust assert [PR102989]Jakub Jelinek1-1/+1
With _BitInt(575) or any other _BitInt(513) or larger constants we can run into this assertion. MAX_BITSIZE_MODE_ANY_INT is just a value from which WIDE_INT_MAX_PRECISION is derived. 2023-08-10 Jakub Jelinek <jakub@redhat.com> PR c/102989 * lto-streamer-in.cc (lto_input_tree_1): Assert TYPE_PRECISION is up to WIDE_INT_MAX_PRECISION rather than MAX_BITSIZE_MODE_ANY_INT.
2023-08-10expr: Small optimization [PR102989]Jakub Jelinek1-6/+4
Small optimization to avoid testing modifier multiple times. 2023-08-10 Jakub Jelinek <jakub@redhat.com> PR c/102989 * expr.cc (expand_expr_real_1) <case MEM_REF>: Add an early return for EXPAND_WRITE or EXPAND_MEMORY modifiers to avoid testing it multiple times.
2023-08-10i386: Do not sanitize upper part of V2HFmode and V4HFmode reg with ↵liuhongt1-6/+14
-fno-trapping-math [PR110832] Also add ix86_partial_vec_fp_math to to condition of V2HF/V4HF named patterns in order to avoid generation of partial vector V8HFmode trapping instructions. gcc/ChangeLog: PR target/110832 * config/i386/mmx.md: (movq_<mode>_to_sse): Also do not sanitize upper part of V4HFmode register with -fno-trapping-math. (<insn>v4hf3): Enable for ix86_partial_vec_fp_math. (<divv4hf3): Ditto. (<insn>v2hf3): Ditto. (divv2hf3): Ditto. (movd_v2hf_to_sse): Do not sanitize upper part of V2HFmode register with -fno-trapping-math.
2023-08-10RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsicPan Li6-89/+186
The frm_mode attr has some assumptions for each define insn as below. 1. The define insn has at least 9 operands. 2. The operands[9] must be frm reg. 3. The operands[9] must be const int. Actually, the frm operand can be operands[8], operands[9] or operands[10], and not all the define insn has frm operands. This patch would like to refactor frm and eliminate the above assumptions, as well as unblock the underlying rounding mode intrinsic API support. After refactor, the default frm will be none, and the selected insn type will be dyn. For the floating point which honors the frm, we will set the frm_mode attr explicitly in define_insn. Signed-off-by: Pan Li <pan2.li@intel.com> Co-Authored-by: Kito Cheng <kito.cheng@sifive.com> gcc/ChangeLog: * config/riscv/riscv-protos.h (enum floating_point_rounding_mode): Add NONE, DYN_EXIT and DYN_CALL. (get_frm_mode): New declaration. * config/riscv/riscv-v.cc (get_frm_mode): New function to get frm mode. * config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Take care of frm reg. * config/riscv/riscv.cc (riscv_static_frm_mode_p): Migrate to FRM_XXX. (riscv_emit_frm_mode_set): Ditto. (riscv_emit_mode_set): Ditto. (riscv_frm_adjust_mode_after_call): Ditto. (riscv_frm_mode_needed): Ditto. (riscv_frm_mode_after): Ditto. (riscv_mode_entry): Ditto. (riscv_mode_exit): Ditto. * config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Ditto. * config/riscv/vector.md (rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none): Removed (symbol_ref): * config/riscv/vector.md: Set frm_mode attr explicitly.
2023-08-10Daily bump.GCC Administrator8-1/+412
2023-08-10RISC-V: Fix VLMAX AVL incorrect local anticipate [VSETVL PASS]Juzhe-Zhong8-47/+47
Realize we have a bug in VSETVL PASS which is triggered by strided_load_run-1.c in RV32 system. FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c execution test This is because VSETVL PASS incorrect hoist vsetvl instruction: ... 10156: 0d9075d7 vsetvli a1,zero,e64,m2,ta,ma ---> pollute 'a1' register which will be used by following insns. 1015a: 01d586b3 add a3,a1,t4 --------> use 'a1' 1015e: 5e070257 vmv.v.v v4,v14 10162: b7032257 vmacc.vv v4,v6,v16 10166: 26440257 vand.vv v4,v4,v8 1016a: 22880227 vs2r.v v4,(a6) 1016e: 00b6b7b3 sltu a5,a3,a1 10172: 22888227 vs2r.v v4,(a7) 10176: 9e60b157 vmv2r.v v2,v6 1017a: 97ba add a5,a5,a4 1017c: a6a62157 vmadd.vv v2,v12,v10 10180: 26240157 vand.vv v2,v2,v8 10184: 22830127 vs2r.v v2,(t1) 10188: 873e mv a4,a5 1018a: 982a add a6,a6,a0 1018c: 98aa add a7,a7,a0 1018e: 932a add t1,t1,a0 10190: 85b6 mv a1,a3 -----> set 'a1' ... gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix incorrect anticipate info. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load_run-1.c: Adapt test. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Ditto.
2023-08-09analyzer: remove default return value from region_model::on_call_preDavid Malcolm20-214/+266
Previously, the code for simulating calls to external functions in region_model::on_call_pre wrote a default svalue to the LHS of the call statement, which could be further overwritten by known_function subclasses. Unfortunately, this led to messy hacks, such as when the default svalue was an allocation: the LHS would be written to with two different heap-allocated regions, requiring special-case cleanups to avoid the stray state from the first heap allocation leading to state explosions; see r14-3001-g021077b94741c9. The following patch eliminates this write of a default svalue to the LHS of callsite. Instead, all known_function implementations that have a return value are now responsible for set the LHS themselves. A new call_details::set_any_lhs_with_defaults function is provided to make it easy to get the old behavior. On working through the various known_function subclasses, I noticed that memset was using the default behavior. That patch updates this so that it's now known to return its first parameter. Cleaning this up eliminates various doubling of saved_diagnostics (e.g. for dubious_allocation_size) where it was generating a diagnostic for both writes to the LHS, deduplicating them to the first diagnostic (with the default LHS), and then failing to create a region_creation_event when emitting the diagnostic, leading to the fallback wording in dubious_allocation_size::describe_final_event, such as: (1) allocated 42 bytes and assigned to ‘int32_t *’ {aka ‘int *’} here; ‘sizeof (int32_t {aka int})’ is ‘4’ Without the double write to the LHS, it creates a region_creation_event, so we get the allocation and the assignment as two separate events in the diagnostic path, e.g.: (1) allocated 42 bytes here (2) assigned to ‘int32_t *’ {aka ‘int *’} here; ‘sizeof (int32_t {aka int})’ is ‘4’ gcc/analyzer/ChangeLog: * analyzer.h (class pure_known_function_with_default_return): New subclass. * call-details.cc (const_fn_p): Move here from region-model.cc. (maybe_get_const_fn_result): Likewise. (get_result_size_in_bytes): Likewise. (call_details::set_any_lhs_with_defaults): New function, based on code in region_model::on_call_pre. * call-details.h (call_details::set_any_lhs_with_defaults): New decl. * diagnostic-manager.cc (diagnostic_manager::emit_saved_diagnostic): Log the index of the saved_diagnostic. * kf.cc (pure_known_function_with_default_return::impl_call_pre): New. (kf_memset::impl_call_pre): Set the LHS to the first param. (kf_putenv::impl_call_pre): Call cd.set_any_lhs_with_defaults. (kf_sprintf::impl_call_pre): Call cd.set_any_lhs_with_defaults. (class kf_stack_restore): Derive from pure_known_function_with_default_return. (class kf_stack_save): Likewise. (kf_strlen::impl_call_pre): Call cd.set_any_lhs_with_defaults. * region-model-reachability.cc (reachable_regions::handle_sval): Remove logic for symbolic regions for pointers. * region-model.cc (region_model::canonicalize): Remove purging of dynamic extents workaround for surplus values from region_model::on_call_pre's default LHS code. (const_fn_p): Move to call-details.cc. (maybe_get_const_fn_result): Likewise. (get_result_size_in_bytes): Likewise. (region_model::update_for_nonzero_return): Call cd.set_any_lhs_with_defaults. (region_model::on_call_pre): Remove the assignment to the LHS of a default return value, instead requiring all known_function implementations to write to any LHS of the call. Use cd.set_any_lhs_with_defaults on the non-kf paths. * sm-fd.cc (kf_socket::outcome_of_socket::update_model): Use cd.set_any_lhs_with_defaults when failing to get at fd state. (kf_bind::outcome_of_bind::update_model): Likewise. (kf_listen::outcome_of_listen::update_model): Likewise. (kf_accept::outcome_of_accept::update_model): Likewise. (kf_connect::outcome_of_connect::update_model): Likewise. (kf_read::impl_call_pre): Use cd.set_any_lhs_with_defaults. * sm-file.cc (class kf_stdio_output_fn): Derive from pure_known_function_with_default_return. (class kf_ferror): Likewise. (class kf_fileno): Likewise. (kf_fgets::impl_call_pre): Use cd.set_any_lhs_with_defaults. (kf_read::impl_call_pre): Likewise. (class kf_getc): Derive from pure_known_function_with_default_return. (class kf_getchar): Likewise. * varargs.cc (kf_va_arg::impl_call_pre): Use cd.set_any_lhs_with_defaults. gcc/testsuite/ChangeLog: * gcc.dg/analyzer/allocation-size-1.c: Update expected results to reflect splitting of allocation size and assignment messages from a single event into pairs of events * gcc.dg/analyzer/allocation-size-2.c: Likewise. * gcc.dg/analyzer/allocation-size-3.c: Likewise. * gcc.dg/analyzer/allocation-size-4.c: Likewise. * gcc.dg/analyzer/allocation-size-multiline-1.c: Likewise. * gcc.dg/analyzer/allocation-size-multiline-2.c: Likewise. * gcc.dg/analyzer/allocation-size-multiline-3.c: Likewise. * gcc.dg/analyzer/memset-1.c (test_1): Verify that the return value is the initial argument. * gcc.dg/plugin/analyzer_kernel_plugin.c (copy_across_boundary_fn::impl_call_pre): Ensure the LHS is set on the "known zero size" case. * gcc.dg/plugin/analyzer_known_fns_plugin.c (known_function_attempt_to_copy::impl_call_pre): Likewise. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-08-09RISC-V: Remove non-existing 'Zve32d' extensionTsukasa OI1-1/+0
Since this extension does not exist, this commit prunes this from the defined extension version table. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Remove 'Zve32d' from the version list.
2023-08-09RISC-V: Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE.Jin Ma1-0/+28
Reference: https://github.com/gcc-mirror/gcc/commit/d0bc0cb66bcb0e6a5a5a31a9e900e8ccc98e34e5 RISC-V should also be implemented to handle no_insn patterns for pipelining. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): New function. (TARGET_SCHED_VARIABLE_ISSUE): New macro. Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
2023-08-09RISC-V: Folding memory for FP + constant caseJivan Hakobyan1-0/+42
Accessing local arrays element turned into load form (fp + (index << C1)) + C2 address. In the case when access is in the loop we got loop invariant computation. For some reason, moving out that part cannot be done in loop-invariant passes. But we can handle that in target-specific hook (legitimize_address). That provides an opportunity to rewrite memory access more suitable for the target architecture. This patch solves the mentioned case by rewriting mentioned case to ((fp + C2) + (index << C1)) I have evaluated it on SPEC2017 and got an improvement on leela (over 7b instructions, .39% of the dynamic count) and dwarfs the regression for gcc (14m instructions, .0012% of the dynamic count). gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_address): Handle folding. (mem_shadd_or_shadd_rtx_p): New function.
2023-08-09MATCH: [PR110937/PR100798] (a ? ~b : b) should be optimized to b ^ -(a)Andrew Pinski5-2/+63
This adds a simple match pattern for this case. I noticed it a couple of different places. One while I was looking at code generation of a parser and also while I was looking at locations where bitwise_inverted_equal_p should be used more. Committed as approved after bootstrapped and tested on x86_64-linux-gnu with no regressions. PR tree-optimization/110937 PR tree-optimization/100798 gcc/ChangeLog: * match.pd (`a ? ~b : b`): Handle this case. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/bool-14.c: New test. * gcc.dg/tree-ssa/bool-15.c: New test. * gcc.dg/tree-ssa/phi-opt-33.c: New test. * gcc.dg/tree-ssa/20030709-2.c: Update testcase so `a ? -1 : 0` is not used to hit the match pattern.
2023-08-09i386: Add missing dot to -mpartial-vector-fp-math descriptionUros Bizjak1-1/+1
gcc/ChangeLog: * config/i386/i386.opt (mpartial-vector-fp-math): Add dot.
2023-08-09aarch64: Add support for Cortex-A520 CPURichard Ball3-3/+5
This patch adds support for the Cortex-A520 CPU to GCC. gcc/ChangeLog: * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A520 CPU. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi: Document Cortex-A520 CPU.
2023-08-09rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementationCarl Love5-112/+156
The current built-in definitions for vcmpneb, vcmpneh, vcmpnew are defined under the Power 9 section of r66000-builtins. This implies they are only supported on Power 9 and above when in fact they are defined and work with Altivec as well with the appropriate Altivec instruction generation. The vec_cmpne builtin should generate the vcmpequ{b,h,w} instruction with Altivec enabled and generate the vcmpne{b,h,w} on Power 9 and newer processors. This patch moves the definitions to the Altivec stanza to make it clear the built-ins are supported for all Altivec processors. The patch removes the confusion as to which processors support the vcmpequ{b,h,w} instructions. There is existing test coverage for the vec_cmpne built-in for vector bool char, vector bool short, vector bool int, vector bool long long in builtins-3-p9.c and p8vector-builtin-2.c. Coverage for vector signed int, vector unsigned int is in p8vector-builtin-2.c. Test vec-cmpne.c is updated to check the generation of the vcmpequ{b,h,w} instructions for Altivec. A new test vec-cmpne-runnable.c is added to verify the built-ins work as expected. Patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10 LE with no regressions. gcc/ChangeLog: * config/rs6000/rs6000-builtins.def (vcmpneb, vcmpneh, vcmpnew): Move definitions to Altivec stanza. * config/rs6000/altivec.md (vcmpneb, vcmpneh, vcmpnew): New define_expand. gcc/testsuite/ChangeLog: * gcc.target/powerpc/vec-cmpne-runnable.c: New execution test. * gcc.target/powerpc/vec-cmpne.c (define_test_functions, execute_test_functions): Move to vec-cmpne.h. Add scan-assembler-times for vcmpequb, vcmpequh, vcmpequw. * gcc.target/powerpc/vec-cmpne.h: New include file for vec-cmpne.c and vec-cmpne-runnable.c. Split define_test_functions definition into define_test_functions and define_init_verify_functions.
2023-08-09libstdc++: Fix constexpr functions to conform to older standardsJonathan Wakely4-13/+12
Some constexpr functions were inadvertently relying on relaxed constexpr rules from later standards. libstdc++-v3/ChangeLog: * include/bits/chrono.h (duration_cast): Do not use braces around statements for C++11 constexpr rules. * include/bits/stl_algobase.h (__lg): Rewrite as a single statement for C++11 constexpr rules. * include/experimental/bits/fs_path.h (path::string): Use _GLIBCXX17_CONSTEXPR not _GLIBCXX_CONSTEXPR for 'if constexpr'. * include/std/charconv (__to_chars_8): Initialize variable for C++17 constexpr rules.
2023-08-09libstdc++: Fix a -Wsign-compare warning in std::listJonathan Wakely1-1/+1
libstdc++-v3/ChangeLog: * include/bits/list.tcc (list::sort(Cmp)): Fix -Wsign-compare warning for loop condition.
2023-08-09libstdc++: Suppress clang -Wc99-extensions warnings in <complex>Jonathan Wakely1-0/+9
This prevents Clang from warning about the use of the non-standard __complex__ keyword. libstdc++-v3/ChangeLog: * include/std/complex: Add diagnostic pragma for clang.
2023-08-09libstdc++: Fix some -Wmismatched-tags warningsJonathan Wakely6-18/+18
libstdc++-v3/ChangeLog: * include/bits/shared_ptr_atomic.h (atomic): Change class-head to struct. * include/bits/stl_tree.h (_Rb_tree_merge_helper): Change class-head to struct in friend declaration. * include/std/chrono (tzdb_list::_Node): Likewise. * include/std/future (_Task_state_base, _Task_state): Likewise. * include/std/scoped_allocator (__inner_type_impl): Likewise. * include/std/valarray (_BinClos, _SClos, _GClos, _IClos) (_ValFunClos, _RefFunClos): Change class-head to struct.
2023-08-09libstdc++: Fix some -Wunused-parameter warningsJonathan Wakely12-26/+26
libstdc++-v3/ChangeLog: * include/bits/alloc_traits.h (allocate): Add [[maybe_unused]] attribute. * include/bits/regex_executor.tcc: Remove name of unused parameter. * include/bits/shared_ptr_atomic.h (atomic_is_lock_free): Likewise. * include/bits/stl_uninitialized.h: Likewise. * include/bits/streambuf_iterator.h (operator==): Likewise. * include/bits/uses_allocator.h: Likewise. * include/c_global/cmath (isfinite, isinf, isnan): Likewise. * include/std/chrono (zoned_time): Likewise. * include/std/future (__future_base::_S_allocate_result): Likewise. (packaged_task): Likewise. * include/std/optional (_Optional_payload_base): Likewise. * include/std/scoped_allocator (__inner_type_impl): Likewise. * include/std/tuple (_Tuple_impl): Likewise.
2023-08-09libstdc++: Explicitly default some copy ctors and assignmentsJonathan Wakely2-0/+17
The standard says that the implicit copy assignment operator is deprecated for classes that have a user-provided copy constructor, and vice versa. libstdc++-v3/ChangeLog: * include/bits/new_allocator.h (__new_allocator): Define copy assignment operator as defaulted. * include/std/complex (complex<float>, complex<double>) (complex<long double>): Define copy constructor as defaulted.
2023-08-09libstdc++: Minor fixes for some warnings in <format>Jonathan Wakely1-15/+13
libstdc++-v3/ChangeLog: * include/std/format: Fix some warnings. (__format::__write(Ctx&, basic_string_view<CharT>)): Remove unused function template.
2023-08-09RISC-V: Support NPATTERNS = 1 stepped vector[PR110950]Juzhe-Zhong2-0/+31
This patch fix ICE: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950 0x1cf8939 expand_const_vector ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:1587 PR target/110950 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Add NPATTERNS = 1 stepped vector support. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr110950.c: New test.
2023-08-09Fortran: Allow pure final procs contained in pure proc. [PR109684]Paul Thomas1-1/+4
2023-08-09 Steve Kargl <sgk@troutmask.apl.washington.edu> gcc/fortran PR fortran/109684 * resolve.cc (resolve_types): Exclude contained procedures with the artificial attribute from test for pureness.
2023-08-09PR modula2/110779: libgm2 fix solaris bootstrap check for tm_gmtoffGaius Mulley6-27/+420
This patch defensively checks for every C function and every struct used in wrapclock.cc. It adds return values to GetTimespec and SetTimespec to allow the module to return a code representing unavailable. gcc/m2/ChangeLog: PR modula2/110779 * gm2-libs-iso/SysClock.mod (GetClock): Test GetTimespec return value. (SetClock): Test SetTimespec return value. * gm2-libs-iso/wrapclock.def (GetTimespec): Add integer return type. (SetTimespec): Add integer return type. libgm2/ChangeLog: PR modula2/110779 * config.h.in: Regenerate. * configure: Regenerate. * configure.ac (AC_CACHE_CHECK): Check for tm_gmtoff field in struct tm. (GM2_CHECK_LIB): Check for daylight, timezone and tzname. * libm2iso/wrapclock.cc (timezone): Guard against absence of struct tm and tm_gmtoff. (daylight): Check for daylight. (timezone): Check for timezone. (isdst): Check for isdst. (tzname): Check for tzname. (GetTimeRealtime): Check for struct timespec. (SetTimeRealtime): Check for struct timespec. (InitTimespec): Check for struct timespec. (KillTimespec): Check for struct timespec. (SetTimespec): Check for struct timespec. (GetTimespec): Check for struct timespec. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-08-09Rename local variable subleaf_level to max_subleaf_level.liuhongt1-3/+4
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Rename local variable subleaf_level to max_subleaf_level.
2023-08-09rtl-optimization/110587 - speedup find_hard_regno_for_1Richard Biener1-4/+5
The following applies a micro-optimization to find_hard_regno_for_1, re-ordering the check so we can easily jump-thread by using an else. This reduces the time spent in this function by 15% for the testcase in the PR. PR rtl-optimization/110587 * lra-assigns.cc (find_hard_regno_for_1): Re-order checks.
2023-08-09rs6000: Teach legitimate_address_p about LEN_{LOAD,STORE} [PR110248]Kewen Lin1-1/+7
This patch is to teach rs6000_legitimate_address_p to handle the queried rtx constructed for LEN_{LOAD,STORE}, since lxvl and stxvl doesn't support x-form or ds-form, so consider it as not legitimate when outer code is PLUS. PR tree-optimization/110248 gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_legitimate_address_p): Check if the given code is for ifn LEN_{LOAD,STORE}, if yes then make it not legitimate when outer code is PLUS.
2023-08-09ivopts: Call valid_mem_ref_p with ifn [PR110248]Kewen Lin6-19/+31
As PR110248 shows, to get the expected query results for that internal functions LEN_{LOAD,STORE} is able to adopt some addressing modes, we need to pass down the related IFN code as well. This patch is to make IVOPTs pass down ifn code for USE_PTR_ADDRESS type uses, it adjusts the related functions {strict_,}memory_address_addr_space_p, and valid_mem_ref_p as well. PR tree-optimization/110248 gcc/ChangeLog: * recog.cc (memory_address_addr_space_p): Add one more argument ch of type code_helper and pass it to targetm.addr_space.legitimate_address_p instead of ERROR_MARK. (offsettable_address_addr_space_p): Update one function pointer with one more argument of type code_helper as its assignees memory_address_addr_space_p and strict_memory_address_addr_space_p have been adjusted, and adjust some call sites with ERROR_MARK. * recog.h (tree.h): New include header file for tree_code ERROR_MARK. (memory_address_addr_space_p): Adjust with one more unnamed argument of type code_helper with default ERROR_MARK. (strict_memory_address_addr_space_p): Likewise. * reload.cc (strict_memory_address_addr_space_p): Add one unnamed argument of type code_helper. * tree-ssa-address.cc (valid_mem_ref_p): Add one more argument ch of type code_helper and pass it to memory_address_addr_space_p. * tree-ssa-address.h (valid_mem_ref_p): Adjust the declaration with one more unnamed argument of type code_helper with default value ERROR_MARK. * tree-ssa-loop-ivopts.cc (get_address_cost): Use ERROR_MARK as code by default, change it with ifn code for USE_PTR_ADDRESS type use, and pass it to all valid_mem_ref_p calls.
2023-08-09targhooks: Extend legitimate_address_p with code_helper [PR110248]Kewen Lin62-106/+190
As PR110248 shows, some middle-end passes like IVOPTs can query the target hook legitimate_address_p with some artificially constructed rtx to determine whether some addressing modes are supported by target for some gimple statement. But for now the existing legitimate_address_p only checks the given mode, it's unable to distinguish some special cases unfortunately, for example, for LEN_LOAD ifn on Power port, we would expand it with lxvl hardware insn, which only supports one register to hold the address (the other register is holding the length), that is we don't support base (reg) + index (reg) addressing mode for sure. But hook legitimate_address_p only considers the given mode which would be some vector mode for LEN_LOAD ifn, and we do support base + index addressing mode for normal vector load and store insns, so the hook will return true for the query unexpectedly. This patch is to introduce one extra argument of type code_helper for hook legitimate_address_p, it makes targets able to handle some special case like what's described above. PR tree-optimization/110248 gcc/ChangeLog: * coretypes.h (class code_helper): Add forward declaration. * doc/tm.texi: Regenerate. * lra-constraints.cc (valid_address_p): Call target hook targetm.addr_space.legitimate_address_p with an extra parameter ERROR_MARK as its prototype changes. * recog.cc (memory_address_addr_space_p): Likewise. * reload.cc (strict_memory_address_addr_space_p): Likewise. * target.def (legitimate_address_p, addr_space.legitimate_address_p): Extend with one more argument of type code_helper, update the documentation accordingly. * targhooks.cc (default_legitimate_address_p): Adjust for the new code_helper argument. (default_addr_space_legitimate_address_p): Likewise. * targhooks.h (default_legitimate_address_p): Likewise. (default_addr_space_legitimate_address_p): Likewise. * config/aarch64/aarch64.cc (aarch64_legitimate_address_hook_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/alpha/alpha.cc (alpha_legitimate_address_p): Likewise. * config/arc/arc.cc (arc_legitimate_address_p): Likewise. * config/arm/arm-protos.h (arm_legitimate_address_p): Likewise. (tree.h): New include for tree_code ERROR_MARK. * config/arm/arm.cc (arm_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/avr/avr.cc (avr_addr_space_legitimate_address_p): Likewise. * config/bfin/bfin.cc (bfin_legitimate_address_p): Likewise. * config/bpf/bpf.cc (bpf_legitimate_address_p): Likewise. * config/c6x/c6x.cc (c6x_legitimate_address_p): Likewise. * config/cris/cris-protos.h (cris_legitimate_address_p): Likewise. (tree.h): New include for tree_code ERROR_MARK. * config/cris/cris.cc (cris_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/csky/csky.cc (csky_legitimate_address_p): Likewise. * config/epiphany/epiphany.cc (epiphany_legitimate_address_p): Likewise. * config/frv/frv.cc (frv_legitimate_address_p): Likewise. * config/ft32/ft32.cc (ft32_addr_space_legitimate_address_p): Likewise. * config/gcn/gcn.cc (gcn_addr_space_legitimate_address_p): Likewise. * config/h8300/h8300.cc (h8300_legitimate_address_p): Likewise. * config/i386/i386.cc (ix86_legitimate_address_p): Likewise. * config/ia64/ia64.cc (ia64_legitimate_address_p): Likewise. * config/iq2000/iq2000.cc (iq2000_legitimate_address_p): Likewise. * config/lm32/lm32.cc (lm32_legitimate_address_p): Likewise. * config/loongarch/loongarch.cc (loongarch_legitimate_address_p): Likewise. * config/m32c/m32c.cc (m32c_legitimate_address_p): Likewise. (m32c_addr_space_legitimate_address_p): Likewise. * config/m32r/m32r.cc (m32r_legitimate_address_p): Likewise. * config/m68k/m68k.cc (m68k_legitimate_address_p): Likewise. * config/mcore/mcore.cc (mcore_legitimate_address_p): Likewise. * config/microblaze/microblaze-protos.h (tree.h): New include for tree_code ERROR_MARK. (microblaze_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/microblaze/microblaze.cc (microblaze_legitimate_address_p): Likewise. * config/mips/mips.cc (mips_legitimate_address_p): Likewise. * config/mmix/mmix.cc (mmix_legitimate_address_p): Likewise. * config/mn10300/mn10300.cc (mn10300_legitimate_address_p): Likewise. * config/moxie/moxie.cc (moxie_legitimate_address_p): Likewise. * config/msp430/msp430.cc (msp430_legitimate_address_p): Likewise. (msp430_addr_space_legitimate_address_p): Adjust with extra code_helper argument with default ERROR_MARK and adjust the call to function msp430_legitimate_address_p. * config/nds32/nds32.cc (nds32_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/nios2/nios2.cc (nios2_legitimate_address_p): Likewise. * config/nvptx/nvptx.cc (nvptx_legitimate_address_p): Likewise. * config/or1k/or1k.cc (or1k_legitimate_address_p): Likewise. * config/pa/pa.cc (pa_legitimate_address_p): Likewise. * config/pdp11/pdp11.cc (pdp11_legitimate_address_p): Likewise. * config/pru/pru.cc (pru_addr_space_legitimate_address_p): Likewise. * config/riscv/riscv.cc (riscv_legitimate_address_p): Likewise. * config/rl78/rl78-protos.h (rl78_as_legitimate_address): Likewise. (tree.h): New include for tree_code ERROR_MARK. * config/rl78/rl78.cc (rl78_as_legitimate_address): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/rs6000/rs6000.cc (rs6000_legitimate_address_p): Likewise. (rs6000_debug_legitimate_address_p): Adjust with extra code_helper argument and adjust the call to function rs6000_legitimate_address_p. * config/rx/rx.cc (rx_is_legitimate_address): Adjust with extra unnamed code_helper argument with default ERROR_MARK. * config/s390/s390.cc (s390_legitimate_address_p): Likewise. * config/sh/sh.cc (sh_legitimate_address_p): Likewise. * config/sparc/sparc.cc (sparc_legitimate_address_p): Likewise. * config/v850/v850.cc (v850_legitimate_address_p): Likewise. * config/vax/vax.cc (vax_legitimate_address_p): Likewise. * config/visium/visium.cc (visium_legitimate_address_p): Likewise. * config/xtensa/xtensa.cc (xtensa_legitimate_address_p): Likewise. * config/stormy16/stormy16-protos.h (xstormy16_legitimate_address_p): Likewise. (tree.h): New include for tree_code ERROR_MARK. * config/stormy16/stormy16.cc (xstormy16_legitimate_address_p): Adjust with extra unnamed code_helper argument with default ERROR_MARK.
2023-08-09Workaround possible CPUID bug in Sandy Bridge.liuhongt1-39/+43
Don't access leaf 7 subleaf 1 unless subleaf 0 says it is supported via EAX. Intel documentation says invalid subleaves return 0. We had been relying on that behavior instead of checking the max sublef number. It appears that some Sandy Bridge CPUs return at least the subleaf 0 EDX value for subleaf 1. Best guess is that this is a bug in a microcode patch since all of the bits we're seeing set in EDX were introduced after Sandy Bridge was originally released. This is causing avxvnniint16 to be incorrectly enabled with -march=native on these CPUs. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Check EAX for valid subleaf before use CPUID.
2023-08-09Daily bump.GCC Administrator4-1/+376
2023-08-08[committed] [RISC-V] Fix bug in condition canonicalization for zicondJeff Law2-1/+14
Vineet's glibc build triggered an ICE building glibc with the latest zicond bits. It's a minor issue in the canonicalization of the condition. When we need to canonicalize the condition we use an SCC insn to handle the primary comparison with the output going into a temporary with the final value of 0/1 which we can then use in a zicond instruction. The mode of the newly generated temporary was taken from mode of the final destination. That's simply wrong. The mode of the condition needs to be word_mode. This patch fixes that minor problem and adds a suitable testcase. gcc/ * config/riscv/riscv.cc (riscv_expand_conditional_move): Use word_mode for the temporary when canonicalizing the condition. gcc/testsuite * gcc.target/riscv/zicond-ice-1.c: New test.
2023-08-08c++: parser cleanup, remove dummy argumentsMarek Polacek1-61/+41
Now that cp_parser_constant_expression accepts a null non_constant_p, we can transitively remove dummy arguments in the call chain. Running dg.exp and counting the # of is_rvalue_constant_expression calls from cp_parser_constant_expression: pre-r14-2800: 2,459,145 this patch : 1,719,454 gcc/cp/ChangeLog: * parser.cc (cp_parser_postfix_expression): Adjust the call to cp_parser_braced_list. (cp_parser_postfix_open_square_expression): Likewise. (cp_parser_new_initializer): Likewise. (cp_parser_assignment_expression): Adjust the call to cp_parser_initializer_clause. (cp_parser_lambda_introducer): Adjust the call to cp_parser_initializer. (cp_parser_range_for): Adjust the call to cp_parser_braced_list. (cp_parser_jump_statement): Likewise. (cp_parser_mem_initializer): Likewise. (cp_parser_template_argument): Likewise. (cp_parser_default_argument): Adjust the call to cp_parser_initializer. (cp_parser_initializer): Handle null is_direct_init and non_constant_p arguments. (cp_parser_initializer_clause): Handle null non_constant_p argument. (cp_parser_braced_list): Likewise. (cp_parser_initializer_list): Likewise. (cp_parser_member_declaration): Adjust the call to cp_parser_initializer_clause and cp_parser_initializer. (cp_parser_yield_expression): Adjust the call to cp_parser_braced_list. (cp_parser_functional_cast): Likewise. (cp_parser_late_parse_one_default_arg): Adjust the call to cp_parser_initializer. (cp_parser_omp_for_loop_init): Likewise. (cp_parser_omp_declare_reduction_exprs): Likewise.
2023-08-08c++: Report invalid id-expression in decltype [PR100482]Nathaniel Shead2-11/+23
This patch ensures that any errors raised by finish_id_expression when parsing a decltype expression are properly reported, rather than potentially going ignored and causing invalid code to be accepted. We can also now remove the separate check for templates without args as this is also checked for in finish_id_expression. PR c++/100482 gcc/cp/ChangeLog: * parser.cc (cp_parser_decltype_expr): Report errors raised by finish_id_expression. gcc/testsuite/ChangeLog: * g++.dg/cpp0x/decltype-100482.C: New test. Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com>
2023-08-08bpf: Fixed GC mistakes in BPF builtins code.Cupertino Miranda2-48/+28
This patches fixes problems with GC within the CO-RE builtins implementation. List of included headers was also revised. gcc/ChangeLog: * config/bpf/core-builtins.cc: Cleaned include headers. (struct cr_builtins): Added GTY. (cr_builtins_ref): Created. (builtins_data) Changed to GC root. (allocate_builtin_data): Changed. Included gt-core-builtins.h. * config/bpf/coreout.cc: (bpf_core_extra) Added GTY. (bpf_core_extra_ref): Created. (bpf_comment_info): Changed to GC root. (bpf_core_reloc_add, output_btfext_header, btf_ext_init): Changed.
2023-08-08i386: Do not sanitize upper part of V2SFmode reg with -fno-trapping-math ↵Uros Bizjak6-32/+103
[PR110832] Also introduce -m[no-]partial-vector-fp-math option to disable trapping V2SF named patterns in order to avoid generation of partial vector V4SFmode trapping instructions. The new option is enabled by default, because even with sanitization, a small but consistent speed up of 2 to 3% with Polyhedron capacita benchmark can be achieved vs. scalar code. Using -fno-trapping-math improves Polyhedron capacita runtime 8 to 9% vs. scalar code. This is what clang does by default, as it defaults to -fno-trapping-math. PR target/110832 gcc/ChangeLog: * config/i386/i386.opt (mpartial-vector-fp-math): New option. * config/i386/mmx.md (movq_<mode>_to_sse): Do not sanitize upper part of V2SFmode register with -fno-trapping-math. (<plusminusmult:insn>v2sf3): Enable for ix86_partial_vec_fp_math. (divv2sf3): Ditto. (<smaxmin:code>v2sf3): Ditto. (sqrtv2sf2): Ditto. (*mmx_haddv2sf3_low): Ditto. (*mmx_hsubv2sf3_low): Ditto. (vec_addsubv2sf3): Ditto. (vec_cmpv2sfv2si): Ditto. (vcond<V2FI:mode>v2sf): Ditto. (fmav2sf4): Ditto. (fmsv2sf4): Ditto. (fnmav2sf4): Ditto. (fnmsv2sf4): Ditto. (fix_truncv2sfv2si2): Ditto. (fixuns_truncv2sfv2si2): Ditto. (floatv2siv2sf2): Ditto. (floatunsv2siv2sf2): Ditto. (nearbyintv2sf2): Ditto. (rintv2sf2): Ditto. (lrintv2sfv2si2): Ditto. (ceilv2sf2): Ditto. (lceilv2sfv2si2): Ditto. (floorv2sf2): Ditto. (lfloorv2sfv2si2): Ditto. (btruncv2sf2): Ditto. (roundv2sf2): Ditto. (lroundv2sfv2si2): Ditto. * doc/invoke.texi (x86 Options): Document -mpartial-vector-fp-math option. gcc/testsuite/ChangeLog: * gcc.target/i386/pr110832-1.c: New test. * gcc.target/i386/pr110832-2.c: New test. * gcc.target/i386/pr110832-3.c: New test.
2023-08-08VR-VALUES [PR28794]: optimize compare assignments alsoAndrew Pinski4-62/+134
This patch fixes the oldish (2006) bug where VRP was not optimizing the comparison for assignments while handling them for GIMPLE_COND only. It just happens to also solves PR 103281 due to allowing to optimize `c < 1` to `c == 0` and then we get `(c == 0) == c` (which was handled by r14-2501-g285c9d04). OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. PR tree-optimization/103281 PR tree-optimization/28794 gcc/ChangeLog: * vr-values.cc (simplify_using_ranges::simplify_cond_using_ranges_1): Split out majority to ... (simplify_using_ranges::simplify_compare_using_ranges_1): Here. (simplify_using_ranges::simplify_casted_cond): Rename to ... (simplify_using_ranges::simplify_casted_compare): This and change arguments to take op0 and op1. (simplify_using_ranges::simplify_compare_assign_using_ranges_1): New method. (simplify_using_ranges::simplify): For tcc_comparison assignments call simplify_compare_assign_using_ranges_1. * vr-values.h (simplify_using_ranges): Add new methods, simplify_compare_using_ranges_1 and simplify_compare_assign_using_ranges_1. Rename simplify_casted_cond and simplify_casted_compare and update argument types. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/pr103281-1.c: New test. * gcc.dg/tree-ssa/vrp-compare-1.c: New test.
2023-08-08RISC-V: Enhance the test case for RVV vfsub/vfrsub roundingPan Li2-2/+30
This patch would like to enhance the vfsub/vfrsub rounding API test for below 2 purposes. * The non-rm API has no frm related insn generated. * The rm API has the frm backup/restore/set insn generated. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-rsub.c: Enhance cases. * gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-08-08genmatch: Log line numbers indirectlyAndrzej Turko1-15/+80
Currently fprintf calls logging to a dump file take line numbers in the match.pd file directly as arguments. When match.pd is edited, referenced code changes line numbers, which causes changes to many fprintf calls and, thus, to many (usually all) .cc files generated by genmatch. This forces make to (unnecessarily) rebuild many .o files. This change replaces those logging fprintf calls with calls to a dedicated logging function. Because it reads the line numbers from the lookup table, it is enough to pass a corresponding index. Thanks to this, when match.pd changes, it is enough to rebuild the file containing the lookup table and, of course, those actually affected by the change. Signed-off-by: Andrzej Turko <andrzej.turko@gmail.com> gcc/ChangeLog: * genmatch.cc: Log line numbers indirectly.
2023-08-08genmatch: Reduce variability of generated codeAndrzej Turko2-3/+4
So far genmatch has been using an unordered map to store information about functions to be generated. Since corresponding locations from match.pd were used as keys in the map, even small changes to match.pd which caused line number changes would change the order in which the functions are generated. This would reshuffle the functions between the generated .cc files. This way even a minimal modification to match.pd forces recompilation of all object files originating from match.pd on rebuild. This commit makes sure that functions are generated in the order of their processing (in contrast to the random order based on hashes of their locations in match.pd). This is done by replacing the unordered map with an ordered one. This way small changes to match.pd does not cause function renaming and reshuffling among generated source files. Together with the subsequent change to logging fprintf calls, this removes unnecessary changes to the files generated by genmatch allowing for reuse of already built object files during rebuild. The aim is to make editing of match.pd and subsequent testing easier. Signed-off-by: Andrzej Turko <andrzej.turko@gmail.com> gcc/ChangeLog: * genmatch.cc: Make sinfo map ordered. * Makefile.in: Require the ordered map header for genmatch.o.
2023-08-08Support get_or_insert in ordered_hash_mapAndrzej Turko2-4/+41
Get_or_insert method is already supported by the unordered hash map. Adding it to the ordered map enables us to replace the unordered map with the ordered one in cases where ordering may be useful. Signed-off-by: Andrzej Turko <andrzej.turko@gmail.com> gcc/ChangeLog: * ordered-hash-map.h: Add get_or_insert. * ordered-hash-map-tests.cc: Use get_or_insert in tests.
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