riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-09-22	Allow -mno-evex512 usagedevel/ix86/evex512	Haochen Jiang	4	-1/+40
2023-09-22	Support -mevex512 for AVX512FP16 intrins	Haochen Jiang	1	-23/+21
2023-09-22	Support -mevex512 for AVX512{IFMA,VBMI,VNNI,BF16,VPOPCNTDQ,VBMI2,BITALG,VP2IN...	Haochen Jiang	2	-27/+31
2023-09-22	Support -mevex512 for AVX512BW intrins	Haochen Jiang	4	-126/+128
2023-09-22	Support -mevex512 for AVX512DQ intrins	Haochen Jiang	3	-17/+31
2023-09-22	Support -mevex512 for AVX512F intrins	Haochen Jiang	9	-335/+445
2023-09-22	Disable zmm register and 512 bit libmvec call when !TARGET_EVEX512	Haochen Jiang	4	-33/+42
2023-09-22	Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins	Haochen Jiang	1	-78/+78
2023-09-22	Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins	Haochen Jiang	1	-94/+94
2023-09-22	Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins	Haochen Jiang	1	-113/+113
2023-09-22	Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins	Haochen Jiang	1	-47/+47
2023-09-22	Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins	Haochen Jiang	2	-348/+372
2023-09-22	Push evex512 target for 512 bit intrins	Haochen Jiang	1	-2678/+2705
2023-09-22	Push evex512 target for 512 bit intrins	Haochen Jiang	18	-221/+282
2023-09-22	Push evex512 target for 512 bit intrins	Haochen Jiang	1	-138/+153
2023-09-22	Push evex512 target for 512 bit intrins	Haochen Jiang	1	-455/+467
2023-09-22	Push evex512 target for 512 bit intrins	Haochen Jiang	1	-3666/+3745
2023-09-22	Initial support for -mevex512	Haochen Jiang	4	-1/+39
2023-09-21	RISC-V: Add more VLS unary tests	Juzhe-Zhong	3	-0/+173
2023-09-21	RISC-V: Support VLS mult high	Juzhe-Zhong	3	-0/+159
2023-09-21	RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emi...	Lehua Ding	1	-12/+21
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for --linux.	Iain Buclaw	3	-0/+63
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for i[34567]86--mingw and x86_64--mingw.	Iain Buclaw	3	-0/+46
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for --fuchsia*.	Iain Buclaw	3	-0/+64
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for --vxworks*	Iain Buclaw	3	-0/+47
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for --dragonfly*	Iain Buclaw	3	-0/+46
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for --solaris2*.	Iain Buclaw	3	-0/+47
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for --openbsd*	Iain Buclaw	3	-0/+47
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for --netbsd*	Iain Buclaw	3	-0/+46
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for --freebsd*	Iain Buclaw	3	-0/+46
2023-09-21	rust: Implement TARGET_RUST_OS_INFO for --darwin*	Iain Buclaw	3	-0/+50
2023-09-21	rust: Implement TARGET_RUST_CPU_INFO for i[34567]86-- and x86_64--	Iain Buclaw	3	-0/+155
2023-09-21	rust: Reintroduce TARGET_RUST_OS_INFO hook	Iain Buclaw	4	-0/+16
2023-09-21	rust: Reintroduce TARGET_RUST_CPU_INFO hook	Iain Buclaw	6	-3/+42
2023-09-21	rust: Add skeleton support and documentation for targetrustm hooks.	Iain Buclaw	11	-3/+220
2023-09-21	RISC-V: Enable undefined support for RVV auto-vectorization[PR110751]	Juzhe-Zhong	22	-53/+105
2023-09-21	RISC-V: Fix SUBREG move of VLS mode[PR111486]	Juzhe-Zhong	2	-1/+13
2023-09-21	check undefine_p for one more vr	Jiufu Guo	2	-1/+9
2023-09-21	using overflow_free_p to simplify pattern	Jiufu Guo	1	-30/+6
2023-09-21	RISC-V: Optimized for strided load/store with stride == element width[PR111450]	xuli	5	-17/+250
2023-09-21	RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names	Lehua Ding	2	-16/+16
2023-09-21	RISC-V: Support VLS INT <-> FP conversions	Juzhe-Zhong	15	-16/+882
2023-09-21	Daily bump.	GCC Administrator	9	-1/+421
2023-09-20	testsuite: Add test for already-fixed issue with _Pragma expansion [PR90400]	Lewis Hyatt	1	-0/+14
2023-09-20	libcpp: Fix ICE on #include after a line marker directive [PR61474]	Lewis Hyatt	4	-2/+21
2023-09-20	Tweak merge_range API.	Andrew MacLeod	1	-24/+15
2023-09-20	aarch64: Ensure const and sign correctness	Pekka Seppänen	1	-2/+3
2023-09-20	RISC-V: Remove math.h import to resolve missing stubs failures	Patrick O'Neill	1	-1/+0
2023-09-20	[frange] Remove special casing from unordered operators.	Aldy Hernandez	3	-16/+112
2023-09-20	c, c++: Accept __builtin_classify_type (typename)	Jakub Jelinek	10	-2/+387