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2023-05-26ada: Use computed value from os_constants to define sigset_tDoug Rupp1-1/+3
Remove hard coded definition and conform to standard usage of using computed os_constants for opaque type declarations. gcc/ada/ * libgnarl/s-osinte__qnx.ads (sigset_t): Modify declaration to use system.os_constants computed value. Align it.
2023-05-26ada: Fix another couple of unchecked conversions to Ada.Tags.TagEric Botcazou1-54/+17
They are problematic on platforms where the provenance of pointers must be tracked throughout their lifetime. gcc/ada/ * exp_sel.adb: Add clauses for Sem_Util, remove them for Opt, Sinfo and Sinfo.Nodes. (Build_K): Always use 'Tag of the object. (Build_S_Assignment): Likewise.
2023-05-26ada: Refine types for an accessibility-checking routinePiotr Trojanek1-2/+2
Code cleanup related to work on expression functions for GNATprove (which require accessibility checks even when they are not expanded and thus have no explicit return statements). gcc/ada/ * accessibility.adb (Is_Formal_Of_Current_Function): This routine expects an entity reference and not the entity itself, so its parameter is a Node_Id and not an Entity_Id.
2023-05-26ada: Clean style in expansion of array aggregatesPiotr Trojanek1-7/+5
Code cleanup only; semantics is unaffected. gcc/ada/ * exp_aggr.adb (Build_Array_Aggr_Code): Change variable to constant. (Check_Same_Aggr_Bounds): Fix style; remove unused initial value.
2023-05-26ada: Fix late extra formals creationRonan Desplanques1-0/+1
Before this patch, in some situations, a subprogram call could be expanded before the extra formals for the subprogram were created. This patch fixes the problem in those situations. gcc/ada/ * sem_ch6.adb (Analyze_Subprogram_Body_Helper): Create extra formals in more situations.
2023-05-26ada: Add missing guards in Selected_Range_ChecksEric Botcazou1-0/+2
gcc/ada/ * checks.adb (Selected_Range_Checks): Add guards to protect calls to Expr_Value on bounds.
2023-05-26ada: Enhance Is_Null_Range and Not_Null_Range predicatesEric Botcazou3-9/+11
Both predicates bail out if the bounds of the range are not known at compile time, whereas Compile_Time_Compare can deal with them in specific cases. gcc/ada/ * sem_eval.ads (Is_Null_Range): Remove requirements of compile-time known bounds and add WARNING line. (Not_Null_Range): Remove requirements of compile-time known bounds. * sem_eval.adb (Is_Null_Range): Fall back to Compile_Time_Compare. (Not_Null_Range): Likewise. * fe.h (Is_Null_Range): New predicate.
2023-05-26i386: Do not disable call to ix86_expand_vecop_qihi2Uros Bizjak1-1/+1
gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_vecop_qihi): Do not disable call to ix86_expand_vecop_qihi2.
2023-05-26Only use NO_REGS in cost calculation when !hard_regno_mode_ok for ↵liuhongt1-4/+8
GENERAL_REGS and mode. r14-172-g0368d169492017 replaces GENERAL_REGS with NO_REGS in cost calculation when the preferred register class are not known yet. It regressed powerpc PR109610 and PR109858, it looks too aggressive to use NO_REGS when mode can be allocated with GENERAL_REGS. The patch takes a step back, still use GENERAL_REGS when hard_regno_mode_ok for mode and GENERAL_REGS, otherwise uses NO_REGS. gcc/ChangeLog: PR target/109610 PR target/109858 * ira-costs.cc (scan_one_insn): Only use NO_REGS in cost calculation when !hard_regno_mode_ok for GENERAL_REGS and mode, otherwise still use GENERAL_REGS.
2023-05-26RISC-V: Fix zero-scratch-regs-3.c failJuzhe-Zhong1-2/+2
gcc/ChangeLog: * config/riscv/riscv.cc (vector_zero_call_used_regs): Add explict VL and drop VL in ops. Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
2023-05-26Daily bump.GCC Administrator5-1/+701
2023-05-26libstdc++: Add relational operators to __gnu_test::PointerBaseJonathan Wakely1-0/+9
The Cpp17Allocator requirements say that an allocator's pointer and const_pointer types must meet the Cpp17RandomAccessIterator requirements. That means our PointerBase helper for defining fancy pointer types should support the full set of relational operators. libstdc++-v3/ChangeLog: * testsuite/util/testsuite_allocator.h (PointerBase): Add relational operators.
2023-05-25testsuite: Require trampolines for nestev-vla testsDimitar Dimitrov3-0/+3
gcc/testsuite/ChangeLog: * gcc.dg/nested-vla-1.c: Require effective target trampolines. * gcc.dg/nested-vla-2.c: Ditto. * gcc.dg/nested-vla-3.c: Ditto. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2023-05-25In pipeline scheduling, insns should not be fusion in different BB blocks.Jin Ma1-1/+1
gcc/ChangeLog: * sched-deps.cc (sched_macro_fuse_insns): Insns should not be fusion in different BB blocks.
2023-05-25i386: Use 2x-wider modes when emulating QImode vector instructionsUros Bizjak3-171/+255
Rewrite ix86_expand_vecop_qihi2 to expand fo 2x-wider (e.g. V16QI -> V16HImode) instructions when available. Currently, the compiler generates following assembly for V16QImode multiplication (-mavx2): vpunpcklbw %xmm0, %xmm0, %xmm3 vpunpcklbw %xmm1, %xmm1, %xmm2 vpunpckhbw %xmm0, %xmm0, %xmm0 movl $255, %eax vpunpckhbw %xmm1, %xmm1, %xmm1 vpmullw %xmm3, %xmm2, %xmm2 vmovd %eax, %xmm3 vpmullw %xmm0, %xmm1, %xmm1 vpbroadcastw %xmm3, %xmm3 vpand %xmm2, %xmm3, %xmm0 vpand %xmm1, %xmm3, %xmm3 vpackuswb %xmm3, %xmm0, %xmm0 and only with -mavx512bw -mavx512vl generates: vpmovzxbw %xmm1, %ymm1 vpmovzxbw %xmm0, %ymm0 vpmullw %ymm1, %ymm0, %ymm0 vpmovwb %ymm0, %xmm0 Patched compiler generates more optimized code involving multiplication in 2x-wider mode in cases where missing truncate instruction has to be emulated with a permutation (-mavx2): vpmovzxbw %xmm0, %ymm0 vpmovzxbw %xmm1, %ymm1 movl $255, %eax vpmullw %ymm1, %ymm0, %ymm1 vmovd %eax, %xmm0 vpbroadcastw %xmm0, %ymm0 vpand %ymm1, %ymm0, %ymm0 vpackuswb %ymm0, %ymm0, %ymm0 vpermq $216, %ymm0, %ymm0 The patch also adjusts cost calculation of V*QImode emulations to account for generation of 2x-wider mode instructions. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Rewrite to expand to 2x-wider (e.g. V16QI -> V16HImode) instructions when available. Emulate truncation via ix86_expand_vec_perm_const_1 when native truncate insn is not available. (ix86_expand_vecop_qihi_partial) <case MULT>: Use pmovzx when available. Trivially rename some variables. (ix86_expand_vecop_qihi): Unconditionally call ix86_expand_vecop_qihi2. * config/i386/i386.cc (ix86_multiplication_cost): Rewrite cost calculation of V*QImode emulations to account for generation of 2x-wider mode instructions. (ix86_shift_rotate_cost): Update cost calculation of V*QImode emulations to account for generation of 2x-wider mode instructions. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512vl-pr95488-1.c: Revert 2023-05-18 change.
2023-05-25target/104327: Allow more inlining between different optimization levels.Georg-Johann Lay1-0/+16
avr-common.cc introduces the following options that are set depending on optimization level: -mgas-isr-prologues, -mmain-is-OS-task and -fsplit-wide-types-early. The inliner thinks that different options disallow cross-optimization inlining, so provide can_inline_p. gcc/ PR target/104327 * config/avr/avr.cc (avr_can_inline_p): New static function. (TARGET_CAN_INLINE_P): Define to that function.
2023-05-25target/82931: Make a pattern more generic to match more bit-transfers.Georg-Johann Lay3-10/+52
There is already a pattern in avr.md that matches single-bit transfers from one register to another one, but it only handled bit 0 of 8-bit registers. This change makes that pattern more generic so it matches more of similar single-bit transfers. gcc/ PR target/82931 * config/avr/avr.md (*movbitqi.0): Rename to *movbit<mode>.0-6. Handle any bit position and use mode QISI. * config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost of 2 insns for bit-transfer of respective style. gcc/testsuite/ PR target/82931 * gcc.target/avr/pr82931.c: New test.
2023-05-25arm: merge MVE_5 and MVE_6 iteratorsChristophe Lyon2-35/+34
MVE_5 and MVE_6 iterators are the same: this patch replaces MVE_6 with MVE_5 everywhere in mve.md and removes MVE_6 from iterators.md. 2023-05-25 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/iterators.md (MVE_6): Remove. * config/arm/mve.md: Replace MVE_6 with MVE_5.
2023-05-25VECT: Add decrement IV iteration loop control by variable amount supportJu-Zhe Zhong7-12/+558
This patch is supporting decrement IV by following the flow designed by Richard: (1) In vect_set_loop_condition_partial_vectors, for the first iteration of: call vect_set_loop_controls_directly. (2) vect_set_loop_controls_directly calculates "step" as in your patch. If rgc has 1 control, this step is the SSA name created for that control. Otherwise the step is a fresh SSA name, as in your patch. (3) vect_set_loop_controls_directly stores this step somewhere for later use, probably in LOOP_VINFO. Let's use "S" to refer to this stored step. (4) After the vect_set_loop_controls_directly call above, and outside the "if" statement that now contains vect_set_loop_controls_directly, check whether rgc->controls.length () > 1. If so, use vect_adjust_loop_lens_control to set the controls based on S. Then the only caller of vect_adjust_loop_lens_control is vect_set_loop_condition_partial_vectors. And the starting step for vect_adjust_loop_lens_control is always S. This patch has well tested for single-rgroup and multiple-rgroup (SLP) and passed all testcase in RISC-V port. Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com> gcc/ChangeLog: * tree-vect-loop-manip.cc (vect_adjust_loop_lens_control): New function. (vect_set_loop_controls_directly): Add decrement IV support. (vect_set_loop_condition_partial_vectors): Ditto. * tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): New variable. * tree-vectorizer.h (LOOP_VINFO_USING_DECREMENTING_IV_P): New macro. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: New test. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: New test. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: New test. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: New test.
2023-05-25aarch64: PR target/99195 Annotate complex FP patterns for vec-concat-zeroKyrylo Tkachov2-16/+80
This patch annotates the complex add and mla patterns for vec-concat-zero. Testing showed an interesting bug in our MD patterns where they were defined to match: (plus:VHSDF (match_operand:VHSDF 1 "register_operand" "0") (unspec:VHSDF [(match_operand:VHSDF 2 "register_operand" "w") (match_operand:VHSDF 3 "register_operand" "w") (match_operand:SI 4 "const_int_operand" "n")] FCMLA)) but the canonicalisation rules for PLUS require the more "complex" operand to be first so during combine when the new substituted patterns were attempted to be formed combine/recog would try to match: (plus:V2SF (unspec:V2SF [ (reg:V2SF 100) (reg:V2SF 101) (const_int 0 [0]) ] UNSPEC_FCMLA270) (reg:V2SF 99)) instead. This patch fixes the operands of the PLUS RTX in these patterns. Similar patterns for the dot-product instructions already used the right order. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_fcadd<rot><mode>): Rename to... (aarch64_fcadd<rot><mode><vczle><vczbe>): ... This. Fix canonicalization of PLUS operands. (aarch64_fcmla<rot><mode>): Rename to... (aarch64_fcmla<rot><mode><vczle><vczbe>): ... This. Fix canonicalization of PLUS operands. (aarch64_fcmla_lane<rot><mode>): Rename to... (aarch64_fcmla_lane<rot><mode><vczle><vczbe>): ... This. Fix canonicalization of PLUS operands. (aarch64_fcmla_laneq<rot>v4hf): Rename to... (aarch64_fcmla_laneq<rot>v4hf<vczle><vczbe>): ... This. Fix canonicalization of PLUS operands. (aarch64_fcmlaq_lane<rot><mode>): Fix canonicalization of PLUS operands. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_9.c: New test.
2023-05-25arm: Implement ACLE Data IntrinsicsChris Sidebottom7-4/+498
This patch implements a number of scalar data processing intrinsics from ACLE that were requested by some users. Some of these have fast single-instruction sequences for Armv6 and later, but even for earlier versions they can still emit an inline sequence or a call to libgcc (and ACLE recommends them being unconditionally available). Chris Sidebottom wrote most of the patch, I just cleaned it up, wired up some builtins and adjusted the tests. Bootstrapped and tested on arm-none-linux-gnueabihf. Co-authored-by: Chris Sidebottom <chris.sidebottom@arm.com> gcc/ChangeLog: * config/arm/arm.md (rbitsi2): Rename to... (arm_rbit): ... This. (ctzsi2): Adjust for the above. (arm_rev16si2): Convert to define_expand. (arm_rev16si2_alt1): New pattern. (arm_rev16si2_alt): Rename to... (*arm_rev16si2_alt2): ... This. * config/arm/arm_acle.h (__ror, __rorl, __rorll, __clz, __clzl, __clzll, __cls, __clsl, __clsll, __revsh, __rev, __revl, __revll, __rev16, __rev16l, __rev16ll, __rbit, __rbitl, __rbitll): Define intrinsics. * config/arm/arm_acle_builtins.def (rbit, rev16si2): Define builtins. gcc/testsuite/ChangeLog: * gcc.target/arm/acle/data-intrinsics-armv6.c: New test. * gcc.target/arm/acle/data-intrinsics-assembly.c: New test. * gcc.target/arm/acle/data-intrinsics-rbit.c: New test. * gcc.target/arm/acle/data-intrinsics.c: New test.
2023-05-25arm: Fix ICE due to infinite splitting [PR109800]Alex Coplan3-4/+9
In r11-966-g9a182ef9ee011935d827ab5c6c9a7cd8e22257d8 we introduce a simplification to emit_move_insn that attempts to simplify moves of the form: (set (subreg:M1 (reg:M2 ...)) (constant C)) where M1 and M2 are of equal mode size. That is problematic for the splitter vfp.md:no_literal_pool_df_immediate in the arm backend, which tries to pun an lvalue DFmode pseudo into DImode and assign a constant to it with emit_move_insn, as the new transformation simply undoes this, and we end up splitting indefinitely. This patch changes things around in the arm backend so that we use a DImode temporary (instead of DFmode) and first load the DImode constant into the pseudo, and then pun the pseudo into DFmode as an rvalue in a reg -> reg move. I believe this should be semantically equivalent but avoids the pathalogical behaviour seen in the PR. gcc/ChangeLog: PR target/109800 * config/arm/arm.md (movdf): Generate temporary pseudo in DImode instead of DFmode. * config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into DFmode as an rvalue. gcc/testsuite/ChangeLog: PR target/109800 * gcc.target/arm/pure-code/pr109800.c: New test.
2023-05-25target/109955 - handle pattern generated COND_EXPR without vcondRichard Biener1-1/+6
The following properly handles pattern matching generated COND_EXPRs which can still have embedded compares in vectorizable_condition which will always code generate the masked vector variant. We were requiring vcond with embedded comparisons instead of also allowing (as code generated) split compare and VEC_COND_EXPR. This fixes some of the fallout when removing vcond{,u,eq} expanders from the x86 backend. PR target/109955 * tree-vect-stmts.cc (vectorizable_condition): For embedded comparisons also handle the case when the target only provides vec_cmp and vcond_mask.
2023-05-25arc: Make TLS Local Dynamic work like Global Dynamic modelClaudiu Zissulescu1-23/+1
Current ARC's TLS Local Dynamic model is using two anchors to access data, namely `.tdata` and `.tbss`. This implementation is unnecessary complicated. However, the TLS Local Dynamic model has better results using Global Dynamic model and anchors. gcc/ChangeLog; * config/arc/arc.cc (arc_call_tls_get_addr): Simplify access using TLS Local Dynamic. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-05-25[aarch64] Ignore cost of scalar moves for seq in vector initialization.Prathamesh Kulkarni1-2/+42
gcc/ChangeLog: * config/aarch64/aarch64.cc (scalar_move_insn_p): New function. (seq_cost_ignoring_scalar_moves): Likewise. (aarch64_expand_vector_init): Call seq_cost_ignoring_scalar_moves.
2023-05-25aarch64: Implement vector FP absolute compare intrinsics with builtinsKyrylo Tkachov2-24/+40
While optimising some vector math library code with intrinsics we stumbled upon the issue in the testcase. The compiler should be generating a FACGT instruction but instead we generate: foo(__Float32x4_t, __Float32x4_t, __Float32x4_t): fabs v0.4s, v0.4s adrp x0, .LC0 ldr q31, [x0, #:lo12:.LC0] fcmgt v0.4s, v0.4s, v31.4s ret This is because the vcagtq_f32 intrinsic is open-coded in arm_neon.h as return vabsq_f32 (__a) > vabsq_f32 (__b) thus relying on the optimisers to merge it back together. But since one of the arms of the comparison is a vector constant the combine pass optimises the abs into it and tries matching: (set (reg:V4SI 101) (neg:V4SI (gt:V4SI (reg:V4SF 100) (const_vector:V4SF [ (const_double:SF 1.0e+2 [0x0.c8p+7]) repeated x4 ])))) and (set (reg:V4SI 101) (neg:V4SI (gt:V4SI (abs:V4SF (reg:V4SF 104)) (reg:V4SF 103)))) instead of what we want: (insn 13 9 14 2 (set (reg/i:V4SI 32 v0) (neg:V4SI (gt:V4SI (abs:V4SF (reg:V4SF 98)) (abs:V4SF (reg:V4SF 96))))) I don't really see a good way around that with our current implementation of these intrinsics. Therefore this patch reimplements these intrinsics with aarch64 builtins that generate the RTL for these instructions directly. Apparently we already had them defined in aarch64-simd-builtins.def and have been using them for the fp16 case already. I realise that this approach is against the general principle of expressing intrinsics in the higher-level constructs, so I'm willing to listen to counter-arguments. That said, the FACGT/FACGE instructions are as fast as the non-ABS comparison instructions on all microarchitectures that I know of so it should always be a win to have them in the merged form rather than split the fabs step separately or try to hoist it. And the testcase does come from real library code that we're trying to optimise. With this patch for the testcase we generate: foo: adrp x0, .LC0 ldr q31, [x0, #:lo12:.LC0] facgt v0.4s, v0.4s, v31.4s ret gcc/ChangeLog: * config/aarch64/arm_neon.h (vcage_f64): Reimplement with builtins. (vcage_f32): Likewise. (vcages_f32): Likewise. (vcageq_f32): Likewise. (vcaged_f64): Likewise. (vcageq_f64): Likewise. (vcagts_f32): Likewise. (vcagt_f32): Likewise. (vcagt_f64): Likewise. (vcagtq_f32): Likewise. (vcagtd_f64): Likewise. (vcagtq_f64): Likewise. (vcale_f32): Likewise. (vcale_f64): Likewise. (vcaled_f64): Likewise. (vcales_f32): Likewise. (vcaleq_f32): Likewise. (vcaleq_f64): Likewise. (vcalt_f32): Likewise. (vcalt_f64): Likewise. (vcaltd_f64): Likewise. (vcaltq_f32): Likewise. (vcaltq_f64): Likewise. (vcalts_f32): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/facgt_constpool_1.c: New test.
2023-05-25i386: Fix incorrect intrinsic signature for AVX512 s{lli|rai|rli}Hu, Lin16-167/+302
This patch aims to fix incorrect intrinsic signature for _mm{512|256|}_s{lli|rai|rli}_epi*. gcc/ChangeLog: PR target/109173 PR target/109174 * config/i386/avx512bwintrin.h (_mm512_srli_epi16): Change type from int to const int or const int to const unsigned int. (_mm512_mask_srli_epi16): Ditto. (_mm512_slli_epi16): Ditto. (_mm512_mask_slli_epi16): Ditto. (_mm512_maskz_slli_epi16): Ditto. (_mm512_srai_epi16): Ditto. (_mm512_mask_srai_epi16): Ditto. (_mm512_maskz_srai_epi16): Ditto. * config/i386/avx512fintrin.h (_mm512_slli_epi64): Ditto. (_mm512_mask_slli_epi64): Ditto. (_mm512_maskz_slli_epi64): Ditto. (_mm512_srli_epi64): Ditto. (_mm512_mask_srli_epi64): Ditto. (_mm512_maskz_srli_epi64): Ditto. (_mm512_srai_epi64): Ditto. (_mm512_mask_srai_epi64): Ditto. (_mm512_maskz_srai_epi64): Ditto. (_mm512_slli_epi32): Ditto. (_mm512_mask_slli_epi32): Ditto. (_mm512_maskz_slli_epi32): Ditto. (_mm512_srli_epi32): Ditto. (_mm512_mask_srli_epi32): Ditto. (_mm512_maskz_srli_epi32): Ditto. (_mm512_srai_epi32): Ditto. (_mm512_mask_srai_epi32): Ditto. (_mm512_maskz_srai_epi32): Ditto. * config/i386/avx512vlbwintrin.h (_mm256_mask_srai_epi16): Ditto. (_mm256_maskz_srai_epi16): Ditto. (_mm_mask_srai_epi16): Ditto. (_mm_maskz_srai_epi16): Ditto. (_mm256_mask_slli_epi16): Ditto. (_mm256_maskz_slli_epi16): Ditto. (_mm_mask_slli_epi16): Ditto. (_mm_maskz_slli_epi16): Ditto. (_mm_maskz_srli_epi16): Ditto. * config/i386/avx512vlintrin.h (_mm256_mask_srli_epi32): Ditto. (_mm256_maskz_srli_epi32): Ditto. (_mm_mask_srli_epi32): Ditto. (_mm_maskz_srli_epi32): Ditto. (_mm256_mask_srli_epi64): Ditto. (_mm256_maskz_srli_epi64): Ditto. (_mm_mask_srli_epi64): Ditto. (_mm_maskz_srli_epi64): Ditto. (_mm256_mask_srai_epi32): Ditto. (_mm256_maskz_srai_epi32): Ditto. (_mm_mask_srai_epi32): Ditto. (_mm_maskz_srai_epi32): Ditto. (_mm256_srai_epi64): Ditto. (_mm256_mask_srai_epi64): Ditto. (_mm256_maskz_srai_epi64): Ditto. (_mm_srai_epi64): Ditto. (_mm_mask_srai_epi64): Ditto. (_mm_maskz_srai_epi64): Ditto. (_mm_mask_slli_epi32): Ditto. (_mm_maskz_slli_epi32): Ditto. (_mm_mask_slli_epi64): Ditto. (_mm_maskz_slli_epi64): Ditto. (_mm256_mask_slli_epi32): Ditto. (_mm256_maskz_slli_epi32): Ditto. (_mm256_mask_slli_epi64): Ditto. (_mm256_maskz_slli_epi64): Ditto. gcc/testsuite/ChangeLog: PR target/109173 PR target/109174 * gcc.target/i386/pr109173-1.c: New test. * gcc.target/i386/pr109174-1.c: Ditto.
2023-05-25ada: Missing warning on null-excluding array aggregate componentJavier Miranda2-3/+165
The compiler does not report warnings on the initialization of arrays of null-excluding access type components by means of iterated component association, when the expression initializing each component is either a conditional expression or a case expression that may initialize some component with a null value. gcc/ada/ * sem_aggr.adb (Warn_On_Null_Component_Association): New subprogram. (Empty_Range): Adding missing support for iterated component association node. (Resolve_Array_Aggregate): Report warning on iterated component association that may initialize some component of an array of null-excluding access type components with a null value. * exp_ch4.adb (Expand_N_Expression_With_Actions): Add missing type check since the subtype of the EWA node and the subtype of the expression may differ.
2023-05-25ada: Expect Exceptional_Cases as a context for attribute OldPiotr Trojanek1-6/+10
When determining whether attribute Old is evaluated conditionally, we must also expect it to appear in the recently added contract Exceptional_Cases. gcc/ada/ * sem_util.adb (Determining_Expressions): Fix style; fix layout and ordering of pragma names; expect pragma Exceptional_Cases.
2023-05-25ada: Use procedural variant of Next_Index where possiblePiotr Trojanek2-4/+4
Code cleanup; semantics is unaffected. gcc/ada/ * einfo-utils.adb (Write_Entity_Info): Use procedural Next_Index. * sem_aggr.adb (Collect_Aggr_Bounds): Reuse local constant. (Resolve_Null_Array_Aggregate): Use procedural Next_Index.
2023-05-25ada: Crash on empty aggregate using the Ada 2022 notationJavier Miranda1-1/+3
The compiler crashes processing an empty aggregate initializing a component of a discriminated record type using the Ada 2022 notation (that is, []). gcc/ada/ * exp_aggr.adb (Build_Record_Aggr_Code): Protect access to aggregate components when the aggregate is empty.
2023-05-25ada: Enable Support_Atomic_Primitives on VxWorks 7 PPCJohannes Kliemann2-2/+2
gcc/ada/ * libgnat/system-vxworks7-ppc-kernel.ads: Enable Support_Atomic_Primitives. * libgnat/system-vxworks7-ppc-rtp-smp.ads: Likewise.
2023-05-25ada: Fix internal error on declare-expression in post-conditionEric Botcazou1-5/+7
It comes from an incorrect node sharing in the expanded tree. gcc/ada/ * sem_ch3.adb (Find_Type_Of_Object): Copy the object definition when building the subtype declaration in the case of a spec expression.
2023-05-25ada: Require successful build of xsnamestTom Tromey1-1/+1
While experimenting, I introduced a compilation error into xsnamest. This took a little while to track down because, while the error was in the log, the build did not stop. This patch changes Make-generated.in to require a successful build of this program. gcc/ada/ * Make-generated.in (ada/stamp-snames): Check result of gnatmake.
2023-05-25ada: Minor adjustments to Standard_AddressEric Botcazou2-4/+16
Standard_Address is an internal entity that is meant to be a clone of System.Address built at compilation startup. It needs to be seen as a bona-fide address by the code generator. For the sake of completeness, it is also given its modulus, although this does not matter in practice. gcc/ada/ * cstand.adb (Create_Standard): Set the Is_Descendant_Of_Address flag on Standard_Address. * freeze.adb (Freeze_Entity): Copy the modulus of System.Address onto Standard_Address.
2023-05-25ada: Add size clause to System.AddressEric Botcazou43-0/+86
Standard'Address_Size is the value provided by the code generator for the size of pointers, and it is set as the default size of every thin pointer by the front-end. Now it is documented in the GNAT RM as having the value of System.Address'Size, which is indeed the case on (correctly configured) platforms where pointers contain exactly the number of bits that are needed to address the memory space. However, on platforms where pointers contain additional bits of metadata, it has a larger value and the documented relation does not hold, which also means that unchecked conversions between System.Address and pointers are seen as potentially problematic. In order to fix the discrepancy on these platforms, this change adds the obvious size clause to System.Address, which is confirming on all the other (correctly configured) platforms. gcc/ada/ * libgnat/system-aix.ads (Address): Likewise. * libgnat/system-darwin-arm.ads (Address): Likewise. * libgnat/system-darwin-ppc.ads (Address): Likewise. * libgnat/system-darwin-x86.ads (Address): Likewise. * libgnat/system-djgpp.ads (Address): Likewise. * libgnat/system-dragonfly-x86_64.ads (Address): Likewise. * libgnat/system-freebsd.ads (Address): Likewise. * libgnat/system-hpux-ia64.ads (Address): Likewise. * libgnat/system-hpux.ads (Address): Likewise. * libgnat/system-linux-alpha.ads (Address): Likewise. * libgnat/system-linux-arm.ads (Address): Likewise. * libgnat/system-linux-hppa.ads (Address): Likewise. * libgnat/system-linux-ia64.ads (Address): Likewise. * libgnat/system-linux-m68k.ads (Address): Likewise. * libgnat/system-linux-mips.ads (Address): Likewise. * libgnat/system-linux-ppc.ads (Address): Likewise. * libgnat/system-linux-riscv.ads (Address): Likewise. * libgnat/system-linux-s390.ads (Address): Likewise. * libgnat/system-linux-sh4.ads (Address): Likewise. * libgnat/system-linux-sparc.ads (Address): Likewise. * libgnat/system-linux-x86.ads (Address): Likewise. * libgnat/system-lynxos178-ppc.ads (Address): Likewise. * libgnat/system-lynxos178-x86.ads (Address): Likewise. * libgnat/system-mingw.ads (Address): Likewise. * libgnat/system-qnx-arm.ads (Address): Likewise. * libgnat/system-rtems.ads (Address): Likewise. * libgnat/system-solaris-sparc.ads (Address): Likewise. * libgnat/system-solaris-x86.ads (Address): Likewise. * libgnat/system-vxworks-ppc-kernel.ads (Address): Likewise. * libgnat/system-vxworks-ppc-rtp-smp.ads (Address): Likewise. * libgnat/system-vxworks-ppc-rtp.ads (Address): Likewise. * libgnat/system-vxworks7-aarch64-rtp-smp.ads (Address): Likewise. * libgnat/system-vxworks7-aarch64.ads (Address): Likewise. * libgnat/system-vxworks7-arm-rtp-smp.ads (Address): Likewise. * libgnat/system-vxworks7-arm.ads (Address): Likewise. * libgnat/system-vxworks7-ppc-kernel.ads (Address): Likewise. * libgnat/system-vxworks7-ppc-rtp-smp.ads (Address): Likewise. * libgnat/system-vxworks7-ppc64-kernel.ads (Address): Likewise. * libgnat/system-vxworks7-ppc64-rtp-smp.ads (Address): Likewise. * libgnat/system-vxworks7-x86-kernel.ads (Address): Likewise. * libgnat/system-vxworks7-x86-rtp-smp.ads (Address): Likewise. * libgnat/system-vxworks7-x86_64-kernel.ads (Address): Likewise. * libgnat/system-vxworks7-x86_64-rtp-smp.ads (Address): Likewise.
2023-05-25ada: Fix error message for Aggregate aspectMarc Poulhiès1-2/+2
The error message was wrongly using % instead of & in the format string, causing the displayed message to refer to incorrect names in some cases. gcc/ada/ * sem_ch13.adb (Check_Aspect_At_Freeze_Point): fix format string, use existing local Ident.
2023-05-25ada: Switch from E_Void to Is_Not_Self_HiddenBob Duff6-80/+71
We had previously used Ekind = E_Void to indicate that a declaration is self-hidden. We now use the Is_Not_Self_Hidden flag instead. This allows us to avoid many "vanishing fields", which are (possibly-latent) bugs, and we now enable the assertions in Atree that detect such bugs. gcc/ada/ * atree.adb (Check_Vanishing_Fields): Fix bug in the "blah type only" cases. Remove the special cases for E_Void. Misc cleanup. (Mutate_Nkind): Disallow mutating to the same kind. (Mutate_Ekind): Disallow mutating to E_Void. (From E_Void is still OK -- entities start out as E_Void by default.) Fix bug in statistics gathering -- was setting the wrong count. Enable Check_Vanishing_Fields for entities. * sem_ch8.adb (Is_Self_Hidden): New function. (Find_Direct_Name): Call Is_Self_Hidden to use the new Is_Not_Self_Hidden flag to determine whether a declaration is hidden from all visibility by itself. This replaces the old method of checking E_Void. (Find_Expanded_Name): Likewise. (Find_Selected_Component): Likewise. * sem_util.adb (Enter_Name): Remove setting of Ekind to E_Void. * sem_ch3.adb: Set the Is_Not_Self_Hidden flag in appropriate places. Comment fixes. (Inherit_Component): Remove setting of Ekind to E_Void. * sem_ch9.adb (Analyze_Protected_Type_Declaration): Update comment. Skip Itypes, which should not be turned into components. * atree.ads (Mutate_Nkind): Document error case. (Mutate_Ekind): Remove comments apologizing for E_Void mutations. Document error cases.
2023-05-25ada: Decouple size of addresses and pointers from size of memory spaceEric Botcazou11-31/+18
This decouples the size of the types representing addresses and pointers, which is Standard'Address_Size, from the size of the memory space, which is System.Memory_Size (more precisely log2 of it). They are tied through the definition of System.Address: type Address is mod Memory_Size; so Standard'Address_Size >= log2 (System.Memory_Size) necessarily, but the equality does not hold on platforms where addresses and pointers contain additional bits of metadata. gcc/ada/ * libgnat/a-ststio.adb (Set_Mode): Test System.Memory_Size. * libgnat/g-debuti.ads (Address_64): Likewise. * libgnat/i-c.ads: Add with clause for System. (ptrdiff_t): Define based on the size of memory space. (size_t): Likewise. * libgnat/s-crtl.ads (size_t): Likewise. (ssize_t): Likewise. * libgnat/s-memory.ads (size_t): Likewise. * libgnat/s-parame.ads (Size_Type): Likewise. * libgnat/s-parame__hpux.ads (Size_Type): Likewise. * libgnat/s-parame__posix2008.ads (Size_Type): Likewise. * libgnat/s-parame__vxworks.ads (Size_Type): Likewise. * libgnat/s-putima.adb (Signed_Address): Likewise. (Unsigned_Address): Likewise. * libgnat/s-stoele.ads (Storage_Offset): Likewise.
2023-05-25ada: Fix copying of quantified expressionsPiotr Trojanek1-1/+4
While visiting the AST as part of routine New_Copy_Tree we maintain an EWA_Level variable in a stack-like fashion. This worked fine for expression with actions nodes but not for quantified expressions. gcc/ada/ * sem_util.adb (Visit_Node): Decrement EWA_Level with the same condition as when it was incremented.
2023-05-25ada: Deconstruct a no longer used parameter of New_Copy_TreePiotr Trojanek2-19/+10
Parameter Scopes_In_EWA_OK of New_Copy_Tree was introduced in 2018 to deal with expressions-with-actions (EWA) in the build-in-place machinery. However, after changes made in 2022 it is no longer used by any caller. Cleanup related to handling of expression functions in GNATprove; semantics is unaffected. gcc/ada/ * sem_util.ads (New_Copy_Tree): Remove Scopes_In_EWA_OK from spec; adapt comment. * sem_util.adb (New_Copy_Tree): Remove Scopes_In_EWA_OK from body; adapt code.
2023-05-25ada: Clean up copying of node treesPiotr Trojanek1-3/+1
Before calling routine In_Entity_Map we checked if the entity map is present; inside this routine we checked this again. Code cleanup; semantics is unaffected. gcc/ada/ * sem_util.adb (Update_New_Entities): Remove redundant check for entity map being present.
2023-05-25ada: Simplify copying of node listsPiotr Trojanek1-6/+1
When creating a copy of a node list we called Copy_Entity for entities and Copy_Separate_Tree for other nodes. This was unnecessary, because the Copy_Separate_Tree when called on entities will just do Copy_Entity. Code cleanup; semantics is unaffected. gcc/ada/ * atree.adb (Copy_List): Call Copy_Separate_Tree for both entities and other nodes.
2023-05-25ada: Avoid duplicated streaming subprogramsSteve Baird5-150/+286
In some common cases, a reference to Some_Type'Some_Streaming_Attribute causes the needed subprogram to be generated "on demand". If there are multiple such references (e.g., two calls to Some_Type'Write) then we want to avoid generating multiple essentially-identical subprograms. This change implies that a generated streaming subprogram may now have multiple call sites, so we can no longer use the source position information from the (one and only) call site. If an exception is raised during a streaming operation, this can make a difference in the reported raise location. gcc/ada/ * exp_attr.adb (Cached_Streaming_Ops): A new package, providing maps to save previously-generated Read/Write/Input/Output procedures. (Expand_N_Attribute_Reference): When a new subprogram is generated for a Read/Write/Input/Output attribute reference, record that type/subp pair in the appropriate Cached_Streaming_Ops map. (Find_Stream_Subprogram): Check the appropriate Cached_Streaming_Ops map to see if an appropriate subprogram has already been generated. If so, then return it. The appropriateness test includes a call to a new nested subprogram, In_Available_Context. * exp_strm.ads, exp_strm.adb: Do not pass in a Loc parameter (or a source-location-bearing Nod parameter) to the 16 procedures provided for building streaming-related subprograms. Use the source location of the type instead. * exp_dist.adb, exp_ch3.adb: Adapt to Exp_Strm spec changes. For these calls the source location of the type was already being used.
2023-05-25ada: Fix crash during function return analysisMarc Poulhiès1-0/+1
The compiler would crash when checking type relation between the function's return type and the type of the expression used in the return statement. It would not work if the function's return type is an access type and the expression is not. gcc/ada/ * sem_ch6.adb (Analyze_Function_Return): Add missing Is_Access_Type check before accessing the Designated_Type field.
2023-05-25ada: Remove unused initial value of a local variablePiotr Trojanek1-1/+1
Cleanup related to improved handling of expression functions in GNATprove; semantics is unaffected. gcc/ada/ * sem_ch6.adb (Analyze_Return_Type): Remove unused initial value.
2023-05-25ada: Fix (again) incorrect handling of Aggregate aspectMarc Poulhiès2-7/+14
Previous fix stopped the processing of the Aggregate aspect early, skipping the call to Record_Rep_Item, making later call to Resolve_Container_Aggregate fail. Also, the previous fix would not handle correctly the case where the type is private and the check for non-array type can only be done at the freeze point with the full type. Adapt the resolving of the aspect when the input is not correct and the parameters can't be resolved. gcc/ada/ * sem_ch13.adb (Analyze_One_Aspect): Call Record_Rep_Item. (Check_Aspect_At_Freeze_Point): Check the aspect is specified on non-array type only... (Analyze_One_Aspect): ... instead of doing it too early here. * sem_aggr.adb (Resolve_Container_Aggregate): Do nothing in case the parameters failed to resolve.
2023-05-25ada: Prevent search of calls in preconditions from going too farPiotr Trojanek1-0/+5
When determining whether a call to protected function appears within a pragma expression we can safely stop at the subprogram body. Cleanup related to recently added support for a new SPARK aspects, whose implementation was based on Contract_Cases. gcc/ada/ * sem_util.adb (Check_Internal_Protected_Use): Add standard protection against search going too far.
2023-05-25ada: Fix comments for recently added SPARK aspectsPiotr Trojanek5-9/+19
Implementation of contract Subprogram_Variant and Exceptional_Cases was based on the existing code for Contract_Cases, i.e. on the existing occurrences of Aspect_Contract_Cases, Name_Contract_Cases and Pragma_Contract_Cases. However, occurrences of "Contract_Cases" itself in the comments were not updated. gcc/ada/ * contracts.adb (Add_Pre_Post_Condition): Mention new aspects in the comment. * contracts.ads (Add_Contract_Item): Likewise. (Analyze_Subprogram_Body_Stub_Contract): Likewise. * sem_prag.adb (Contract_Freeze_Error): Likewise. (Ensure_Aggregate_Form): Likewise. * sem_prag.ads (Find_Related_Declaration_Or_Body): Likewise. * sinfo.ads (Is_Generic_Contract_Pragma): Likewise.
2023-05-25ada: Add missing supportive code for recently added SPARK aspectsPiotr Trojanek2-21/+27
Fix minor inconsistencies with the recently added SPARK aspects Exceptional_Cases and Subprogram_Variant, whose implementation is based on Contract_Cases. gcc/ada/ * aspects.ads (Implementation_Defined_Aspect): Recently added aspects are implementation-defined, just like Contract_Cases. * sem_prag.ads (Aspect_Specifying_Pragma): Recently added aspects have corresponding pragmas, just like Contract_Cases. (Pragma_Significant_To_Subprograms): Recently added aspects are significant to subprograms, just like Contract_Cases.
generated by cgit v1.1 at 2025-08-03 06:20:30 +0000