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2023-06-01RISC-V: Introduce vfloat16m{f}*_t and their machine mode.Pan Li7-10/+49
This patch would like to introduce the built-in type vfloat16m{f}*_t, as well as their machine mode VNx*HF. They depend on architecture zvfhmin or zvfh. When givn the zvfhmin or zvfh, the macro TARGET_VECTOR_ELEN_FP_16 will be true. The underlying PATCH will implement the zvfhmin extension based on this. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin and zvfh. * config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16. (main): Disable FP16 tuple. * config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro. (TARGET_VECTOR_ELEN_FP_16): Ditto. * config/riscv/riscv-vector-builtins.cc (check_required_extensions): Add FP16. * config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type. (vfloat16mf2_t): Ditto. (vfloat16m1_t): Ditto. (vfloat16m2_t): Ditto. (vfloat16m4_t): Ditto. (vfloat16m8_t): Ditto. * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16): New macro. * config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16 machine mode based on TARGET_VECTOR_ELEN_FP_16.
2023-06-01libstdc++: Reduce <functional> inclusion to <stl_algobase.h>François Dumont6-150/+149
Move the std::search definition from stl_algo.h to stl_algobase.h and use the later in <functional>. For consistency also move std::__parallel::search and associated helpers from <parallel/stl_algo.h> to <parallel/stl_algobase.h> so that std::__parallel::search is accessible along with std::search. libstdc++-v3/ChangeLog: * include/bits/stl_algo.h (std::__search, std::search(_FwdIt1, _FwdIt1, _FwdIt2, _FwdIt2, _BinPred)): Move... * include/bits/stl_algobase.h: ...here. * include/std/functional: Replace <stl_algo.h> include by <stl_algobase.h>. * include/parallel/algo.h (std::__parallel::search<_FIt1, _FIt2, _BinaryPred>) (std::__parallel::__search_switch<_FIt1, _FIt2, _BinaryPred, _ItTag1, _ItTag2>): Move... * include/parallel/algobase.h: ...here. * include/experimental/functional: Remove <bits/stl_algo.h> and <parallel/algorithm> includes. Include <bits/stl_algobase.h>.
2023-05-31c++: make -fpermissive avoid -Werror=narrowingJason Merrill1-1/+2
Currently we make -Wnarrowing an error by default by forcing pedantic_errors on, but for consistency -fpermissive should prevent that. In general I'm inclined to move away from using permerror in favor of this kind of model, with specific flags for each diagnostic. gcc/cp/ChangeLog: * typeck2.cc (check_narrowing): Check flag_permissive.
2023-06-01Daily bump.GCC Administrator4-1/+432
2023-06-01RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscsJuzhe-Zhong3-0/+61
gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (register_frm): New function. (DEF_RVV_FRM_ENUM): New macro. (handle_pragma_vector): Add FRM enum * config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro. (RNE): Ditto. (RTZ): Ditto. (RDN): Ditto. (RUP): Ditto. (RMM): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/frm-1.c: New test.
2023-05-31Refactor wi::bswap as a function (instead of a method).Roger Sayle5-24/+36
This patch implements Richard Sandiford's suggestion from https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618215.html that wi::bswap (and a new wi::bitreverse) should be functions, and ideally only accessors are member functions. This patch implements the first step, moving/refactoring wi::bswap. 2023-05-31 Roger Sayle <roger@nextmovesoftware.com> Richard Sandiford <richard.sandiford@arm.com> gcc/ChangeLog * fold-const-call.cc (fold_const_call_ss) <CFN_BUILT_IN_BSWAP*>: Update call to wi::bswap. * simplify-rtx.cc (simplify_const_unary_operation) <case BSWAP>: Update call to wi::bswap. * tree-ssa-ccp.cc (evaluate_stmt) <case BUILT_IN_BSWAP*>: Update calls to wi::bswap. * wide-int.cc (wide_int_storage::bswap): Remove/rename to... (wi::bswap_large): New function, with revised API. * wide-int.h (wi::bswap): New (template) function prototype. (wide_int_storage::bswap): Remove method. (sext_large, zext_large): Consistent indentation/line wrapping. (bswap_large): Prototype helper function containing implementation. (wi::bswap): New template wrapper around bswap_large.
2023-05-31libstdc++: Add separate autoconf macro for std::float_t and std::double_t ↵Jonathan Wakely4-6/+62
[PR109818] This should make it possible to use openlibm with djgpp (and other targets with missing C99 <math.h> functions). The <math.h> from openlibm provides all the functions, but not the float_t and double_t typedefs. By separating the autoconf checks for the functionsand the typedefs, we don't disable support for all the functions just because those typedefs are not present. libstdc++-v3/ChangeLog: PR libstdc++/109818 * acinclude.m4 (GLIBCXX_ENABLE_C99): Add separate check for float_t and double_t and define HAVE_C99_FLT_EVAL_TYPES. * config.h.in: Regenerate. * configure: Regenerate. * include/c_global/cmath (float_t, double_t): Guard using new _GLIBCXX_HAVE_C99_FLT_EVAL_TYPES macro.
2023-05-31libstdc++: Stop using _GLIBCXX_USE_C99_MATH_TR1 in <cmath>Jonathan Wakely17-106/+396
Similar to the three commits r14-908, r14-909 and r14-910, the _GLIBCXX_USE_C99_MATH_TR1 macro is misleading when it is also used for <cmath>, not only for <tr1/cmath> headers. It is also wrong, because the configure checks for TR1 use -std=c++98 and a target might define the C99 features for C++11 but not for C++98. Add separate configure checks for the <math.h> functions using -std=c++11 for the checks. Use the new macro defined by those checks in the C++11-specific parts of <cmath>, and in <complex>, <random> etc. The check that defines _GLIBCXX_NO_C99_ROUNDING_FUNCS is only needed for the C++11 <cmath> checks, so remove that from GLIBCXX_CHECK_C99_TR1 and only do it for GLIBCXX_ENABLE_C99. libstdc++-v3/ChangeLog: * acinclude.m4 (GLIBCXX_ENABLE_C99): Add checks for C99 math functions and define _GLIBCXX_USE_C99_MATH_FUNCS. Move checks for C99 rounding functions to here. (GLIBCXX_CHECK_C99_TR1): Remove checks for C99 rounding functions from here. * config.h.in: Regenerate. * configure: Regenerate. * include/bits/random.h: Use _GLIBCXX_USE_C99_MATH_FUNCS instead of _GLIBCXX_USE_C99_MATH_TR1. * include/bits/random.tcc: Likewise. * include/c_compatibility/math.h: Likewise. * include/c_global/cmath: Likewise. * include/ext/random: Likewise. * include/ext/random.tcc: Likewise. * include/std/complex: Likewise. * testsuite/20_util/from_chars/4.cc: Likewise. * testsuite/20_util/from_chars/8.cc: Likewise. * testsuite/26_numerics/complex/proj.cc: Likewise. * testsuite/26_numerics/headers/cmath/60401.cc: Likewise. * testsuite/26_numerics/headers/cmath/types_std_c++0x.cc: Likewise. * testsuite/lib/libstdc++.exp (check_v3_target_cstdint): Likewise. * testsuite/util/testsuite_random.h: Likewise.
2023-05-31libstdc++: Express std::vector's size() <= capacity() invariant in codeJonathan Wakely3-4/+44
This adds optimizer hints so that GCC knows that size() <= capacity() is always true. This allows the compiler to optimize away re-allocating paths when assigning new values to the vector without resizing it, e.g., vec.assign(vec.size(), new_val). libstdc++-v3/ChangeLog: * include/bits/stl_vector.h (_Vector_base::_M_invariant()): New function. (vector::size(), vector::capacity()): Call _M_invariant(). * testsuite/23_containers/vector/capacity/invariant.cc: New test. * testsuite/23_containers/vector/types/1.cc: Add suppression for false positive warning (PR110060).
2023-05-31libstdc++: Fix build for targets without _Float128 [PR109921]Jonathan Wakely1-1/+1
My r14-1431-g7037e7b6e4ac41 change caused the _Float128 overload to be compiled unconditionally, by moving the USE_STRTOF128_FOR_FROM_CHARS check into the function body. That function should still only be compiled if the target actually supports _Float128. libstdc++-v3/ChangeLog: PR libstdc++/109921 * src/c++17/floating_from_chars.cc: Check __FLT128_MANT_DIG__ is defined before trying to use _Float128.
2023-05-31libstdc++: Fix configure test for 32-bit targetsJonathan Wakely2-2/+2
The -mlarge model for msp430-elf uses 20-bit pointers, which means that sizeof(void*) == 4 and so the r14-1432-g51cf0b3949b88b change gives the wrong answer. Check __INTPTR_WIDTH__ >= 32 instead. libstdc++-v3/ChangeLog: * acinclude.m4 (GLIBCXX_ZONEINFO_DIR): Fix for 32-bit pointers to check __INT_PTR_WIDTH__ instead of sizeof(void*). * configure: Regenerate.
2023-05-31testsuite: rename force_conventional_outputBernhard Reutner-Fischer4-15/+15
The procedure force_conventional_output_for is a bit misnomed, what it primarily does is to set the required options for the corresponding test. So rename the proc to set_required_options_for and also rename the participating variable accordingly. gcc/testsuite/ChangeLog: * lib/gcc-dg.exp: Rename gcc_force_conventional_output to gcc_set_required_options. * lib/target-supports.exp: Rename force_conventional_output_for to set_required_options_for. * lib/scanasm.exp: Adjust callers. * lib/scanrtl.exp: Same.
2023-05-31aarch64: PR target/99195 Annotate dot-product patterns for vec-concat-zeroKyrylo Tkachov2-5/+43
This straightforward patch annotates the dotproduct instructions, including the i8mm ones. Tests included. Nothing unexpected here. Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (<sur>dot_prod<vsi2qi>): Rename to... (<sur>dot_prod<vsi2qi><vczle><vczbe>): ... This. (usdot_prod<vsi2qi>): Rename to... (usdot_prod<vsi2qi><vczle><vczbe>): ... This. (aarch64_<sur>dot_lane<vsi2qi>): Rename to... (aarch64_<sur>dot_lane<vsi2qi><vczle><vczbe>): ... This. (aarch64_<sur>dot_laneq<vsi2qi>): Rename to... (aarch64_<sur>dot_laneq<vsi2qi><vczle><vczbe>): ... This. (aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi>): Rename to... (aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi><vczle><vczbe>): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_11.c: New test.
2023-05-31aarch64: PR target/99195 Annotate saturating mult patterns for vec-concat-zeroKyrylo Tkachov3-11/+54
This patch goes through the various alphabet soup saturating multiplication patterns, including those in TARGET_RDMA and annotates them with <vczle><vczbe>. Many other patterns are widening and always write the full 128-bit vectors so this annotation doesn't apply to them. Nothing out of the ordinary in this patch. Bootstrapped and tested on aarch64-none-linux and aarch64_be-none-elf. gcc/ChangeLog: PR target/99195 * config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh<mode>): Rename to... (aarch64_sq<r>dmulh<mode><vczle><vczbe>): ... This. (aarch64_sq<r>dmulh_n<mode>): Rename to... (aarch64_sq<r>dmulh_n<mode><vczle><vczbe>): ... This. (aarch64_sq<r>dmulh_lane<mode>): Rename to... (aarch64_sq<r>dmulh_lane<mode><vczle><vczbe>): ... This. (aarch64_sq<r>dmulh_laneq<mode>): Rename to... (aarch64_sq<r>dmulh_laneq<mode><vczle><vczbe>): ... This. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>): Rename to... (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode><vczle><vczbe>): ... This. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Rename to... (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>): ... This. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Rename to... (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>): ... This. gcc/testsuite/ChangeLog: PR target/99195 * gcc.target/aarch64/simd/pr99195_1.c: Add tests for qdmulh, qrdmulh. * gcc.target/aarch64/simd/pr99195_10.c: New test.
2023-05-31btf: improve -dA comments for testsuiteDavid Faust17-69/+224
Many BTF type kinds refer to other types via index to the final types list. However, the order of the final types list is not guaranteed to remain the same for the same source program between different runs of the compiler, making it difficult to test inter-type references. This patch updates the assembler comments output when writing a given BTF record to include minimal information about the referenced type, if any. This allows for the regular expressions used in the gcc testsuite to do some basic integrity checks on inter-type references. For example, for the type unsigned int * Assembly comments like the following are written with -dA: .4byte 0 ; TYPE 2 BTF_KIND_PTR '' .4byte 0x2000000 ; btt_info: kind=2, kflag=0, vlen=0 .4byte 0x1 ; btt_type: (BTF_KIND_INT 'unsigned int') Several BTF tests which can immediately be made more robust with this change are updated. It will also be useful in new tests for the upcoming btf_type_tag support. gcc/ * btfout.cc (btf_kind_names): New. (btf_kind_name): New. (btf_absolute_var_id): New utility function. (btf_relative_var_id): Likewise. (btf_relative_func_id): Likewise. (btf_absolute_datasec_id): Likewise. (btf_asm_type_ref): New. (btf_asm_type): Update asm comments and use btf_asm_type_ref (). (btf_asm_array): Likewise. Accept ctf_container_ref parameter. (btf_asm_varent): Likewise. (btf_asm_func_arg): Likewise. (btf_asm_datasec_entry): Likewise. (btf_asm_datasec_type): Likewise. (btf_asm_func_type): Likewise. Add index parameter. (btf_asm_enum_const): Likewise. (btf_asm_sou_member): Likewise. (output_btf_vars): Update btf_asm_* call accordingly. (output_asm_btf_sou_fields): Likewise. (output_asm_btf_enum_list): Likewise. (output_asm_btf_func_args_list): Likewise. (output_asm_btf_vlen_bytes): Likewise. (output_btf_func_types): Add ctf_container_ref parameter. Pass it to btf_asm_func_type. (output_btf_datasec_types): Update btf_asm_datsec_type call similarly. (btf_output): Update output_btf_func_types call similarly. gcc/testsuite/ * gcc.dg/debug/btf/btf-array-1.c: Use new BTF asm comments in scan-assembler expressions where useful. * gcc.dg/debug/btf/btf-anonymous-struct-1.c: Likewise. * gcc.dg/debug/btf/btf-anonymous-union-1.c: Likewise. * gcc.dg/debug/btf/btf-bitfields-2.c: Likewise. * gcc.dg/debug/btf/btf-bitfields-3.c: Likewise. * gcc.dg/debug/btf/btf-datasec-2.c: Likewise. * gcc.dg/debug/btf/btf-enum-1.c: Likewise. * gcc.dg/debug/btf/btf-function-6.c: Likewise. * gcc.dg/debug/btf/btf-pointers-1.c: Likewise. * gcc.dg/debug/btf/btf-struct-1.c: Likewise. * gcc.dg/debug/btf/btf-struct-2.c: Likewise. * gcc.dg/debug/btf/btf-typedef-1.c: Likewise. * gcc.dg/debug/btf/btf-union-1.c: Likewise. * gcc.dg/debug/btf/btf-variables-1.c: Likewise. * gcc.dg/debug/btf/btf-variables-2.c: Likewise. Update outdated comment. * gcc.dg/debug/btf/btf-function-3.c: Update outdated comment.
2023-05-31btf: be clear when record size/type is not usedDavid Faust1-0/+6
All BTF type records have a 4-byte field used to encode a size or link to another type, depending on the type kind. But BTF_KIND_ARRAY and BTF_KIND_FWD do not use this field at all, and should write zero. GCC already correctly writes zero in this field for these type kinds, but the process is not straightforward and results in the -dA comment claiming the field is a reference to another type. This patch makes the behavior explicit and updates the assembler comment to state clearly that the field is unused. gcc/ * btfout.cc (btf_asm_type): Add dedicated cases for BTF_KIND_ARRAY and BTF_KIND_FWD which do not use the size/type field at all.
2023-05-31emit-rtl: Change return type of predicate functions from int to boolUros Bizjak3-36/+32
Also fix some stalled comments. gcc/ChangeLog: * rtl.h (subreg_lowpart_p): Change return type from int to bool. (active_insn_p): Ditto. (in_sequence_p): Ditto. (unshare_all_rtl): Change return type from int to void. * emit-rtl.h (mem_expr_equal_p): Change return type from int to bool. * emit-rtl.cc (subreg_lowpart_p): Change return type from int to bool and adjust function body accordingly. (mem_expr_equal_p): Ditto. (unshare_all_rtl): Change return type from int to void and adjust function body accordingly. (verify_rtx_sharing): Remove unneeded return. (active_insn_p): Change return type from int to bool and adjust function body accordingly. (in_sequence_p): Ditto.
2023-05-31alias: Change return type of predicate functions from int to boolUros Bizjak3-135/+122
Also remove a bunch of unneeded forward declarations. gcc/ChangeLog: * rtl.h (true_dependence): Change return type from int to bool. (canon_true_dependence): Ditto. (read_dependence): Ditto. (anti_dependence): Ditto. (canon_anti_dependence): Ditto. (output_dependence): Ditto. (canon_output_dependence): Ditto. (may_alias_p): Ditto. * alias.h (alias_sets_conflict_p): Ditto. (alias_sets_must_conflict_p): Ditto. (objects_must_conflict_p): Ditto. (nonoverlapping_memrefs_p): Ditto. * alias.cc (rtx_equal_for_memref_p): Remove forward declaration. (record_set): Ditto. (base_alias_check): Ditto. (find_base_value): Ditto. (mems_in_disjoint_alias_sets_p): Ditto. (get_alias_set_entry): Ditto. (decl_for_component_ref): Ditto. (write_dependence_p): Ditto. (memory_modified_1): Ditto. (mems_in_disjoint_alias_set_p): Change return type from int to bool and adjust function body accordingly. (alias_sets_conflict_p): Ditto. (alias_sets_must_conflict_p): Ditto. (objects_must_conflict_p): Ditto. (rtx_equal_for_memref_p): Ditto. (base_alias_check): Ditto. (read_dependence): Ditto. (nonoverlapping_memrefs_p): Ditto. (true_dependence_1): Ditto. (true_dependence): Ditto. (canon_true_dependence): Ditto. (write_dependence_p): Ditto. (anti_dependence): Ditto. (canon_anti_dependence): Ditto. (output_dependence): Ditto. (canon_output_dependence): Ditto. (may_alias_p): Ditto. (init_alias_analysis): Change "changed" variable to bool.
2023-05-31RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for ↵Juzhe-Zhong10-4/+262
RVV auto-vectorization Base on V1 patch, adding comment: ;; Use define_insn_and_split to define vsext.vf2/vzext.vf2 will help combine PASS ;; to combine instructions as below: ;; vsext.vf2 + vsext.vf2 + vadd.vv ==> vwadd.vv gcc/ChangeLog: * config/riscv/autovec.md (<optab><v_double_trunc><mode>2): Change expand into define_insn_and_split. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: * gcc.target/riscv/rvv/autovec/widen/widen-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-2.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-3.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-4.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: New test.
2023-05-31RISC-V: Add testcase for vrsub.vi auto-vectorizationJuzhe-Zhong4-1/+59
Apparently, we are missing vrsub.vi tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add vsub.vi. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Ditto. Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
2023-05-31RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)Juzhe-Zhong1-3/+1
Base on the discussion here: https://github.com/riscv/riscv-v-spec/issues/884 vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching support. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-31RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening ↵Juzhe-Zhong1-3/+1
conversion) Base on the discussion here: https://github.com/riscv/riscv-v-spec/issues/884 vfwcvt.f.x<u>.v doesn't depend on FRM. So remove FRM preparing for mode switching support. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-31RISC-V: Remove FRM for vfncvt.rod instructionJuzhe-Zhong1-3/+1
Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-31aarch64: Add pattern for bswap + rotate [PR 110039]Christophe Lyon1-0/+10
After commit g:d8545fb2c71683f407bfd96706103297d4d6e27b, we missed a pattern to match the new GIMPLE form. With this patch, gcc.target/aarch64/rev16_2.c passes again. 2023-05-31 Christophe Lyon <christophe.lyon@linaro.org> PR target/110039 gcc/ * config/aarch64/aarch64.md (aarch64_rev16si2_alt3): New pattern.
2023-05-31libstdc++: Do not include <exception> in <mutex>Jonathan Wakely2-5/+8
We previously needed <exception> in <mutex> for the std::lock_error exception class, but that was moved out of <mutex> in 2009 when it was removed from the C++0x draft. We can stop including <exception> now. Move the include for <bits/error_constants.h> to <bits/unique_lock.h> where it's actually used, and only include <errno.h> in <mutex> (for EAGAIN and EDEADLK). Also add some headers to <mutex> that are needed but are not included directly: <bits/functexcept.h>, <bits/invoke.h> and <bits/move.h>. libstdc++-v3/ChangeLog: * include/bits/unique_lock.h: Include <bits/error_constants.h> here for std::errc constants. * include/std/mutex: Do not include <bits/error_constants.h> and <exception> here.
2023-05-31libstdc++: Replace obsolete shell syntax in configure.acJonathan Wakely2-2/+2
The current POSIX standard says that the -a and -o operators to the 'test' utility are obsolete, and the shell operators && and || should be used instead. libstdc++-v3/ChangeLog: * configure.ac: Replace use of -o operator for test. * configure: Regenerate.
2023-05-31libstdc++: Add missing noexcept to std::scoped_allocator_adaptorJonathan Wakely2-19/+73
The standard requires these constructors and accessors to be noexcept. libstdc++-v3/ChangeLog: * include/std/scoped_allocator (scoped_allocator_adaptor): Add noexcept to all constructors except the default constructor. (scoped_allocator_adaptor::inner_allocator): Add noexcept. (scoped_allocator_adaptor::outer_allocator): Likewise. * testsuite/20_util/scoped_allocator/noexcept.cc: New test.
2023-05-31libstdc++: Add std::numeric_limits<__float128> specialization [PR104772]Jonathan Wakely2-0/+87
As suggested by Jakub in the PR, this just hardcodes the constants with a Q suffix, since the properties of __float128 are not going to change. We can only define it for non-strict modes because the suffix gives an error otherwise, even in system headers: limits:2085: error: unable to find numeric literal operator 'operator""Q' libstdc++-v3/ChangeLog: PR libstdc++/104772 * include/std/limits (numeric_limits<__float128>): Define. * testsuite/18_support/numeric_limits/128bit.cc: New test.
2023-05-31libstdc++: Disable embedded tzdata for all 16-bit targetsJonathan Wakely2-12/+21
libstdc++-v3/ChangeLog: * acinclude.m4 (GLIBCXX_ZONEINFO_DIR): Extend logic for avr and msp430 to all 16-bit targets. * configure: Regenerate.
2023-05-31libstdc++: Fix preprocessor conditions for std::from_chars [PR109921]Jonathan Wakely1-7/+13
We use the from_chars_strtod function with __strtof128 to read a _Float128 value, but from_chars_strtod is not defined unless uselocale is available. This can lead to compilation failures for some targets, because we try to define the _Flaot128 overload in terms of a non-existing from_chars_strtod function. Only try to use __strtof128 if uselocale is available, otherwise fallback to the long double overload of std::from_chars (which might fallback to the double overload, which should use fast_float). This ensures we always define the full set of overloads, even if they are not always accurate for all values of the wider types. libstdc++-v3/ChangeLog: PR libstdc++/109921 * src/c++17/floating_from_chars.cc (USE_STRTOF128_FOR_FROM_CHARS): Only define when USE_STRTOD_FOR_FROM_CHARS is also defined. (USE_STRTOD_FOR_FROM_CHARS): Do not undefine when long double is binary64. (from_chars(const char*, const char*, double&, chars_format)): Check __LDBL_MANT_DIG__ == __DBL_MANT_DIG__ here. (from_chars(const char*, const char*, _Float128&, chars_format)) Only use from_chars_strtod when USE_STRTOD_FOR_FROM_CHARS is defined, otherwise parse a long double and convert to _Float128.
2023-05-31libstdc++: Deprecate std::setfill for std::basic_istream [PR109922]Jonathan Wakely11-10/+24
Prior to N0966 (July 1996) the std::setfill manipulator was specified to work with both input and output streams. In the final C++98 standard it is only specified to work with output streams. We have always supported it for input streams, despite that never being in the standard, and having no meaning for any input streams defined by the standard. This commit adds a deprecated attribute to the overload for input streams, so that we can stop supporting this some day. libstdc++-v3/ChangeLog: PR libstdc++/109922 * include/std/iomanip (operator>>(basic_istream&, _Setfill)): Add deprecated attribute to non-standard overload. * doc/xml/manual/evolution.xml: Document deprecation. * doc/html/*: Regenerate. * testsuite/27_io/manipulators/standard/char/1.cc: Add dg-warning for expected deprecated warning. * testsuite/27_io/manipulators/standard/char/2.cc: Likewise. * testsuite/27_io/manipulators/standard/wchar_t/1.cc: Likewise. * testsuite/27_io/manipulators/standard/wchar_t/2.cc: Likewise.
2023-05-31ipa/109983 - (IPA) PTA speedupRichard Biener1-72/+46
This improves the edge avoidance heuristic by re-ordering the topological sort of the graph to make sure the component with the ESCAPED node is processed first. This improves the number of created edges which directly correlates with the number of bitmap_ior_into calls from 141447426 to 239596 and the compile-time from 1083s to 3s. It also improves the compile-time for the related PR109143 from 81s to 27s. I've modernized the topological sorting API on the way as well. PR ipa/109983 PR tree-optimization/109143 * tree-ssa-structalias.cc (struct topo_info): Remove. (init_topo_info): Likewise. (free_topo_info): Likewise. (compute_topo_order): Simplify API, put the component with ESCAPED last so it's processed first. (topo_visit): Adjust. (solve_graph): Likewise.
2023-05-31IPA PTA stats enhancement and non-details dump slimmingRichard Biener1-2/+8
The following keeps track of the number of edges we avoid to create because they redundandly feed ESCAPED. It also avoids printing a header for -details when not using -details. * tree-ssa-structalias.cc (constraint_stats::num_avoided_edges): New. (add_graph_edge): Count redundant edges we avoid to create. (dump_sa_stats): Dump them. (ipa_pta_execute): Do not dump generating constraints when we are not dumping them.
2023-05-31aarch64: Simplify output template emission code for a few patternsKyrylo Tkachov2-99/+40
If the output code for a define_insn just does a switch (which_alternative) with no other computation we can almost always replace it with more compact MD syntax for each alternative in a mult-alternative '@' block. This patch cleans up some such patterns in the aarch64 backend, making them shorter and more concise. No behavioural change intended. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>): Rewrite output template to avoid explicit switch on which_alternative. (*aarch64_simd_mov<VQMOV:mode>): Likewise. (and<mode>3): Likewise. (ior<mode>3): Likewise. * config/aarch64/aarch64.md (*mov<mode>_aarch64): Likewise.
2023-05-31xtensa: Improve "*shlrd_reg" insn pattern and its variantTakayuki 'January June' Suwa2-26/+58
The insn "*shlrd_reg" shifts two registers with a funnel shifter by the third register to get a single word result: reg0 = (reg1 SHIFT_OP0 reg3) BIT_JOIN_OP (reg2 SHIFT_OP1 (32 - reg3)) where the funnel left shift is SHIFT_OP0 := ASHIFT, SHIFT_OP1 := LSHIFTRT and its right shift is SHIFT_OP0 := LSHIFTRT, SHIFT_OP1 := ASHIFT, respectively. And also, BIT_JOIN_OP can be either PLUS or IOR in either shift direction. [(set (match_operand:SI 0 "register_operand" "=a") (match_operator:SI 6 "xtensa_bit_join_operator" [(match_operator:SI 4 "logical_shift_operator" [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 3 "register_operand" "r")]) (match_operator:SI 5 "logical_shift_operator" [(match_operand:SI 2 "register_operand" "r") (neg:SI (match_dup 3))])]))] Although the RTL matching template can express it as above, there is no way of direcing that the operator (operands[6]) that combines the two individual shifts is commutative. Thus, if multiple insn sequences matching the above pattern appear adjacently, the combiner may accidentally mix them up and get partial results. This patch adds a new insn-and-split pattern with the two sides swapped representation of the bit-combining operation that was lacking and described above. And also changes the other "*shlrd" variants from previously describing the arbitraryness of bit-combining operations with code iterators to a combination of the match_operator and the predicate above. gcc/ChangeLog: * config/xtensa/predicates.md (xtensa_bit_join_operator): New predicate. * config/xtensa/xtensa.md (ior_op): Remove. (*shlrd_reg): Rename from "*shlrd_reg_<code>", and add the insn_and_split pattern of the same name to express and capture the bit-combining operation with both sides swapped. In addition, replace use of code iterator with new operator predicate. (*shlrd_const, *shlrd_per_byte): Likewise regarding the code iterator.
2023-05-31Fix ICE in rewrite_expr_tree_parallelCui, Lili3-1/+15
1. Limit the value of tree-reassoc-width to IntegerRange(0, 256). 2. Add width limit in rewrite_expr_tree_parallel. gcc/ChangeLog: PR tree-optimization/110038 * params.opt: Add a limit on tree-reassoc-width. * tree-ssa-reassoc.cc (rewrite_expr_tree_parallel): Add width limit. gcc/testsuite/ChangeLog: PR tree-optimization/110038 * gcc.dg/pr110038.c: New test.
2023-05-31RISC-V: Add ZVFH extension to the -march= optionPan Li4-0/+66
This patch would like to add new sub extension (aka ZVFH) to the -march= option. To make it simple, only the sub extension itself is involved in this patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFH. The Zvfh extension depends on the Zve32f and Zfhmin extensions. You can locate more information about ZVFH from below spec doc. https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#185-zvfh-vector-extension-for-half-precision-floating-point Signed-off-by: Pan Li <pan2.li@intel.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfh item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZVFH): New macro. (TARGET_ZVFH): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-21.c: New test. * gcc.target/riscv/predef-27.c: New test.
2023-05-31RISC-V: Fix unreachable test code for init repeat sequence.Pan Li1-1/+0
This patch fix one unreachable test code, which is for debugging purpose without cleanup before commit. Signed-off-by: Pan Li <pan2.li@intel.com> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Remove debug code. Signed-off-by: Pan Li <pan2.li@intel.com>
2023-05-31Daily bump.GCC Administrator8-1/+587
2023-05-31Enhance NARROW FLOAT_EXPR vectorization by truncating integer to lower ↵liuhongt4-32/+121
precision. Similar like WIDEN FLOAT_EXPR, when direct_optab is not existed, try intermediate integer type whenever gimple ranger can tell it's safe. .i.e. When there's no direct optab for vector long long -> vector float, but the value range of integer can be represented as int, try vector int -> vector float if availble. gcc/ChangeLog: PR tree-optimization/108804 * tree-vect-patterns.cc (vect_get_range_info): Remove static. * tree-vect-stmts.cc (vect_create_vectorized_demotion_stmts): Add new parameter narrow_src_p. (vectorizable_conversion): Enhance NARROW FLOAT_EXPR vectorization by truncating to lower precision. * tree-vectorizer.h (vect_get_range_info): New declare. gcc/testsuite/ChangeLog: * gcc.target/i386/pr108804.c: New test.
2023-05-30testsuite: add verify-sarif-file to some testcases that were missing itDavid Malcolm2-0/+3
gcc/testsuite/ChangeLog: * gcc.dg/analyzer/malloc-sarif-1.c: Add missing verify-sarif-file directive. * gcc.dg/analyzer/sarif-pr107366.c: Likewise. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-05-30[libstdc++] [testsuite] xfail double-prec from_chars for x86_64 ldblAlexandre Oliva2-2/+2
When long double is wider than double, but from_chars is implemented in terms of double, tests that involve the full precision of long double are expected to fail. Mark them as such on x86_64-*-vxworks*. for libstdc++-v3/ChangeLog * testsuite/20_util/from_chars/4.cc: Skip long double test06 on x86_64-vxworks. * testsuite/20_util/to_chars/long_double.cc: Xfail run on x86_64-vxworks.
2023-05-30testsuite/52641: Fix more of implicit int=32 assumption fallout.Georg-Johann Lay7-3/+13
gcc/testsuite/ PR testsuite/52641 * gcc.dg/torture/pr107451.c: Require int32plus. * gcc.dg/torture/pr108574-3.c: Use __INT32_TYPE__ instead of int. * gcc.dg/torture/pr109940.c: Use __INTPTR_TYPE__ instead of long. * gcc.dg/torture/pr95248.c: Require size24plus. * gcc.dg/torture/pr95295-3.c: Use var_* with at least 32 bits int. * gcc.dg/torture/pr98640.c: Cast to __INT32_TYPE__ instead of int. * gcc.dg/tree-ssa/pr103771.c: Use int with at least 32 bits.
2023-05-30LRA: Update insn sp offset if its input reload changes SPVladimir N. Makarov3-4/+36
The patch fixes a bug when there is input reload changing SP. The bug was triggered by switching H8300 target to LRA. The insn in question is (insn 21 20 22 2 (set (mem/f:SI (pre_dec:SI (reg/f:SI 7 sp)) [3 S4 A32]) (reg/f:SI 31)) "j.c":10:3 19 {*movsi} (expr_list:REG_DEAD (reg/f:SI 31) (expr_list:REG_ARGS_SIZE (const_int 4 [0x4]) (nil)))) The memory address is reloaded but the SP offset for the original insn was not updated. gcc/ChangeLog: * lra-int.h (lra_update_sp_offset): Add the prototype. * lra.cc (setup_sp_offset): Change the return type. Use lra_update_sp_offset. * lra-eliminations.cc (lra_update_sp_offset): New function. (lra_process_new_insns): Push the current insn to reprocess if the input reload changes sp offset.
2023-05-30i386: Fix misleading identation in i386-expand.cc [PR110041]Uros Bizjak1-12/+12
gcc/ChangeLog: PR target/110041 * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Fix misleading identation.
2023-05-30jump: Change return type of predicate functions from int to boolUros Bizjak2-107/+107
gcc/ChangeLog: * rtl.h (comparison_dominates_p): Change return type from int to bool. (condjump_p): Ditto. (any_condjump_p): Ditto. (any_uncondjump_p): Ditto. (simplejump_p): Ditto. (returnjump_p): Ditto. (eh_returnjump_p): Ditto. (onlyjump_p): Ditto. (invert_jump_1): Ditto. (invert_jump): Ditto. (rtx_renumbered_equal_p): Ditto. (redirect_jump_1): Ditto. (redirect_jump): Ditto. (condjump_in_parallel_p): Ditto. * jump.cc (invert_exp_1): Adjust forward declaration. (comparison_dominates_p): Change return type from int to bool and adjust function body accordingly. (simplejump_p): Ditto. (condjump_p): Ditto. (condjump_in_parallel_p): Ditto. (any_uncondjump_p): Ditto. (any_condjump_p): Ditto. (returnjump_p): Ditto. (eh_returnjump_p): Ditto. (onlyjump_p): Ditto. (redirect_jump_1): Ditto. (redirect_jump): Ditto. (invert_exp_1): Ditto. (invert_jump_1): Ditto. (invert_jump): Ditto. (rtx_renumbered_equal_p): Ditto.
2023-05-30MAINTAINERS: Add myself to write after approvalJeevitha1-0/+1
2023-05-30 Jeevitha Palanisamy <jeevitha@linux.ibm.com> ChangeLog: * MAINTAINERS (Write After Approval): Add myself.
2023-05-30testsuite: make mve_intrinsic_type_overloads-int.c libc-agnosticChristophe Lyon1-13/+15
Glibc defines int32_t as 'int' while newlib defines it as 'long int'. Although these correspond to the same size, g++ complains when using the 'wrong' version: invalid conversion from 'long int*' to 'int32_t*' {aka 'int*'} [-fpermissive] or invalid conversion from 'int*' to 'int32_t*' {aka 'long int*'} [-fpermissive] when calling vst1q(int32*, int32x4_t) with a first parameter of type 'long int *' (resp. 'int *') To make this test pass with any type of toolchain, this patch defines 'word_type' according to which libc is in use. 2023-05-23 Christophe Lyon <christophe.lyon@linaro.org> gcc/testsuite/ * gcc.target/arm/mve/intrinsics/mve_intrinsic_type_overloads-int.c: Support both definitions of int32_t.
2023-05-30Add a != MIN/MAX_VALUE_CST ? CST-+1 : a to minmax_from_comparisonAndrew Pinski3-2/+40
This patch adds the support for match that was implemented for PR 87913 in phiopt. It implements it by adding support to minmax_from_comparison for the check. It uses the range information if available which allows to produce MIN/MAX expression when comparing against the lower/upper bound of the range instead of lower/upper of the type. minmax-20.c is the new testcase which tests the ranges part. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: * fold-const.cc (minmax_from_comparison): Add support for NE_EXPR. * match.pd ((cond (cmp (convert1? x) c1) (convert2? x) c2) pattern): Add ne as a possible cmp. ((a CMP b) ? minmax<a, c> : minmax<b, c> pattern): Likewise. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/minmax-22.c: New test.
2023-05-30MATCH: Move `a <= CST1 ? MAX<a, CST2> : a` optimization to matchAndrew Pinski5-2/+68
This moves the `a <= CST1 ? MAX<a, CST2> : a` optimization from phiopt to match. It just adds a new pattern to match.pd. There is one more change needed before being able to remove minmax_replacement from phiopt. A few notes on the testsuite changes: * phi-opt-5.c is now able to optimize at phiopt1 so remove the xfail. * pr66726-4.c can be optimized during fold before phiopt1 so need to change the scanning. * pr66726-5.c needs two phiopt passes currently to optimize to the right thing, it needed 2 phiopt passes before, the cast from int to unsigned char is the reason. * pr66726-6.c is what the original pr66726-4.c was testing before the fold was able to optimize it. OK? Bootstrapped and tested on x86_64-linux-gnu. gcc/ChangeLog: * match.pd (`(a CMP CST1) ? max<a,CST2> : a`): New pattern. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/phi-opt-5.c: Remove last xfail. * gcc.dg/tree-ssa/pr66726-4.c: Change how scanning works. * gcc.dg/tree-ssa/pr66726-5.c: New test. * gcc.dg/tree-ssa/pr66726-6.c: New test.
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