aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2024-06-19RISC-V: Add testcases for unsigned .SAT_ADD vector form 7Pan Li9-0/+395
After the middle-end support the form 7 of unsigned SAT_ADD and the RISC-V backend implement the .SAT_ADD for vector mode, add more test case to cover the form 7. Form 7: #define DEF_VEC_SAT_U_ADD_FMT_7(T) \ void __attribute__((noinline)) \ vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = (T)(x + y) < x ? -1 : (x + y); \ } \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper macro for testing. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_ADD vector form 6Pan Li9-0/+395
After the middle-end support the form 6 of unsigned SAT_ADD and the RISC-V backend implement the .SAT_ADD for vector mode, add more test case to cover the form 6. Form 6: #define DEF_VEC_SAT_U_ADD_FMT_6(T) \ void __attribute__((noinline)) \ vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x <= (T)(x + y) ? (x + y) : -1; \ } \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper macro for testing. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_ADD vector form 5Pan Li9-0/+396
After the middle-end support the form 5 of unsigned SAT_ADD and the RISC-V backend implement the .SAT_ADD for vector mode, add more test case to cover the form 5. Form 5: #define DEF_VEC_SAT_U_ADD_FMT_5(T) \ void __attribute__((noinline)) \ vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \ } \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper macro for testing. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_ADD vector form 4Pan Li9-0/+396
After the middle-end support the form 4 of unsigned SAT_ADD and the RISC-V backend implement the .SAT_ADD for vector mode, add more test case to cover the form 4. Form 4: #define DEF_VEC_SAT_U_ADD_FMT_4(T) \ void __attribute__((noinline)) \ vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret; \ } \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper macro for testing. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_ADD vector form 3Pan Li9-0/+397
After the middle-end support the form 3 of unsigned SAT_ADD and the RISC-V backend implement the .SAT_ADD for vector mode, add more test case to cover the form 3. Form 3: #define DEF_VEC_SAT_U_ADD_FMT_3(T) \ void __attribute__((noinline)) \ vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ T overflow = __builtin_add_overflow (x, y, &ret); \ out[i] = (T)(-overflow) | ret; \ } \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper macro for testing. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_ADD vector form 2Pan Li9-0/+395
After the middle-end support the form 2 of unsigned SAT_ADD and the RISC-V backend implement the .SAT_ADD for vector mode, add more test case to cover the form 2. Form 2: #define DEF_VEC_SAT_U_ADD_FMT_2(T) \ void __attribute__((noinline)) \ vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = (T)(x + y) >= x ? (x + y) : -1; \ } \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper macro for testing. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12Pan Li9-0/+182
After the middle-end support the form 12 of unsigned SAT_SUB and the RISC-V backend implement the SAT_SUB for vector mode, add more test case to cover the form 12. Form 12: #define DEF_SAT_U_SUB_FMT_12(T) \ T __attribute__((noinline)) \ sat_u_sub_##T##_fmt_12 (T x, T y) \ { \ T ret; \ bool overflow = __builtin_sub_overflow (x, y, &ret); \ return !overflow ? ret : 0; \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for testing. * gcc.target/riscv/sat_u_sub-45.c: New test. * gcc.target/riscv/sat_u_sub-46.c: New test. * gcc.target/riscv/sat_u_sub-47.c: New test. * gcc.target/riscv/sat_u_sub-48.c: New test. * gcc.target/riscv/sat_u_sub-run-45.c: New test. * gcc.target/riscv/sat_u_sub-run-46.c: New test. * gcc.target/riscv/sat_u_sub-run-47.c: New test. * gcc.target/riscv/sat_u_sub-run-48.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11Pan Li9-0/+183
After the middle-end support the form 11 of unsigned SAT_SUB and the RISC-V backend implement the SAT_SUB for vector mode, add more test case to cover the form 11. Form 11: #define DEF_SAT_U_SUB_FMT_11(T) \ T __attribute__((noinline)) \ sat_u_sub_##T##_fmt_11 (T x, T y) \ { \ T ret; \ bool overflow = __builtin_sub_overflow (x, y, &ret); \ return overflow ? 0 : ret; \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for testing. * gcc.target/riscv/sat_u_sub-41.c: New test. * gcc.target/riscv/sat_u_sub-42.c: New test. * gcc.target/riscv/sat_u_sub-43.c: New test. * gcc.target/riscv/sat_u_sub-44.c: New test. * gcc.target/riscv/sat_u_sub-run-41.c: New test. * gcc.target/riscv/sat_u_sub-run-42.c: New test. * gcc.target/riscv/sat_u_sub-run-43.c: New test. * gcc.target/riscv/sat_u_sub-run-44.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19[MAINTAINERS] Update my email address and move to DCO.Ramana Radhakrishnan1-1/+2
Signed-off-by: Ramana Radhakrishnan <ramanara@nvidia.com> * MAINTAINERS: Update my email address.
2024-06-19Daily bump.GCC Administrator8-1/+698
2024-06-18RISC-V: Move mode assertion out of conditional branch in emit_insnEdwin Lu1-6/+19
When emitting insns, we have an early assertion to ensure the input operand's mode and the expanded operand's mode are the same; however, it does not perform this check if the pattern does not have an explicit machine mode specifying the operand. In this scenario, it will always assume that mode = Pmode to correctly satisfy the maybe_legitimize_operand check, however, there may be problems when working in 32 bit environments. Make the assert unconditional and replace it with an internal error for more descriptive logging gcc/ChangeLog: * config/riscv/riscv-v.cc: Move assert out of conditional block Signed-off-by: Edwin Lu <ewlu@rivosinc.com> Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>
2024-06-18RISC-V: Fix vwsll combine on rv32 targetsEdwin Lu1-4/+2
On rv32 targets, vwsll_zext1_scalar_<mode> would trigger an ice in maybe_legitimize_instruction when zero extending a uint32 to uint64 due to a mismatch between the input operand's mode (DI) and the expanded insn operand's mode (Pmode == SI). Ensure that mode of the operands match gcc/ChangeLog: * config/riscv/autovec-opt.md: Fix mode mismatch Signed-off-by: Edwin Lu <ewlu@rivosinc.com> Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>
2024-06-18[committed] [RISC-V] Fix wrong patch applicationJeff Law1-1/+1
Applied the wrong patch which didn't have the final testsuite adjustment to skip -Os on the new test. Fixed thusly. Pushed to the trunk. gcc/testsuite * gcc.target/riscv/zbs-ext-2.c: Do not run for -Os.
2024-06-18aarch64: Add comment about thunderxt81/t83 being aliasesAndrew Pinski1-0/+1
Since these were already aliases just make it clear on that. gcc/ChangeLog: * config/aarch64/aarch64-cores.def: Add comment saying thunderxt81/t83 are aliases of octeontx81/83. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-06-18aarch64: make thunderxt88p1 an alias of thunderxt88Andrew Pinski2-4/+3
Since r7-6575-g71aba51d6460ff, thunderxt88 has been the same as thunderxt88p1 so let's make them a true alias and remove the odd variant handling and moves it below thunderxt88. Bootstrapped and tested on aarch64-linux-gnu with no regressions. gcc/ChangeLog: * config/aarch64/aarch64-cores.def (thunderxt88p1): Make an alias of thunderxt88 and move below thunderxt88. * config/aarch64/aarch64-tune.md: Regenerate. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-06-18diagnostics: rename tree-diagnostic-path.cc to diagnostic-path.ccDavid Malcolm4-7/+6
Now that nothing in tree-diagnostic-path.cc uses "tree", this patch renames it to diagnostic-path.cc and moves it from OBJS to OBJS-libcommon. No functional change intended. gcc/ChangeLog: * Makefile.in (OBJS): Move selftest-diagnostic-path.o, selftest-logical-location.o, and tree-diagnostic-path.o to... (OBJS-libcommon): ...here, renaming tree-diagnostic-path.o to diagnostic-path.o. * tree-diagnostic-path.cc: Rename to... * diagnostic-path.cc: ...this. Drop include of "tree.h". (tree_diagnostic_path_cc_tests): Rename to... (diagnostic_path_cc_tests): ...this. * selftest-run-tests.cc (selftest::run_tests): Update for above renaming. * selftest.h (tree_diagnostic_path_cc_tests): Rename decl to... (diagnostic_path_cc_tests): ...this. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-06-18diagnostics: eliminate diagnostic_context::m_print_path callbackDavid Malcolm7-23/+19
No functional change intended. gcc/ChangeLog: * diagnostic-format-json.cc (diagnostic_output_format_init_json): Replace clearing of diagnostic_context::m_print_path callback with setting the path format to DPF_NONE. * diagnostic-format-sarif.cc (diagnostic_output_format_init_sarif): Likewise. * diagnostic.cc (diagnostic_context::show_any_path): Replace call to diagnostic_context::m_print_path callback with a direct call to diagnostic_context::print_path. * diagnostic.h (diagnostic_context::print_path): New decl. (diagnostic_context::m_print_path): Delete callback. * tree-diagnostic-path.cc (default_tree_diagnostic_path_printer): Convert to... (diagnostic_context::print_path): ...this. * tree-diagnostic.cc (tree_diagnostics_defaults): Delete initialization of m_print_path. * tree-diagnostic.h (default_tree_diagnostic_path_printer): Delete decl. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-06-18diagnostics: introduce diagnostic-macro-unwinding.h/ccDavid Malcolm7-202/+253
Eliminate a dependency on "tree" from the code used by diagnostic_path handling. No functional change intended. gcc/ChangeLog: * Makefile.in (OBJS): Add diagnostic-macro-unwinding.o. gcc/c-family/ChangeLog: * c-opts.cc: Replace include of "tree-diagnostic.h" with "diagnostic-macro-unwinding.h". gcc/ChangeLog: * diagnostic-macro-unwinding.cc: New file, with material taken from tree-diagnostic.cc. * diagnostic-macro-unwinding.h: New file, with material taken from tree-diagnostic.h. * tree-diagnostic-path.cc: Repalce include of "tree-diagnostic.h" with "diagnostic-macro-unwinding.h". * tree-diagnostic.cc (struct loc_map_pair): Move to diagnostic-macro-unwinding.cc. (maybe_unwind_expanded_macro_loc): Likewise. (virt_loc_aware_diagnostic_finalizer): Likewise. * tree-diagnostic.h (virt_loc_aware_diagnostic_finalizer): Move decl to diagnostic-macro-unwinding.h. (maybe_unwind_expanded_macro_loc): Likewise. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-06-18diagnostics: eliminate diagnostic_context::m_make_json_for_pathDavid Malcolm5-40/+34
Now that the path-handling code for json_output_format no longer needs "tree", and thus can be in OBJS-libcommon we can move it from tree-diagnostic-path.cc to diagnostic-format-json.cc where it should have been all along. No functional change intended. gcc/ChangeLog: * diagnostic-format-json.cc: Include "diagnostic-path.h" and "logical-location.h". (make_json_for_path): Move tree-diagnostic-path.cc's default_tree_make_json_for_path here, renaming it and making it static. (json_output_format::on_end_diagnostic): Replace call of m_context's m_make_json_for_path callback with a direct call to make_json_for_path. * diagnostic.h (diagnostic_context::m_make_json_for_path): Drop field. * tree-diagnostic-path.cc: Drop include of "json.h". (default_tree_make_json_for_path): Rename to make_json_for_path and move to diagnostic-format-json.cc. * tree-diagnostic.cc (tree_diagnostics_defaults): Drop initialization of m_make_json_for_path. * tree-diagnostic.h (default_tree_make_json_for): Delete decl. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-06-18diagnostics: remove tree usage from tree-diagnostic-path.ccDavid Malcolm7-113/+580
No functional change intended. gcc/ChangeLog: * Makefile.in (OBJS): Add selftest-diagnostic-path.o and selftest-logical-location.o. * logical-location.h: Include "label-text.h". (class logical_location): Update leading comment. * selftest-diagnostic-path.cc: New file, adapted from simple-diagnostic-path.cc and from material in tree-diagnostic-path.cc. * selftest-diagnostic-path.h: New file, adapted from simple-diagnostic-path.h and from material in tree-diagnostic-path.cc. * selftest-logical-location.cc: New file. * selftest-logical-location.h: New file. * tree-diagnostic-path.cc: Remove includes of "tree-pretty-print.h", "langhooks.h", and "simple-diagnostic-path.h". Add include of "selftest-diagnostic-path.h". (class test_diagnostic_path): Delete, in favor of new implementation in selftest-diagnostic-path.{h,cc}, which is directly derived from diagnostic_path, rather than from simple_diagnostic_path. (selftest::test_intraprocedural_path): Eliminate tree usage, via change to test_diagnostic_path, using strings rather than function_decls for identifying functions in the test. (selftest::test_interprocedural_path_1): Likewise. (selftest::test_interprocedural_path_2): Likewise. (selftest::test_recursion): Likewise. (selftest::test_control_flow_1): Likewise. (selftest::test_control_flow_2): Likewise. (selftest::test_control_flow_3): Likewise. (selftest::assert_cfg_edge_path_streq): Likewise. (selftest::test_control_flow_5): Likewise. (selftest::test_control_flow_6): Likewise. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-06-18diagnostics: eliminate "tree" from diagnostic_{event,path}David Malcolm11-70/+161
This patch eliminates the use of "tree" from diagnostic_{event,path} in favor of const logical_location *. No functional change intended. gcc/analyzer/ChangeLog: * checker-event.h (checker_event::fndecl): Drop "final" and "override", converting from a vfunc implementation to a plain accessor. * checker-path.cc (checker_path::same_function_p): New. * checker-path.h (checker_path::same_function_p): New decl. gcc/ChangeLog: * diagnostic.cc: Include "logical-location.h". (diagnostic_path::get_first_event_in_a_function): Fix typo in leading comment. Rewrite to use logical_location rather than tree. Drop test on stack depth. (diagnostic_path::interprocedural_p): Rewrite to use logical_location rather than tree. (logical_location::function_p): New. * diagnostic-path.h (diagnostic_event::get_fndecl): Eliminate vfunc. (diagnostic_path::same_function_p): New pure virtual func. * logical-location.h (logical_location::get_name_for_path_output): New pure virtual func. * simple-diagnostic-path.cc (simple_diagnostic_path::same_function_p): New. (simple_diagnostic_event::simple_diagnostic_event): Initialize m_logical_loc. * simple-diagnostic-path.h: Include "tree-logical-location.h". (simple_diagnostic_event::get_fndecl): Convert from a vfunc implementation to an accessor. (simple_diagnostic_event::get_logical_location): Use m_logical_loc. (simple_diagnostic_event::m_logical_loc): New field. (simple_diagnostic_path::same_function_p): New decl. * tree-diagnostic-path.cc: Move pragma disabling -Wformat-diag to cover the whole file. (can_consolidate_events): Add params "path", "ev1_idx", and "ev2_idx". Rewrite to use diagnostic_path::same_function_p rather than tree. (per_thread_summary::per_thread_summary): Add "path" param (per_thread_summary::m_path): New field. (event_range::event_range): Update for conversion of m_fndecl to m_logical_loc. (event_range::maybe_add_event): Rename param "idx" to "new_ev_idx". Update call to can_consolidate_events to pass in "m_path", "m_start_idx", and "new_ev_idx". (event_range::m_fndecl): Replace with... (event_range::m_logical_loc): ...this. (path_summary::get_or_create_events_for_thread_id): Pass "path" to per_thread_summary ctor. (per_thread_summary::interprocedural_p): Rewrite to use diagnostic_path::same_function_p rather than tree. (print_fndecl): Delete. (thread_event_printer::print_swimlane_for_event_range): Update for conversion from tree to logical_location. (default_tree_diagnostic_path_printer): Likewise. (default_tree_make_json_for_path): Likewise. * tree-logical-location.cc: Include "intl.h". (compiler_logical_location::get_name_for_tree_for_path_output): New. (tree_logical_location::get_name_for_path_output): New. (current_fndecl_logical_location::get_name_for_path_output): New. * tree-logical-location.h (compiler_logical_location::get_name_for_tree_for_path_output): New decl. (tree_logical_location::get_name_for_path_output): New decl. (current_fndecl_logical_location::get_name_for_path_output): New decl. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-06-18diagnostics: move simple_diagnostic_{path,thread,event} to their own .h/ccDavid Malcolm10-251/+366
As work towards eliminating the dependency on "tree" from path-printing, move these classes to a new simple-diagnostic-path.h/cc. No functional change intended. gcc/analyzer/ChangeLog: * checker-path.h: Include "simple-diagnostic-path.h". gcc/ChangeLog: * Makefile.in (OBJS): Add simple-diagnostic-path.o. * diagnostic-path.h (class simple_diagnostic_event): Move to simple-diagnostic-path.h. (class simple_diagnostic_thread): Likewise. (class simple_diagnostic_path): Likewise. * diagnostic.cc (simple_diagnostic_path::simple_diagnostic_path): Move to simple-diagnostic-path.cc. (simple_diagnostic_path::num_events): Likewise. (simple_diagnostic_path::get_event): Likewise. (simple_diagnostic_path::num_threads): Likewise. (simple_diagnostic_path::get_thread): Likewise. (simple_diagnostic_path::add_thread): Likewise. (simple_diagnostic_path::add_event): Likewise. (simple_diagnostic_path::add_thread_event): Likewise. (simple_diagnostic_path::connect_to_next_event): Likewise. (simple_diagnostic_event::simple_diagnostic_event): Likewise. (simple_diagnostic_event::~simple_diagnostic_event): Likewise. * selftest-run-tests.cc (selftest::run_tests): Call selftest::simple_diagnostic_path_cc_tests. * selftest.h (selftest::simple_diagnostic_path_cc_tests): New decl. * simple-diagnostic-path.cc: New file, from the above material. * simple-diagnostic-path.h: New file, from the above material from diagnostic-path.h. * tree-diagnostic-path.cc: Include "simple-diagnostic-path.h". gcc/testsuite/ChangeLog * gcc.dg/plugin/diagnostic_plugin_test_paths.c: Include "simple-diagnostic-path.h". Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2024-06-18Match: Support forms 7 and 8 for the unsigned .SAT_ADDPan Li1-0/+10
When investigate the vectorization of .SAT_ADD, we notice there are additional 2 forms, aka form 7 and 8 for .SAT_ADD. Form 7: #define DEF_SAT_U_ADD_FMT_7(T) \ T __attribute__((noinline)) \ sat_u_add_##T##_fmt_7 (T x, T y) \ { \ return x > (T)(x + y) ? -1 : (x + y); \ } Form 8: #define DEF_SAT_U_ADD_FMT_8(T) \ T __attribute__((noinline)) \ sat_u_add_##T##_fmt_8 (T x, T y) \ { \ return x <= (T)(x + y) ? (x + y) : -1; \ } Thus, add above 2 forms to the match gimple_unsigned_integer_sat_add, and then the vectorizer can try to recog the pattern like form 7 and form 8. The below test suites are passed for this patch: 1. The rv64gcv fully regression test with newlib. 2. The rv64gcv build with glibc. 3. The x86 bootstrap test. 4. The x86 fully regression test. gcc/ChangeLog: * match.pd: Add form 7 and 8 for the unsigned .SAT_ADD match. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-18Match: Support form 11 for the unsigned scalar .SAT_SUBPan Li1-1/+8
We missed one match pattern for the unsigned scalar .SAT_SUB, aka form 11. Form 11: #define SAT_SUB_U_11(T) \ T sat_sub_u_11_##T (T x, T y) \ { \ T ret; \ bool overflow = __builtin_sub_overflow (x, y, &ret); \ return overflow ? 0 : ret; \ } Thus, add above form 11 to the match pattern gimple_unsigned_integer_sat_sub. The below test suites are passed for this patch: 1. The rv64gcv fully regression test with newlib. 2. The rv64gcv build with glibc. 3. The x86 bootstrap test. 4. The x86 fully regression test. gcc/ChangeLog: * match.pd: Add form 11 match pattern for .SAT_SUB. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-18tree-optimization/115537 - ICE with SLP condition reduction vectorizationRichard Biener2-2/+22
The condition rejecting "multiple-type" SLP condition reduction lacks handling EXTRACT_LAST reductions. PR tree-optimization/115537 * tree-vect-loop.cc (vectorizable_reduction): Also reject SLP condition reductions of EXTRACT_LAST kind when multiple statement copies are involved. * gcc.dg/vect/pr115537.c: New testcase.
2024-06-18[to-be-committed,RISC-V] Improve bset generation when bit position is limitedJeff Law2-0/+60
So more work in the ongoing effort to make better use of the Zbs extension. This time we're trying to exploit knowledge of the shift count/bit position to allow us to use a bset instruction. Consider this expression in SImode (1 << (pos & 0xf) None of the resulting values will have bit 31 set. So if there's an explicit zero or sign extension to DI we can drop that explicit extension and generate a simple bset with x0 as the input value. Or another example (which I think came from spec at some point and IIRC was the primary motivation for this patch): (1 << (7-(pos) % 8)) Before this change they'd generate something like this respectively: li a5,1 andi a0,a0,15 sllw a0,a5,a0 li a5,7 andn a0,a5,a0 li a5,1 sllw a0,a5,a0 After this change they generate: andi a0,a0,15 # 9 [c=4 l=4] *anddi3/1 bset a0,x0,a0 # 17 [c=8 l=4] *bsetdi_2 li a5,7 # 27 [c=4 l=4] *movdi_64bit/1 andn a0,a5,a0 # 28 [c=4 l=4] and_notdi3 bset a0,x0,a0 # 19 [c=8 l=4] *bsetdi_2 We achieve this with simple define_splits which target the bsetdi_2 pattern I recently added. Much better than the original implementation I did a few months back :-) I've got a bclr/binv variant from a few months back as well, but it needs to be updated to the simpler implementation found here. Just ran this through my tester. Will wait for the precommit CI to render its verdict before moving forward. gcc/ * config/riscv/bitmanip.md (bset splitters): New patterns for generating bset when bit position is limited.
2024-06-18libstdc++: Fix outdated comment about standard integer typesJonathan Wakely1-4/+2
The long long and unsigned long long types have been standard since C++11, so are not extensions. There are also the char8_t, char16_t and char32_t types. Just refer to the standard integer types, without saying how many there are. libstdc++-v3/ChangeLog: * include/bits/cpp_type_traits.h: Fix outdated comment about the number of standard integer types.
2024-06-18analyzer: Fix g++ 4.8 bootstrap without using std::move to return ↵Jonathan Wakely12-33/+33
std::unique_ptr Revert the changes in r15-1111-ge22b7f741ab54f and fix bootstrap with GCC 4.8 a different way. The original problem is not related to C++17 guaranteed copy elision, it's related to Core DR 1579 [1], which was part of C++14 but only implemented in G++ as a C++11 DR with r5-1576-gfb682f9458c6cf (so GCC 4.8 doesn't implement it). The original fix causes -Wredundant-move warnings with GCC trunk. [1] https://cplusplus.github.io/CWG/issues/1579.html gcc/analyzer/ChangeLog * constraint-manager.cc (equiv_class::make_dump_widget): Change return type to match return value and do not use std::move on return value. (bounded_ranges_constraint::make_dump_widget): Likewise. (constraint_manager::make_dump_widget): Likewise. * constraint-manager.h (equiv_class::make_dump_widget): Change return type. (bounded_ranges_constraint::make_dump_widget): Likewise. (constraint_manager::make_dump_widget): Likewise. * program-state.cc (sm_state_map::make_dump_widget): Likewise. (program_state::make_dump_widget): Likewise. * program-state.h (sm_state_map::make_dump_widget): Likewise. (program_state::make_dump_widget): Likewise. * region-model.cc (region_to_value_map::make_dump_widget): Likewise. (region_model::make_dump_widget): Likewise. * region-model.h (region_to_value_map::make_dump_widget): Likewise. (region_model::make_dump_widget): Likewise. * region.cc (region::make_dump_widget): Likewise. * region.h (region::make_dump_widget): Likewise. * store.cc (binding_cluster::make_dump_widget): Likewise. (store::make_dump_widget): Likewise. * store.h (binding_cluster::make_dump_widget): Likewise. (store::make_dump_widget): Likewise. * svalue.cc (svalue::make_dump_widget): Likewise. * svalue.h (svalue::make_dump_widget): Likewise.
2024-06-18[MAINTAINERS] Update my email addressKyrylo Tkachov1-2/+2
Pushing to trunk. * MAINTAINERS (aarch64 port): Update my email address. (DCO section): Likewise. Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>
2024-06-18aarch64: Add some uses of force_highpart_subregRichard Sandiford1-13/+4
This patch adds uses of force_highpart_subreg to places that already use force_lowpart_subreg. gcc/ * config/aarch64/aarch64.cc (aarch64_addti_scratch_regs): Use force_highpart_subreg instead of gen_highpart and simplify_gen_subreg. (aarch64_subvti_scratch_regs): Likewise.
2024-06-18Add force_highpart_subregRichard Sandiford4-14/+20
This patch adds a force_highpart_subreg to go along with the recently added force_lowpart_subreg. gcc/ * explow.h (force_highpart_subreg): Declare. * explow.cc (force_highpart_subreg): New function. * builtins.cc (expand_builtin_issignaling): Use it. * expmed.cc (emit_store_flag_1): Likewise.
2024-06-18Make more use of force_lowpart_subregRichard Sandiford3-14/+12
This patch makes target-independent code use force_lowpart_subreg instead of simplify_gen_subreg and lowpart_subreg in some places. The criteria were: (1) The code is obviously specific to expand (where new pseudos can be created), or at least would be invalid to call when !can_create_pseudo_p () and temporaries are needed. (2) The value is obviously an rvalue rather than an lvalue. Doing this should reduce the likelihood of bugs like PR115464 occuring in other situations. gcc/ * builtins.cc (expand_builtin_issignaling): Use force_lowpart_subreg instead of simplify_gen_subreg and lowpart_subreg. * expr.cc (convert_mode_scalar, expand_expr_real_2): Likewise. * optabs.cc (expand_doubleword_mod): Likewise.
2024-06-18aarch64: Add some uses of force_lowpart_subregRichard Sandiford5-17/+23
This patch makes more use of force_lowpart_subreg, similarly to the recent patch for force_subreg. The criteria were: (1) The code is obviously specific to expand (where new pseudos can be created). (2) The value is obviously an rvalue rather than an lvalue. gcc/ PR target/115464 * config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin) (aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of simplify_gen_subreg and lowpart_subreg. * config/aarch64/aarch64-sve-builtins-base.cc (svset_neonq_impl::expand): Likewise. * config/aarch64/aarch64-sve-builtins-sme.cc (add_load_store_slice_operand): Likewise. * config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise. (aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise. gcc/testsuite/ PR target/115464 * gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.
2024-06-18Add force_lowpart_subregRichard Sandiford3-22/+17
optabs had a local function called lowpart_subreg_maybe_copy that is very similar to the lowpart version of force_subreg. This patch adds a force_lowpart_subreg wrapper around force_subreg and uses it in optabs.cc. The only difference between the old and new functions is that the old one asserted success while the new one doesn't. It's common not to assert elsewhere when taking subregs; normally a null result is enough. Later patches will make more use of the new function. gcc/ * explow.h (force_lowpart_subreg): Declare. * explow.cc (force_lowpart_subreg): New function. * optabs.cc (lowpart_subreg_maybe_copy): Delete. (expand_absneg_bit): Use force_lowpart_subreg instead of lowpart_subreg_maybe_copy. (expand_copysign_bit): Likewise.
2024-06-18Make more use of force_subregRichard Sandiford2-29/+20
This patch makes target-independent code use force_subreg instead of simplify_gen_subreg in some places. The criteria were: (1) The code is obviously specific to expand (where new pseudos can be created), or at least would be invalid to call when !can_create_pseudo_p () and temporaries are needed. (2) The value is obviously an rvalue rather than an lvalue. (3) The offset wasn't a simple lowpart or highpart calculation; a later patch will deal with those. Doing this should reduce the likelihood of bugs like PR115464 occuring in other situations. gcc/ * expmed.cc (store_bit_field_using_insv): Use force_subreg instead of simplify_gen_subreg. (store_bit_field_1): Likewise. (extract_bit_field_as_subreg): Likewise. (extract_integral_bit_field): Likewise. (emit_store_flag_1): Likewise. * expr.cc (convert_move): Likewise. (convert_modes): Likewise. (emit_group_load_1): Likewise. (emit_group_store): Likewise. (expand_assignment): Likewise.
2024-06-18aarch64: Use force_subreg in more placesRichard Sandiford4-12/+10
This patch makes the aarch64 code use force_subreg instead of simplify_gen_subreg in more places. The criteria were: (1) The code is obviously specific to expand (where new pseudos can be created). (2) The value is obviously an rvalue rather than an lvalue. (3) The offset wasn't a simple lowpart or highpart calculation; a later patch will deal with those. gcc/ * config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin): Use force_subreg instead of simplify_gen_subreg. * config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (svget_impl::expand): Likewise. (svget_neonq_impl::expand): Likewise. * config/aarch64/aarch64-sve-builtins-functions.h (multireg_permute::expand): Likewise.
2024-06-18Make force_subreg emit nothing on failureRichard Sandiford1-1/+5
While adding more uses of force_subreg, I realised that it should be more careful to emit no instructions on failure. This kind of failure should be very rare, so I don't think it's a case worth optimising for. gcc/ * explow.cc (force_subreg): Emit no instructions on failure.
2024-06-18c23: Fix for redeclared enumerator initialized with different type [PR115109]Martin Uecker4-3/+95
c23 specifies that the type of a redeclared enumerator is the one of the previous declaration. Convert initializers with different type accordingly and emit an error when the value does not fit. 2024-06-01 Martin Uecker <uecker@tugraz.at> PR c/115109 gcc/c/ * c-decl.cc (build_enumerator): When redeclaring an enumerator convert value to previous type. For redeclared enumerators use underlying type for computing the next value. gcc/testsuite/ * gcc.dg/pr115109.c: New test. * gcc.dg/c23-tag-enum-6.c: New test. * gcc.dg/c23-tag-enum-7.c: New test.
2024-06-18rs6000: Shrink rs6000_init_generated_builtins size [PR115324]Jakub Jelinek2-12/+29
While my r15-1001-g4cf2de9b5268224 PCH PIE power fix change decreased the .data section sizes (219792 -> 189336), it increased the size of already huge rs6000_init_generated_builtins generated function, from 218328 to 228668 bytes. That is because there are thousands of array references to global arrays and we keep constructing the addresses of the arrays again and again. Ideally some optimization would figure out we have a single function which has 461 rs6000_overload_info 1257 rs6000_builtin_info_fntype 1768 rs6000_builtin_decls 2548 rs6000_instance_info_fntype array references and that maybe it might be a good idea to just preload the addresses of those arrays into some register if it decreases code size and doesn't slow things down. The function actually is called just once and is huge, so code size is even more important than speed, which is dominated by all the GC allocations anyway. Until that is done, here is a slightly cleaner version of the hack, which makes the function noipa (so that LTO doesn't undo it) for GCC 8.1+ and passes the 4 arrays as arguments to the function from the caller. This decreases the function size from 228668 bytes to 207572 bytes. 2024-06-18 Jakub Jelinek <jakub@redhat.com> PR target/115324 * config/rs6000/rs6000-gen-builtins.cc (write_decls): Change declaration of rs6000_init_generated_builtins from no arguments to 4 pointer arguments. (write_init_bif_table): Change rs6000_builtin_info_fntype to builtin_info_fntype and rs6000_builtin_decls to builtin_decls. (write_init_ovld_table): Change rs6000_instance_info_fntype to instance_info_fntype, rs6000_builtin_decls to builtin_decls and rs6000_overload_info to overload_info. (write_init_file): Add __noipa__ attribute to rs6000_init_generated_builtins for GCC 8.1+ and change the function from no arguments to 4 pointer arguments. Change rs6000_builtin_decls to builtin_decls. * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Adjust rs6000_init_generated_builtins caller.
2024-06-18tree-optimization/115493 - fix wrong code with SLP induction cond reductionRichard Biener1-2/+2
The following fixes a bad final value being used when doing single-lane SLP integer induction cond reduction vectorization. PR tree-optimization/115493 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the first scalar result.
2024-06-18Enhance if-conversion for automatic arraysRichard Biener6-10/+44
Automatic arrays that are not address-taken should not be subject to store data races. This applies to OMP SIMD in-branch lowered functions result array which for the testcase otherwise prevents vectorization with SSE and for AVX and AVX512 ends up with spurious .MASK_STORE to the stack surviving. This inefficiency was noted in PR111793. I've introduced ref_can_have_store_data_races, commonizing uses of flag_store_data_races in if-conversion, cselim and store motion. PR tree-optimization/111793 * tree-ssa-alias.h (ref_can_have_store_data_races): Declare. * tree-ssa-alias.cc (ref_can_have_store_data_races): New function. * tree-if-conv.cc (ifcvt_memrefs_wont_trap): Use ref_can_have_store_data_races to allow more unconditional stores. * tree-ssa-loop-im.cc (execute_sm): Likewise. * tree-ssa-phiopt.cc (cond_store_replacement): Likewise. * gcc.dg/vect/vect-simd-clone-21.c: New testcase.
2024-06-17testsuite, rs6000: Replace powerpc_altivec_ok with powerpc_altivec [PR114842]Kewen Lin220-242/+247
As noted in PR114842, most of the test cases which require effective target check powerpc_altivec_ok actually care about if ALTIVEC feature is enabled, and they should adopt effective target powerpc_altivec instead. Otherwise, when users are specifying extra option -mno-altivec in RUNTESTFLAGS, the check powerpc_altivec_ok returns true then the test case would be tested without ALTIVEC so it would fail. With commit r15-716, dg-options and dg-additional-options can be taken into account when evaluating powerpc_altivec, so this patch also moves dg-{additional,}-options lines before dg-require-effective-target to make it effective. PR testsuite/114842 gcc/testsuite/ChangeLog: * c-c++-common/pr72747-1.c: Replace powerpc_altivec_ok with powerpc_altivec, move dg-options and dg-additional-options lines before dg-require-effective-target lines when it doesn't cause any side effect like note message. * c-c++-common/pr72747-2.c: Likewise. * g++.dg/torture/pr79905.C: Likewise. * g++.target/powerpc/altivec-1.C: Likewise. * g++.target/powerpc/altivec-10.C: Likewise. * g++.target/powerpc/altivec-11.C: Likewise. * g++.target/powerpc/altivec-12.C: Likewise. * g++.target/powerpc/altivec-13.C: Likewise. * g++.target/powerpc/altivec-14.C: Likewise. * g++.target/powerpc/altivec-15.C: Likewise. * g++.target/powerpc/altivec-16.C: Likewise. * g++.target/powerpc/altivec-17.C: Likewise. * g++.target/powerpc/altivec-18.C: Likewise. * g++.target/powerpc/altivec-2.C: Likewise. * g++.target/powerpc/altivec-4.C: Likewise. * g++.target/powerpc/altivec-5.C: Likewise. * g++.target/powerpc/altivec-6.C: Likewise. * g++.target/powerpc/altivec-7.C: Likewise. * g++.target/powerpc/altivec-8.C: Likewise. * g++.target/powerpc/altivec-9.C: Likewise. * g++.target/powerpc/altivec-cell-1.C: Likewise. * g++.target/powerpc/altivec-cell-5.C: Likewise. * g++.target/powerpc/altivec-types-1.C: Likewise. * g++.target/powerpc/altivec-types-2.C: Likewise. * g++.target/powerpc/altivec-types-3.C: Likewise. * g++.target/powerpc/altivec-types-4.C: Likewise. * gcc.target/powerpc/altivec-1-runnable.c: Likewise. * gcc.target/powerpc/altivec-11.c: Likewise. * gcc.target/powerpc/altivec-13.c: Likewise. * gcc.target/powerpc/altivec-14.c: Likewise. * gcc.target/powerpc/altivec-15.c: Likewise. * gcc.target/powerpc/altivec-16.c: Likewise. * gcc.target/powerpc/altivec-17.c: Likewise. * gcc.target/powerpc/altivec-18.c: Likewise. * gcc.target/powerpc/altivec-19.c: Likewise. * gcc.target/powerpc/altivec-2.c: Likewise. * gcc.target/powerpc/altivec-21.c: Likewise. * gcc.target/powerpc/altivec-22.c: Likewise. * gcc.target/powerpc/altivec-23.c: Likewise. * gcc.target/powerpc/altivec-25.c: Likewise. * gcc.target/powerpc/altivec-26.c: Likewise. * gcc.target/powerpc/altivec-27.c: Likewise. * gcc.target/powerpc/altivec-28.c: Likewise. * gcc.target/powerpc/altivec-29.c: Likewise. * gcc.target/powerpc/altivec-30.c: Likewise. * gcc.target/powerpc/altivec-31.c: Likewise. * gcc.target/powerpc/altivec-32.c: Likewise. * gcc.target/powerpc/altivec-33.c: Likewise. * gcc.target/powerpc/altivec-34.c: Likewise. * gcc.target/powerpc/altivec-35.c: Likewise. * gcc.target/powerpc/altivec-36.c: Likewise. * gcc.target/powerpc/altivec-4.c: Likewise. * gcc.target/powerpc/altivec-5.c: Likewise. * gcc.target/powerpc/altivec-6.c: Likewise. * gcc.target/powerpc/altivec-7.c: Likewise. * gcc.target/powerpc/altivec-8.c: Likewise. * gcc.target/powerpc/altivec-9.c: Likewise. * gcc.target/powerpc/altivec-cell-1.c: Likewise. * gcc.target/powerpc/altivec-cell-5.c: Likewise. * gcc.target/powerpc/altivec-cell-6.c: Likewise. * gcc.target/powerpc/altivec-cell-7.c: Likewise. * gcc.target/powerpc/altivec-perm-1.c: Likewise. * gcc.target/powerpc/altivec-perm-2.c: Likewise. * gcc.target/powerpc/altivec-perm-3.c: Likewise. * gcc.target/powerpc/altivec-perm-4.c: Likewise. * gcc.target/powerpc/altivec-pr22085.c: Likewise. * gcc.target/powerpc/altivec-splat.c: Likewise. * gcc.target/powerpc/altivec-types-1.c: Likewise. * gcc.target/powerpc/altivec-types-2.c: Likewise. * gcc.target/powerpc/altivec-types-3.c: Likewise. * gcc.target/powerpc/altivec-types-4.c: Likewise. * gcc.target/powerpc/altivec-volatile.c: Likewise. * gcc.target/powerpc/altivec_vld_vst_addr-1.c: Likewise. * gcc.target/powerpc/bool2-av.c: Likewise. * gcc.target/powerpc/bool2-p5.c: Likewise. * gcc.target/powerpc/bool3-av.c: Likewise. * gcc.target/powerpc/builtin-vec-sums-be-int.c: Likewise. * gcc.target/powerpc/builtins-3.c: Likewise. * gcc.target/powerpc/cell_builtin-3.c: Likewise. * gcc.target/powerpc/cell_builtin-5.c: Likewise. * gcc.target/powerpc/cell_builtin-6.c: Likewise. * gcc.target/powerpc/cell_builtin-7.c: Likewise. * gcc.target/powerpc/cell_builtin-8.c: Likewise. * gcc.target/powerpc/fold-vec-abs-char-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-abs-char.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int.p7.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-abs-short.c: Likewise. * gcc.target/powerpc/fold-vec-add-1.c: Likewise. * gcc.target/powerpc/fold-vec-add-2.c: Likewise. * gcc.target/powerpc/fold-vec-add-3.c: Likewise. * gcc.target/powerpc/fold-vec-add-5.c: Likewise. * gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise. * gcc.target/powerpc/fold-vec-ld-char.c: Likewise. * gcc.target/powerpc/fold-vec-ld-float.c: Likewise. * gcc.target/powerpc/fold-vec-ld-int.c: Likewise. * gcc.target/powerpc/fold-vec-ld-short.c: Likewise. * gcc.target/powerpc/fold-vec-madd-short.c: Likewise. * gcc.target/powerpc/fold-vec-mergehl-char.c: Likewise. * gcc.target/powerpc/fold-vec-mergehl-float.c: Likewise. * gcc.target/powerpc/fold-vec-mergehl-int.c: Likewise. * gcc.target/powerpc/fold-vec-mergehl-short.c: Likewise. * gcc.target/powerpc/fold-vec-minmax-char.c: Likewise. * gcc.target/powerpc/fold-vec-minmax-int.c: Likewise. * gcc.target/powerpc/fold-vec-minmax-short.c: Likewise. * gcc.target/powerpc/fold-vec-missing-lhs.c: Likewise. * gcc.target/powerpc/fold-vec-msum-char.c: Likewise. * gcc.target/powerpc/fold-vec-msum-short.c: Likewise. * gcc.target/powerpc/fold-vec-mule-char.c: Likewise. * gcc.target/powerpc/fold-vec-mule-short.c: Likewise. * gcc.target/powerpc/fold-vec-mult-char.c: Likewise. * gcc.target/powerpc/fold-vec-mult-short.c: Likewise. * gcc.target/powerpc/fold-vec-pack-int.c: Likewise. * gcc.target/powerpc/fold-vec-pack-short.c: Likewise. * gcc.target/powerpc/fold-vec-perm-char.c: Likewise. * gcc.target/powerpc/fold-vec-perm-float.c: Likewise. * gcc.target/powerpc/fold-vec-perm-int.c: Likewise. * gcc.target/powerpc/fold-vec-perm-pixel.c: Likewise. * gcc.target/powerpc/fold-vec-perm-short.c: Likewise. * gcc.target/powerpc/fold-vec-shift-char.c: Likewise. * gcc.target/powerpc/fold-vec-shift-int.c: Likewise. * gcc.target/powerpc/fold-vec-shift-left-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-shift-left.c: Likewise. * gcc.target/powerpc/fold-vec-shift-short.c: Likewise. * gcc.target/powerpc/fold-vec-splat-32.c: Likewise. * gcc.target/powerpc/fold-vec-splat-8.c: Likewise. * gcc.target/powerpc/fold-vec-splat-char.c: Likewise. * gcc.target/powerpc/fold-vec-splat-int.c: Likewise. * gcc.target/powerpc/fold-vec-splat-short.c: Likewise. * gcc.target/powerpc/fold-vec-splats-char.c: Likewise. * gcc.target/powerpc/fold-vec-splats-int.c: Likewise. * gcc.target/powerpc/fold-vec-splats-short.c: Likewise. * gcc.target/powerpc/fold-vec-st-char.c: Likewise. * gcc.target/powerpc/fold-vec-st-float.c: Likewise. * gcc.target/powerpc/fold-vec-st-int.c: Likewise. * gcc.target/powerpc/fold-vec-st-short.c: Likewise. * gcc.target/powerpc/fold-vec-sub-char.c: Likewise. * gcc.target/powerpc/fold-vec-sub-float.c: Likewise. * gcc.target/powerpc/fold-vec-sub-int.c: Likewise. * gcc.target/powerpc/fold-vec-sub-short.c: Likewise. * gcc.target/powerpc/fold-vec-sums-int.c: Likewise. * gcc.target/powerpc/fold-vec-unpack-char.c: Likewise. * gcc.target/powerpc/fold-vec-unpack-pixel.c: Likewise. * gcc.target/powerpc/fold-vec-unpack-short.c: Likewise. * gcc.target/powerpc/ppc-fma-3.c: Likewise. * gcc.target/powerpc/ppc-fma-4.c: Likewise. * gcc.target/powerpc/ppc-fma-7.c: Likewise. * gcc.target/powerpc/ppc-vector-memcpy.c: Likewise. * gcc.target/powerpc/ppc-vector-memset.c: Likewise. * gcc.target/powerpc/pr100645.c: Likewise. * gcc.target/powerpc/pr101384-1.c: Likewise. * gcc.target/powerpc/pr101384-2.c: Likewise. * gcc.target/powerpc/pr103353.c: Likewise. * gcc.target/powerpc/pr103702.c: Likewise. * gcc.target/powerpc/pr108348-1.c: Likewise. * gcc.target/powerpc/pr108348-2.c: Likewise. * gcc.target/powerpc/pr109932-1.c: Likewise. * gcc.target/powerpc/pr109932-2.c: Likewise. * gcc.target/powerpc/pr110776.c: Likewise. * gcc.target/powerpc/pr16155.c: Likewise. * gcc.target/powerpc/pr16286.c: Likewise. * gcc.target/powerpc/pr27158.c: Likewise. * gcc.target/powerpc/pr37168.c: Likewise. * gcc.target/powerpc/pr47197.c: Likewise. * gcc.target/powerpc/pr67071-1.c: Likewise. * gcc.target/powerpc/pr67071-2.c: Likewise. * gcc.target/powerpc/pr67071-3.c: Likewise. * gcc.target/powerpc/pr70010-2.c: Likewise. * gcc.target/powerpc/pr70010-3.c: Likewise. * gcc.target/powerpc/pr71297.c: Likewise. * gcc.target/powerpc/pr82112.c: Likewise. * gcc.target/powerpc/pr84220-sld.c: Likewise. * gcc.target/powerpc/pr84878.c: Likewise. * gcc.target/powerpc/pr86731-fwrapv.c: Likewise. * gcc.target/powerpc/pr86731.c: Likewise. * gcc.target/powerpc/pr88100.c: Likewise. * gcc.target/powerpc/pragma_power6.c: Likewise. * gcc.target/powerpc/pragma_power7.c: Likewise. * gcc.target/powerpc/pragma_power9.c: Likewise. * gcc.target/powerpc/swaps-p8-21.c: Likewise. * gcc.target/powerpc/unpack-vectorize-1.c: Likewise. * gcc.target/powerpc/vec-cg.c: Likewise. * gcc.target/powerpc/vec-cmpne.c: Likewise. * gcc.target/powerpc/vec-constvolatile.c: Likewise. * gcc.target/powerpc/vec-mult-char-2.c: Likewise. * gcc.target/powerpc/vec-rotate-1.c: Likewise. * gcc.target/powerpc/vec-rotate-3.c: Likewise. * gcc.target/powerpc/vec-shift.c: Likewise. * g++.target/powerpc/altivec-3.C: Likewise. * g++.target/powerpc/altivec-cell-2.C: Likewise. * g++.target/powerpc/altivec-cell-3.C: Likewise. * g++.target/powerpc/altivec-cell-4.C: Likewise. * g++.target/powerpc/const2.C: Likewise. * gcc.dg/debug/dwarf2/const-2.c: Likewise. * gcc.dg/dfp/altivec-types.c: Likewise. * gcc.dg/ubsan/pr88234.c: Likewise. * gcc.dg/vect/vect-82_64.c: Likewise. * gcc.dg/vect/vect-83_64.c: Likewise. * gcc.target/powerpc/altivec-1.c: Likewise. * gcc.target/powerpc/altivec-10.c: Likewise. * gcc.target/powerpc/altivec-12.c: Likewise. * gcc.target/powerpc/altivec-20.c: Likewise. * gcc.target/powerpc/altivec-24.c: Likewise. * gcc.target/powerpc/altivec-3.c: Likewise. * gcc.target/powerpc/altivec-cell-2.c: Likewise. * gcc.target/powerpc/altivec-cell-3.c: Likewise. * gcc.target/powerpc/altivec-cell-4.c: Likewise. * gcc.target/powerpc/altivec-consts.c: Likewise. * gcc.target/powerpc/altivec-macros.c: Likewise. * gcc.target/powerpc/altivec-varargs-1.c: Likewise. * gcc.target/powerpc/altivec-vec-merge.c: Likewise. * gcc.target/powerpc/darwin-save-world-1.c: Likewise. * gcc.target/powerpc/le-altivec-consts.c: Likewise. * gcc.target/powerpc/pr35907.c: Likewise. * gcc.target/powerpc/vec-mult-char-1.c: Likewise.
2024-06-18i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avxHu, Lin110-78/+236
gcc/ChangeLog: * config/i386/avxintrin.h: Move cmp[p|s][s|d] to [e|x]mmintrin.h, and move macros to xmmintrin.h * config/i386/emmintrin.h: Add cmp[p|s]s intrins. * config/i386/i386-builtin.def: Modify __builtin_ia32_cmp[p|s][s|d]. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Raise error when imm is in range of [8, 32] without avx. * config/i386/predicates.md (cmpps_imm_operand): New predicate. * config/i386/sse.md (avx_cmp<mode>3): Modefy define_insn. (avx_vmcmp<mode>3): Ditto. * config/i386/xmmintrin.h (_CMP_EQ_OQ): New macro for sse/sse2. (_CMP_LT_OS): Ditto (_CMP_LE_OS): Ditto (_CMP_UNORD_Q): Ditto (_CMP_NEQ_UQ): Ditto (_CMP_NLT_US): Ditto (_CMP_NLE_US): Ditto (_CMP_ORD_Q): Ditto (_mm_cmp_ps): Move intrin from avxintrin.h to xmmintrin.h (_mm_cmp_ss): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/sse-cmp-1.c: New test. * gcc.target/i386/sse-cmp-2.c: Ditto. * gcc.target/i386/sse-cmp-error.c: Ditto.
2024-06-18Daily bump.GCC Administrator7-1/+410
2024-06-17aarch64: Add testcase for PR97405Andrew Pinski1-0/+13
This aarch64 sve specific code was fixed by r15-917-gc9842f99042454 which added a riscv specific testcase so adding an aarch64 one to test the fix does not regress is a good idea. Committed as obvious after testing the testcase for aarch64-linux-gnu. PR tree-optimization/97405 gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/pr97405-1.c: New test. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-06-17[to-be-committed,RISC-V] Handle zero_extract destination for single bit ↵Jeff Law2-0/+44
insertions Combine will use zero_extract destinations for certain bitfield insertions. If the bitfield is a single bit constant, then we can use bset/bclr. In this case we are only dealing with word_mode objects, so we don't have to worry about the SI->DI extension issues for TARGET_64BIT. The testcase was derived from 502.gcc in spec from the RAU team. An earlier version of this (TARGET_64BIT only) went through Ventana's CI system. This version has gone though mine after generalizing it to handle rv32 as well. I'll wait for pre-commit CI to render its verdict before moving forward. gcc/ * config/riscv/bitmanip.md (bsetclr_zero_extract): New pattern. gcc/testsuite/ * gcc.target/riscv/zbs-zext-3.c: New test.
2024-06-17Add minimal support for __bf16 to -fdump-ada-specEric Botcazou1-1/+22
gcc/c-family/ * c-ada-spec.cc (is_float16): New predicate. (dump_ada_node) <REAL_TYPE>: Call it.
2024-06-17diagnostics: Fix add_misspelling_candidates [PR115440]Jakub Jelinek2-2/+12
The option_map array for most entries contains just non-NULL opt0 { "-Wno-", NULL, "-W", false, true }, { "-fno-", NULL, "-f", false, true }, { "-gno-", NULL, "-g", false, true }, { "-mno-", NULL, "-m", false, true }, { "--debug=", NULL, "-g", false, false }, { "--machine-", NULL, "-m", true, false }, { "--machine-no-", NULL, "-m", false, true }, { "--machine=", NULL, "-m", false, false }, { "--machine=no-", NULL, "-m", false, true }, { "--machine", "", "-m", false, false }, { "--machine", "no-", "-m", false, true }, { "--optimize=", NULL, "-O", false, false }, { "--std=", NULL, "-std=", false, false }, { "--std", "", "-std=", false, false }, { "--warn-", NULL, "-W", true, false }, { "--warn-no-", NULL, "-W", false, true }, { "--", NULL, "-f", true, false }, { "--no-", NULL, "-f", false, true } and so add_misspelling_candidates works correctly for it, but 3 out of these, { "--machine", "", "-m", false, false }, { "--machine", "no-", "-m", false, true }, and { "--std", "", "-std=", false, false }, use non-NULL opt1. That says that --machine foo should map to -mfoo and --machine no-foo should map to -mno-foo and --std c++17 should map to -std=c++17 add_misspelling_canidates was not handling this, so it hapilly registered say --stdc++17 or --machineavx512 (twice) as spelling alternatives, when those options aren't recognized. Instead we support --std c++17 or --machine avx512 --machine no-avx512 The following patch fixes that. On this particular testcase, we no longer suggest anything, even when among the suggestion is say that --std c++17 or -std=c++17 etc. 2024-06-17 Jakub Jelinek <jakub@redhat.com> PR driver/115440 * opts-common.cc (add_misspelling_candidates): If opt1 is non-NULL, add a space and opt1 to the alternative suggestion text. * g++.dg/cpp1z/pr115440.C: New test.
2024-06-17vshuf-mem.C: Make -march=z14 depend on s390_vxeAndreas Krebbel1-1/+1
gcc/testsuite/ChangeLog: * g++.dg/torture/vshuf-mem.C: Use -march=z14 only, if the we are on a machine which can actually run it.
2024-06-17c: Implement C2Y alignof on incomplete arraysJoseph Myers4-1/+23
C2Y has adopted support for alignof applied to incomplete array types (N3273). Add this support to GCC. As the relevant checks are in c-family code that doesn't have access to functions such as pedwarn_c23, this remains a hard error for older versions and isn't handled by -Wc23-c2y-compat, although preferably it would work like pedwarn_c23 (pedwarn-if-pedantic for older versions, warning with -Wc23-c2y-compat in C2Y mode). Bootstrapped with no regressions for x86_64-pc-linux-gnu. gcc/c-family/ * c-common.cc (c_sizeof_or_alignof_type): Allow alignof on an incomplete array type for C2Y. gcc/testsuite/ * gcc.dg/c23-align-10.c, gcc.dg/c2y-align-1.c, gcc.dg/c2y-align-2.c: New tests.
generated by cgit v1.1 at 2025-07-27 01:17:56 +0000