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2024-06-20ada: Couple of minor fixes in GNAT Reference ManualEric Botcazou4-31/+30
The Storage_Model pragma no longer exists. gcc/ada/ * doc/gnat_rm/gnat_language_extensions.rst (Pragma Storage_Model): Rename to Storage Model. * doc/gnat_rm/implementation_defined_aspects.rst: Alphabetize. * gnat_rm.texi: Regenerate. * gnat_ugn.texi: Regenerate.
2024-06-20ada: Add Dump_Buffers hooks for code coverageRonan Desplanques1-0/+7
The purpose of this patch is to make it possible to set up code coverage for the GNAT front end in gnat1 using GNATcoverage. It is not obvious how to have GNATcoverage instrument gnat1's main function, and since the front end has a clear entry point (Gnat1drv), we add manual instrumentation annotations there. gcc/ada/ * gnat1drv.adb (Gnat1drv): Add coverage instrumentation annotations.
2024-06-20ada: Do not compute Has_Controlled_Component twice during freezingEric Botcazou3-42/+7
The Has_Controlled_Component flag is computed twice during freezing when expansion is enabled: in Freeze_Array_Type and Expand_Freeze_Array_Type for array types, and in Freeze_Record_Type and Expand_Freeze_Record_Type for record types. This removes the latter computation in both cases, as well as moves the computation of concurrent flags from the latter to the former places, which happens to plug a loophole in the detection of errors when the No_Task_Parts aspect is specified on peculiar types. gcc/ada/ * exp_ch3.adb (Expand_Freeze_Array_Type): Do not propagate the concurrent flags and the Has_Controlled_Component flag here. (Expand_Freeze_Record_Type): Likewise. * freeze.adb (Freeze_Array_Type): Propagate the concurrent flags. (Freeze_Record_Type): Likewise. * sem_util.adb (Has_Some_Controlled_Component): Adjust comment.
2024-06-20ada: Fix minor issues in commentsEric Botcazou1-11/+10
gcc/ada/ * mutably_tagged.ads: Fix minor issues in comments throughout.
2024-06-20ada: Document -gnatd_w for CCGRichard Kenner1-1/+3
gcc/ada/ * debug.adb: Add documentation for -gnatd_w.
2024-06-20ada: Change messages for -gnatw.v to warningsViljar Indus3-23/+21
Previously this switch was emitting only info messages which was both confusing in terms of the name of the switch that was used internally and externally. gcc/ada/ * doc/gnat_ugn/building_executable_programs_with_gnat.rst: Update documentation for -gnatw.v. * sem_ch13.adb: Convert all -gnatw.v related messages to warnings. * gnat_ugn.texi: Regenerate.
2024-06-20ada: Convert -gnatw.n messages to warningsViljar Indus3-12/+14
Previously the messages produced by this warning switch were info messages that were suppressed with the same methods as regular warnings. Since info messages are now separated as a completely different class of messages then these messages should be converted back to warnings in order for the previous pragma based suppression methods to work. gcc/ada/ * doc/gnat_ugn/building_executable_programs_with_gnat.rst: Update documentation for -gnatw.n switch. * exp_util.adb: Convert info messages into warnings. * gnat_ugn.texi: Regenerate.
2024-06-20ada: Add switch for suppressing info messagesViljar Indus5-244/+297
Add a separate switch -gnatis to suppress info messages separately from warning messages that are controlled by -gnatws. gcc/ada/ * doc/gnat_ugn/building_executable_programs_with_gnat.rst: Add entry for -gnatis. * errout.adb (Error_Msg_Internal): Stop printing info messages if -gnatis was used. * opt.ads: Add Info_Suppressed flag to track whether info messages should be suppressed. * switch-c.adb: Add parsing for -gnatis. * gnat_ugn.texi: Regenerate.
2024-06-20ada: Treat Info-Warnings as Info messagesViljar Indus4-76/+96
There was a general concept of info messages being a subset of warnings. However that is no longer the case. Messages with an info insertion character should be treated just as info messages. gcc/ada/ * atree.ads: Remove Warning_Info_Messages. * errout.adb: Remove various places where Warning_Info_Messages was used. * erroutc.adb: Remove various places where Warning_Info_Messages was used. Create Error_Msg_Object objects with only an info attribute if the message contained both info and warning insertion characters. New method Has_Switch_Tag for detecting if a message should have an error tag. * errutil.adb: Create Error_Msg_Object objects with only an info attribute if the message contained both info and warning insertion characters.
2024-06-20ada: Update documentation for 'SuperJustin Squirek4-491/+497
This patch moves the documentation for 'Super from gnat language extensions to experimental language extensions. gcc/ada/ * doc/gnat_rm/gnat_language_extensions.rst: Add entry for 'Super. * doc/gnat_rm/implementation_defined_attributes.rst: Remove entry for 'Super. * gnat_rm.texi: Regenerate. * gnat_ugn.texi: Regenerate.
2024-06-20ada: Improve preprocessor error handling.Steve Baird2-2/+10
In some cases, gnatprep would correctly emit an error message and then incorrectly exit with a return code of zero, indicating success. In some cases, a correct message about an error detected by the integrated preprocessor would be accompanied by an incorrect message indicating that a source file could not be found. gcc/ada/ * gprep.adb (Process_Files.Process_One_File): When calling OS_Exit in an error path, pass in a Status parameter of 1 instead of 0 (because 0 indicates success). * lib-load.adb (Load_Main_Source): Do not emit a message about a missing source file if other error messages were generated by calling Load_Source_File; the file isn't missing - it failed preprocessing.
2024-06-20ada: Fix list of attributes defined by Ada 2022Piotr Trojanek2-12/+3
Recognize references to attributes Put_Image and Object_Size as language-defined in Ada 2022 and implementation-defined in earlier versions of Ada. Other attributes listed in Ada 2022 RM, K.2 and currently implemented in GNAT are correctly categorized. This change only affects code with restriction No_Implementation_Attributes. gcc/ada/ * sem_attr.adb (Attribute_22): Add Put_Image and Object_Size. * sem_attr.ads (Attribute_Impl_Def): Remove Object_Size.
2024-06-20i386: Fix some ISA bit test in option_overrideHongyu Wang4-8/+12
Adjust several new feature check in ix86_option_override_interal that directly use TARGET_* instead of TARGET_*_P (opts->ix86_isa_flags) to avoid cmdline option overrides target_attribute isa flag. gcc/ChangeLog: * config/i386/i386-options.cc (ix86_option_override_internal): Use TARGET_*_P (opts->x_ix86_isa_flags*) instead of TARGET_* for UINTR, LAM and APX_F. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-ccmp-2.c: Remove -mno-apxf in option. * gcc.target/i386/funcspec-56.inc: Drop uintr tests. * gcc.target/i386/funcspec-6.c: Add uintr tests.
2024-06-20Fortran: Auto array allocation with function dependencies [PR59104]Paul Thomas10-29/+238
2024-06-20 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/59104 * dependency.cc (dependency_fcn, gfc_function_dependency): New functions to detect dependency in array bounds and character lengths on old style function results. * dependency.h : Add prototype for gfc_function_dependency. * error.cc (error_print): Remove trailing space. * gfortran.h : Remove dummy_order and add fn_result_spec. * symbol.cc : Remove declaration of next_dummy_order.. (gfc_set_sym_referenced): remove setting of symbol dummy order. * trans-array.cc (gfc_trans_auto_array_allocation): Detect non-dummy symbols with function dependencies and put the allocation at the end of the initialization code. * trans-decl.cc : Include dependency.h. (decl_order): New function that determines uses the location field of the symbol 'declared_at' to determine the order of two declarations. (gfc_defer_symbol_init): Call gfc_function_dependency to put dependent symbols in the right part of the tlink chain. Use the location field of the symbol declared_at to determine the order of declarations. (gfc_trans_auto_character_variable): Put character length initialization of dependent symbols at the end of the chain. * trans.cc (gfc_add_init_cleanup): Add boolean argument with default false that determines whther an expression is placed at the back or the front of the initialization chain. * trans.h : Update the prototype for gfc_add_init_cleanup. gcc/testsuite/ PR fortran/59104 * gfortran.dg/dependent_decls_2.f90: New test.
2024-06-20tree-optimization/114413 - SLP CSE after permute optimizationRichard Biener2-12/+70
We currently fail to re-CSE SLP nodes after optimizing permutes which results in off cost estimates. For gcc.dg/vect/bb-slp-32.c this shows in not re-using the SLP node with the load and arithmetic for both the store and the reduction. The following implements CSE by re-bst-mapping nodes as finalization part of vect_optimize_slp. I've tried to make the CSE part of permute materialization but it isn't a very good fit there. I've not bothered to implement something more complete, also handling external defs or defs without SLP_TREE_SCALAR_STMTS. I realize this might result in more BB SLP which in turn might slow down code given costing for BB SLP is difficult (even that we now vectorize gcc.dg/vect/bb-slp-32.c on x86_64 might be not a good idea). This is nevertheless feeding more accurate info to costing which is good. PR tree-optimization/114413 * tree-vect-slp.cc (release_scalar_stmts_to_slp_tree_map): New function, split out from ... (vect_analyze_slp): ... here. Call it. (vect_cse_slp_nodes): New function. (vect_optimize_slp): Call it. * gcc.dg/vect/bb-slp-32.c: Expect CSE and vectorization on x86.
2024-06-20build: Fix missing variable quotes and typoCollin Funk2-8/+8
When dlopen and pthread_create are in libc the variable is set to "none required", therefore running configure will show the following errors: ./configure: line 8997: test: too many arguments ./configure: line 8999: test: too many arguments ./configure: line 9003: test: too many arguments ./configure: line 9005: test: =: unary operator expected ChangeLog: PR bootstrap/115453 * configure.ac: Quote variable result of AC_SEARCH_LIBS. Fix typo ac_cv_search_pthread_crate. * configure: Regenerate. Signed-off-by: Collin Funk <collin.funk1@gmail.com>
2024-06-20vect: Tighten an assertion for lane-reducing in transformFeng Xue1-3/+5
According to logic of code nearby the assertion, all lane-reducing operations should not appear, not just DOT_PROD_EXPR. Since "use_mask_by_cond_expr_p" treats SAD_EXPR same as DOT_PROD_EXPR, and WIDEN_SUM_EXPR should not be allowed by the following assertion "gcc_assert (commutative_binary_op_p (...))", so tighten the assertion. 2024-06-16 Feng Xue <fxue@os.amperecomputing.com> gcc/ * tree-vect-loop.cc (vect_transform_reduction): Change assertion to cover all lane-reducing ops.
2024-06-20vect: Use an array to replace 3 relevant variablesFeng Xue1-25/+18
It's better to place 3 relevant independent variables into array, since we have requirement to access them via an index in the following patch. At the same time, this change may get some duplicated code be more compact. 2024-06-16 Feng Xue <fxue@os.amperecomputing.com> gcc/ * tree-vect-loop.cc (vect_transform_reduction): Replace vec_oprnds0/1/2 with one new array variable vec_oprnds[3].
2024-06-20vect: Use one reduction_type local variableFeng Xue1-4/+4
Two local variables were defined to refer same STMT_VINFO_REDUC_TYPE, better to keep only one. 2024-06-16 Feng Xue <fxue@os.amperecomputing.com> gcc/ * tree-vect-loop.cc (vectorizable_reduction): Remove v_reduc_type, and replace it to another local variable reduction_type.
2024-06-20vect: Remove duplicated check on reduction operandFeng Xue1-4/+2
In vectorizable_reduction, one check on a reduction operand via index could be contained by another one check via pointer, so remove the former. 2024-06-16 Feng Xue <fxue@os.amperecomputing.com> gcc/ * tree-vect-loop.cc (vectorizable_reduction): Remove the duplicated check.
2024-06-20vect: Add a function to check lane-reducing stmtFeng Xue2-3/+13
Add a utility function to check if a statement is lane-reducing operation, which could simplify some existing code. 2024-06-16 Feng Xue <fxue@os.amperecomputing.com> gcc/ * tree-vectorizer.h (lane_reducing_stmt_p): New function. * tree-vect-slp.cc (vect_analyze_slp): Use new function lane_reducing_stmt_p to check statement.
2024-06-20Daily bump.GCC Administrator6-1/+474
2024-06-20Revert "build: Fix missing variable quotes"YunQiang Su4-11/+11
This reverts commit c6a9ab8c920f297c4efd289182aef9fbc73f5906.
2024-06-20Revert "Build: Fix typo ac_cv_search_pthread_crate"YunQiang Su2-2/+2
This reverts commit 8088374a868aacab4dff208ec3e3fde790a1d9a3.
2024-06-19[PATCH v2] RISC-V: Remove float vector eqne patterndemin.han3-92/+56
We can unify eqne and other comparison operations. Tested on RV32 and RV64 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond * config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove patterns (*pred_eqne<mode>_scalar_merge_tie_mask): Ditto (*pred_eqne<mode>_scalar): Ditto (*pred_eqne<mode>_scalar_narrow): Ditto gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-cmp-eqne.c: New test.
2024-06-19RISC-V: Promote Zaamo/Zalrsc to a when using an old binutilsPatrick O'Neill1-0/+1
Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify both Zaamo and Zalrsc, promote them to 'a' in the -march string. This does not affect testsuite results for users with old versions of binutils. Testcases that failed due to 'call'/isa string continue to fail after this PATCH when using an old version of binutils. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add 'a' extension to riscv_combine_info. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2024-06-19bitint: Fix up lowering of COMPLEX_EXPR [PR115544]Jakub Jelinek2-1/+20
We don't really support _Complex _BitInt(N), the only place we use bitint complex types is for the .{ADD,SUB,MUL}_OVERFLOW internal function results and COMPLEX_EXPR in the usual case should be either not present yet because the ifns weren't folded and will be lowered, or optimized into something simpler, because normally the complex bitint should be used just for extracting the 2 subparts from it. Still, with disabled optimizations it can occassionally happen that it appears in the IL and that is why there is support for lowering those, but it doesn't handle optimizing those too much, so if it uses SSA_NAME, it relies on them having a backing VAR_DECL during the lowering. This is normally achieves through the && ((is_gimple_assign (use_stmt) && (gimple_assign_rhs_code (use_stmt) != COMPLEX_EXPR)) || gimple_code (use_stmt) == GIMPLE_COND) hunk in gimple_lower_bitint, but as the following testcase shows, there is one thing I've missed, the load optimization isn't guarded by the above stuff. So, either we'd need to add support for loads to lower_complexexpr_stmt, or because they should be really rare, this patch just disables the load optimization if at least one load use is a COMPLEX_EXPR (like we do already for PHIs, calls, asm). 2024-06-19 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/115544 * gimple-lower-bitint.cc (gimple_lower_bitint): Disable optimizing loads used by COMPLEX_EXPR operands. * gcc.dg/bitint-107.c: New test.
2024-06-19i386: Zhaoxin shijidadao enablementmayshao15-14/+183
This patch enables -march/-mtune=shijidadao, costs and tunings are set according to the characteristics of the processor. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize shijidadao. * common/config/i386/i386-common.cc: Add shijidadao. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add ZHAOXIN_FAM7H_SHIJIDADAO. * config.gcc: Add shijidadao. * config/i386/driver-i386.cc (host_detect_local_cpu): Let -march=native recognize shijidadao processors. * config/i386/i386-c.cc (ix86_target_macros_internal): Add shijidadao. * config/i386/i386-options.cc (m_ZHAOXIN): Add m_SHIJIDADAO. (m_SHIJIDADAO): New definition. * config/i386/i386.h (enum processor_type): Add PROCESSOR_SHIJIDADAO. * config/i386/x86-tune-costs.h (struct processor_costs): Add shijidadao_cost. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add shijidadao. (ix86_adjust_cost): Ditto. * config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Add m_SHIJIDADAO. (X86_TUNE_USE_GATHER_4PARTS): Ditto. (X86_TUNE_USE_GATHER_8PARTS): Ditto. (X86_TUNE_AVOID_128FMA_CHAINS): Ditto. * doc/extend.texi: Add details about shijidadao. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv32.C: Handle new -march * gcc.target/i386/funcspec-56.inc: Ditto.
2024-06-19xtensa: Eliminate double MEMW insertions for volatile memoryTakayuki 'January June' Suwa1-1/+11
This patch makes avoid inserting a MEMW instruction before a load/store nstruction with volatile memory reference if there is already a MEMW immediately before it. gcc/ChangeLog: * config/xtensa/xtensa.cc (print_operand): When outputting MEMW before the instruction, check if the previous instruction is already that.
2024-06-19libstdc++: Consistently indent <future> with tabsJonathan Wakely1-164/+164
libstdc++-v3/ChangeLog: * include/std/future: Adjust whitespace to use tabs for indentation.
2024-06-19libstdc++: Add noexcept to some std::promise shared state internalsJonathan Wakely1-2/+2
Making the state ready for a std::promise<void> only needs to move a unique_ptr, which cannot throw. Make its call operator noexcept. Similarly, making the state ready by storing an exception_ptr also can't throw, so make that call operator noexcept too. libstdc++-v3/ChangeLog: * include/std/future (_State_baseV2::_Setter<R, void>): Add noexcept to call operator. (_State_baseV2::_Setter<R, __exception_ptr_tag>): Likewise.
2024-06-19libstdc++: Add conditional noexcept to std::pair default ctorJonathan Wakely1-0/+2
Most of std::pair constructors implemented using C++20 concepts have a conditional noexcept-specifier, but the default constructor doesn't. This fixes that. libstdc++-v3/ChangeLog: * include/bits/stl_pair.h [__cpp_lib_concepts] (pair()): Add conditional noexcept.
2024-06-19Fortran: fix for CHARACTER(len=*) dummies with bind(C) [PR115390]Harald Anlauf2-2/+47
gcc/fortran/ChangeLog: PR fortran/115390 * trans-decl.cc (gfc_conv_cfi_to_gfc): Move derivation of type sizes for character via gfc_trans_vla_type_sizes to after character length has been set. gcc/testsuite/ChangeLog: PR fortran/115390 * gfortran.dg/bind_c_char_11.f90: New test.
2024-06-19arm: Add support for MVE Tail-Predicated Low Overhead LoopsAndre Vieira23-82/+3321
This patch adds support for MVE Tail-Predicated Low Overhead Loops by using the doloop funcitonality added to support predicated vectorized hardware loops. gcc/ChangeLog: * config/arm/arm-protos.h (arm_target_bb_ok_for_lob): Change declaration to pass basic_block. (arm_attempt_dlstp_transform): New declaration. * config/arm/arm.cc (TARGET_LOOP_UNROLL_ADJUST): Define targethook. (TARGET_PREDICT_DOLOOP_P): Likewise. (arm_target_bb_ok_for_lob): Adapt condition. (arm_mve_get_vctp_lanes): New function. (arm_dl_usage_type): New internal enum. (arm_get_required_vpr_reg): New function. (arm_get_required_vpr_reg_param): New function. (arm_get_required_vpr_reg_ret_val): New function. (arm_mve_get_loop_vctp): New function. (arm_mve_insn_predicated_by): New function. (arm_mve_across_lane_insn_p): New function. (arm_mve_load_store_insn_p): New function. (arm_mve_impl_pred_on_outputs_p): New function. (arm_mve_impl_pred_on_inputs_p): New function. (arm_last_vect_def_insn): New function. (arm_mve_impl_predicated_p): New function. (arm_mve_check_reg_origin_is_num_elems): New function. (arm_mve_dlstp_check_inc_counter): New function. (arm_mve_dlstp_check_dec_counter): New function. (arm_mve_loop_valid_for_dlstp): New function. (arm_predict_doloop_p): New function. (arm_loop_unroll_adjust): New function. (arm_emit_mve_unpredicated_insn_to_seq): New function. (arm_attempt_dlstp_transform): New function. * config/arm/arm.opt (mdlstp): New option. * config/arm/iterators.md (dlstp_elemsize, letp_num_lanes, letp_num_lanes_neg, letp_num_lanes_minus_1): New attributes. (DLSTP, LETP): New iterators. * config/arm/mve.md (predicated_doloop_end_internal<letp_num_lanes>, dlstp<dlstp_elemsize>_insn): New insn patterns. * config/arm/thumb2.md (doloop_end): Adapt to support tail-predicated loops. (doloop_begin): Likewise. * config/arm/types.md (mve_misc): New mve type to represent predicated_loop_end insn sequences. * config/arm/unspecs.md: (DLSTP8, DLSTP16, DLSTP32, DSLTP64, LETP8, LETP16, LETP32, LETP64): New unspecs for DLSTP and LETP. gcc/testsuite/ChangeLog: * gcc.target/arm/lob.h: Add new helpers. * gcc.target/arm/lob1.c: Use new helpers. * gcc.target/arm/lob6.c: Likewise. * gcc.target/arm/mve/dlstp-compile-asm-1.c: New test. * gcc.target/arm/mve/dlstp-compile-asm-2.c: New test. * gcc.target/arm/mve/dlstp-compile-asm-3.c: New test. * gcc.target/arm/mve/dlstp-int8x16.c: New test. * gcc.target/arm/mve/dlstp-int8x16-run.c: New test. * gcc.target/arm/mve/dlstp-int16x8.c: New test. * gcc.target/arm/mve/dlstp-int16x8-run.c: New test. * gcc.target/arm/mve/dlstp-int32x4.c: New test. * gcc.target/arm/mve/dlstp-int32x4-run.c: New test. * gcc.target/arm/mve/dlstp-int64x2.c: New test. * gcc.target/arm/mve/dlstp-int64x2-run.c: New test. * gcc.target/arm/mve/dlstp-invalid-asm.c: New test. Co-authored-by: Stam Markianos-Wright <stam.markianos-wright@arm.com>
2024-06-19doloop: Add support for predicated vectorized loopsAndre Vieira3-67/+113
This patch adds support in the target agnostic doloop pass for the detection of predicated vectorized hardware loops. Arm is currently the only target that will make use of this feature. gcc/ChangeLog: * df-core.cc (df_bb_regno_only_def_find): New helper function. * df.h (df_bb_regno_only_def_find): Declare new function. * loop-doloop.cc (doloop_condition_get): Add support for detecting predicated vectorized hardware loops. (doloop_modify): Add support for GTU condition checks. (doloop_optimize): Update costing computation to support alterations to desc->niter_expr by the backend. Co-authored-by: Stam Markianos-Wright <stam.markianos-wright@arm.com>
2024-06-19Build: Fix typo ac_cv_search_pthread_crateYunQiang Su2-2/+2
The correct variable name is ac_cv_search_pthread_create ChangeLog: PR bootstrap/115453 * configure.ac: Fix typo ac_cv_search_pthread_crate. * configure: Regnerate.
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB vector form 10Pan Li9-0/+397
After the middle-end support the form 10 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 10: #define DEF_VEC_SAT_U_SUB_FMT_10(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ bool overflow = __builtin_sub_overflow (x, y, &ret); \ out[i] = !overflow ? ret : 0; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB vector form 9Pan Li9-0/+398
After the middle-end support the form 9 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 9: #define DEF_VEC_SAT_U_SUB_FMT_9(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ bool overflow = __builtin_sub_overflow (x, y, &ret); \ out[i] = overflow ? 0 : ret; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB vector form 8Pan Li9-0/+397
After the middle-end support the form 8 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 8: #define DEF_VEC_SAT_U_SUB_FMT_8(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ out[i] = ret & (T)-(!overflow); \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB vector form 7Pan Li9-0/+397
After the middle-end support the form 7 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 7: #define DEF_VEC_SAT_U_SUB_FMT_7(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ out[i] = ret & (T)(overflow - 1); \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB vector form 6Pan Li9-0/+395
After the middle-end support the form 6 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 6: #define DEF_VEC_SAT_U_SUB_FMT_6(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x <= y ? 0 : x - y; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB vector form 5Pan Li9-0/+395
After the middle-end support the form 5 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 5: #define DEF_VEC_SAT_U_SUB_FMT_5(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x < y ? 0 : x - y; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB vector form 4Pan Li9-0/+395
After the middle-end support the form 4 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 4: #define DEF_VEC_SAT_U_SUB_FMT_4(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x >= y ? x - y : 0; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19RISC-V: Add testcases for unsigned .SAT_SUB vector form 3Pan Li9-0/+396
After the middle-end support the form 3 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 3: #define DEF_VEC_SAT_U_SUB_FMT_3(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x > y ? x - y : 0; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-19libstdc++: Fix warning regressions in <bits/stl_tempbuf.h>Jonathan Wakely1-4/+4
I caused some new warnings with -Wsystem-headers with my recent changes to std::get_temporary_buffer and std::_Temporary_buffer. There's a -Wsign-compare warning which can be avoided by casting the ptrdiff_t argument to size_t (which also conveniently rejects negative values). There's also a -Wdeprecated-declarations warning because I moved where std::get_temporary_buffer is called, but didn't move the diagnostic pragmas that suppress the warning for calling it. libstdc++-v3/ChangeLog: * include/bits/stl_tempbuf.h (__get_temporary_buffer): Cast argument to size_t to handle negative values and suppress -Wsign-compare warning. (_Temporary_buffer): Move diagnostic pragmas to new location of call to std::get_temporary_buffer.
2024-06-19build: Fix missing variable quotesCollin Funk4-11/+11
When dlopen and pthread_create are in libc the variable is set to "none required", therefore running configure will show the following errors: ./configure: line 8997: test: too many arguments ./configure: line 8999: test: too many arguments ./configure: line 9003: test: too many arguments ./configure: line 9005: test: =: unary operator expected gcc/configure also has a similar problem on gcc_cv_as_mips_explicit_relocs: ./gcc/configure: line 30242: test: =: unary operator expected ChangeLog: * configure.ac: Quote variable result of AC_SEARCH_LIBS. * configure: Regenerate. gcc/ChangeLog: * configure.ac: Add missing quotation of variable gcc_cv_as_mips_explicit_relocs. * configure: Regenerate. Signed-off-by: Collin Funk <collin.funk1@gmail.com>
2024-06-19Improve gcc.dg/vect/bb-slp-32.c testcaseRichard Biener1-6/+20
The following adds a correctness check to the combined store/reduce vectorization. * gcc.dg/vect/bb-slp-32.c: Add check for correctness.
2024-06-19Fortran: Set the vptr of a class typed result.Andre Vehreschild5-11/+45
PR fortran/90076 gcc/fortran/ChangeLog: * trans-decl.cc (gfc_generate_function_code): Set vptr for results to declared class type. * trans-expr.cc (gfc_reset_vptr): Allow to provide the typespec instead of the expression. * trans.h (gfc_reset_vptr): Same. gcc/testsuite/ChangeLog: * gfortran.dg/class_76.f90: Add declared vtab occurrence. * gfortran.dg/class_78.f90: New test.
2024-06-19xtensa: constantsynth: Reforge to fix some non-fatal issuesTakayuki 'January June' Suwa3-30/+103
The previous constant synthesis logic had some issues that were non-fatal but worth considering: - It didn't work with DFmode literals, because those were cast to SImode rather SFmode when splitting into two natural-width words by split_double(). - It didn't work with large literals when TARGET_AUTO_LITPOOLS was enabled, because those were relaxed MOVI immediates rather references to literal pool entries, - It didn't take into account that when literals with the same RTL representation are pooled multiple times within a function, those entries are shared (especially important when optimizing for size). This patch addresses the above issues by making appropriate tweaks to the constant synthesis logic. gcc/ChangeLog: * config/xtensa/xtensa-protos.h (xtensa_constantsynth): Change the second argument from HOST_WIDE_INT to rtx. * config/xtensa/xtensa.cc (#include): Add "context.h" and "pass_manager.h". (machine_function): Add a new hash_map field "litpool_usage". (xtensa_constantsynth): Make "src" (the second operand) accept RTX literal instead of its value, and treat both bare and pooled SI/SFmode literals equally by bit-exact canonicalization into CONST_INT RTX internally. And then, make avoid synthesis if such multiple identical canonicalized literals are found in same function when optimizing for size. Finally, for literals where synthesis is not possible or has been avoided, re-emit "move" RTXes with canonicalized ones to increase the chances of sharing literal pool entries. * config/xtensa/xtensa.md (split patterns for constant synthesis): Change to simply invoke xtensa_constantsynth() as mentioned above, and add new patterns for when TARGET_AUTO_LITPOOLS is enabled.
2024-06-19RISC-V: Add testcases for unsigned .SAT_ADD vector form 8Pan Li9-0/+395
After the middle-end support the form 8 of unsigned SAT_ADD and the RISC-V backend implement the .SAT_ADD for vector mode, add more test case to cover the form 8. Form 8: #define DEF_VEC_SAT_U_ADD_FMT_8(T) \ void __attribute__((noinline)) \ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x > (T)(x + y) ? -1 : (x + y); \ } \ } Passed the rv64gcv regression tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper macro for testing. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
generated by cgit v1.1 at 2025-07-24 23:57:27 +0000