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2024-04-09Guard function->cond_uids access [PR114601]Jørgen Kvalsvik2-2/+18
PR114601 shows that it is possible to reach the condition_uid lookup without having also created the fn->cond_uids, through compiler-generated conditionals. Consider all lookups on non-existing maps misses, which they are from the perspective of the source code, to avoid the NULL access. PR gcov-profile/114601 gcc/ChangeLog: * tree-profile.cc (condition_uid): Guard fn->cond_uids access. gcc/testsuite/ChangeLog: * gcc.misc-tests/gcov-pr114601.c: New test.
2024-04-09i386: Fix aes/vaes patterns [PR114576]Jakub Jelinek3-40/+121
On Wed, Apr 19, 2023 at 02:40:59AM +0000, Jiang, Haochen via Gcc-patches wrote: > > > (define_insn "aesenc" > > > - [(set (match_operand:V2DI 0 "register_operand" "=x,x") > > > - (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") > > > - (match_operand:V2DI 2 "vector_operand" "xBm,xm")] > > > + [(set (match_operand:V2DI 0 "register_operand" "=x,x,v") > > > + (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v") > > > + (match_operand:V2DI 2 "vector_operand" > > > + "xBm,xm,vm")] > > > UNSPEC_AESENC))] > > > - "TARGET_AES" > > > + "TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)" > > > "@ > > > aesenc\t{%2, %0|%0, %2} > > > + vaesenc\t{%2, %1, %0|%0, %1, %2} > > > vaesenc\t{%2, %1, %0|%0, %1, %2}" > > > - [(set_attr "isa" "noavx,avx") > > > + [(set_attr "isa" "noavx,aes,avx512vl") > > Shouldn't it be vaes_avx512vl and then remove " || (TARGET_VAES && > > TARGET_AVX512VL)" from condition. > > Since VAES should not imply AES, we need that "|| (TARGET_VAES && > TARGET_AVX512VL)" > > And there is no need to add vaes_avx512vl since the last alternative will only > be hit when there is no aes. When there is no aes, the pattern will need vaes > and avx512vl both or we could not use this pattern. avx512vl here is just like > a placeholder. As the following testcase shows, the above change was incorrect. Using aes isa for the second alternative is obviously wrong, aes is enabled whenever -maes is, regardless of -mavx or -mno-avx, so the above change means that for -maes -mno-avx RA can choose, either it matches the first alternative with the dup operand, or it matches the second one (but that is of course wrong because vaesenc VEX encoded insn needs AES & AVX CPUID). The big question is if "Since VAES should not imply AES" is the case or not. Looking around at what LLVM does on godbolt, seems since clang 6 which added -mvaes support -mvaes there implies -maes, but GCC treats those two independent. Now, if we'd take the LLVM path of making -mvaes imply -maes and -mno-aes imply -mno-vaes, then we should probably just revert the above patch and tweak common/config/i386/ to do the implications (+ add the testcase from this patch). If we keep the current behavior, where AES and VAES are completely independent extensions, then we need to do more changes as the following patch attempts to do. We should use the aesenc etc. insns for noavx as before, we know at that point that TARGET_AES must be true because (TARGET_VAES && TARGET_AVX512VL) won't be true when !TARGET_AVX - TARGET_AVX512VL implies TARGET_AVX. For the second alternative, i.e. the AVX AES VEX or VAES AVX512F EVEX case without using %xmm16+/EGPR regs, the patch uses avx isa, but we need to emit {evex} prefix in the assembly if AES ISA is not enabled. For the last alternative, we need to use a new vaes_avx512vl isa attribute, because the %xmm16+/EGPR support is there only if both VAES and AVX512VL is enabled, not just AVX and AES. Still, I wonder if -mvaes shouldn't imply at least -mavx512f and -mno-avx512f shouldn't imply -mno-vaes, because otherwise can't see how it could use 512-bit registers (this part not done in the patch). 2024-04-09 Jakub Jelinek <jakub@redhat.com> PR target/114576 * config/i386/i386.md (isa): Remove aes, add vaes_avx512vl. (enabled): Remove aes isa check, add vaes_avx512vl. * config/i386/sse.md (aesenc, aesenclast, aesdec, aesdeclast): Use jm instead of m for second alternative and emit {evex} prefix for it if !TARGET_AES. Use noavx,avx,vaes_avx512vl isa attribute. (vaesdec_<mode>, vaesdeclast_<mode>, vaesenc_<mode>, vaesenclast_<mode>): Add second alternative with x instead of v and jm instead of m. * gcc.target/i386/aes-pr114576.c: New test.
2024-04-09modula2: remove description of fdebug-trace-quad, fdebug-trace-api and add ↵Gaius Mulley1-8/+5
fm2-debug-trace= This documentation fix removes the descriptions of -fdebug-trace-quad and -fdebug-trace-api. It adds a description of -fm2-debug-trace= together with the trace alternatives: line,token,quad,all. gcc/ChangeLog: * doc/gm2.texi (Compiler options): Remove -fdebug-trace-quad. Remove -fdebug-trace-api. Add -fm2-debug-trace=. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-04-09modula2: tidyup makeSystemGaius Mulley1-5/+9
This patch provides a tidyup for gcc/m2/tools-src/makeSystem. It only runs the compiler once and will echo a debug command line should it fail. gcc/m2/ChangeLog: * tools-src/makeSystem: Invoke ${COMPILER} once and adjust the echo string to expand the shell variables with -wrapper gdb, --args. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-04-09LoongArch: Enable switchable targetYang Yujie5-17/+127
This patch fixes the back-end context switching in cases where functions should be built with their own target contexts instead of the global one, such as LTO linking and functions with target attributes (TBD). PR target/113233 gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_reg_init): Reinitialize the loongarch_regno_mode_ok cache. (loongarch_option_override): Same. (loongarch_save_restore_target_globals): Restore target globals. (loongarch_set_current_function): Restore the target contexts for functions. (TARGET_SET_CURRENT_FUNCTION): Define. * config/loongarch/loongarch.h (SWITCHABLE_TARGET): Enable switchable target context. * config/loongarch/loongarch-builtins.cc (loongarch_init_builtins): Initialize all builtin functions at startup. (loongarch_expand_builtin): Turn assertion of builtin availability into a test. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Define condition loongarch_sx_as. * gcc.dg/lto/pr113233_0.c: New test.
2024-04-09rust: Add rust.install-dvi and rust.install-html rulesChristophe Lyon1-0/+2
rust has the (empty) rust.dvi and rust.html rules, but lacks the (empty) rust.install-dvi and rust.install-html ones. 2024-04-04 Christophe Lyon <christophe.lyon@linaro.org> gcc/rust/ * Make-lang.in (rust.install-dvi, rust.install-html): New rules.
2024-04-09Generate constant at start of loop, without UBJørgen Kvalsvik1-5/+15
Generating the constants used for recording the edges taken for condition coverage would trigger undefined behavior when an expression had exactly 64 (== sizeof (1ULL)) conditions, as it would generate the constant for the next iteration at the end of the loop body, even if there was never a next iteration. By moving the check and constant generation to the top of the loop and hoisting the increment flag there is no opportunity for UB. PR middle-end/114627 gcc/ChangeLog: * tree-profile.cc (instrument_decisions): Generate constant at the start of loop.
2024-04-09Add tree-inlined gconds to caller cond->expr mapJørgen Kvalsvik2-19/+76
Properly add the condition -> expression mapping of inlined gconds from the caller into the callee map. This is a fix for PR114599 that works beyond fixing the segfault, as the previous fixed copied references to the source gconds, not the deep copied ones that end up in the calle body. The new tests checks this, both in the case of a calle without conditions (which triggered the segfault), and a test that shows that conditions are properly mapped, and not mixed. PR middle-end/114599 gcc/ChangeLog: * tree-inline.cc (copy_bb): Copy cond_uids into callee. (prepend_lexical_block): Remove outdated comment. (add_local_variables): Remove bad cond_uids copy. gcc/testsuite/ChangeLog: * gcc.misc-tests/gcov-19.c: New test.
2024-04-09libquadmath: Provide __BYTE_ORDER, __LITTLE_ENDIAN and __BIG_ENDIAN definitionsJakub Jelinek1-0/+5
My earlier libquadmath change apparently broke mingw32 build, while on Linux <bits/endian.h> is included and defines these, on Mingw apparently that isn't the case, while soft-fp wants a guarantee that sfp-machine.h defines these. 2024-04-09 Jakub Jelinek <jakub@redhat.com> * sfp-machine.h (__LITTLE_ENDIAN, __BIG_ENDIAN, __BYTE_ORDER): Define if __BYTE_ORDER isn't defined.
2024-04-09c++: Fix up maybe_warn_for_constant_evaluated calls [PR114580]Jakub Jelinek2-7/+31
When looking at maybe_warn_for_constant_evaluated for the trivial infinite loops patch, I've noticed that it can emit weird diagnostics for if constexpr in templates, first warn that std::is_constant_evaluted() always evaluates to false (because the function template is not constexpr) and then during instantiation warn that std::is_constant_evaluted() always evaluates to true (because it is used in if constexpr condition). Now, only the latter is actually true, even when the if constexpr is in a non-constexpr function, it will still always evaluate to true. So, the following patch fixes it to call maybe_warn_for_constant_evaluated always with IF_STMT_CONSTEXPR_P (if_stmt) as the second argument rather than true if it is if constexpr with non-dependent condition etc. 2024-04-09 Jakub Jelinek <jakub@redhat.com> PR c++/114580 * semantics.cc (finish_if_stmt_cond): Call maybe_warn_for_constant_evaluated with IF_STMT_CONSTEXPR_P (if_stmt) as the second argument, rather than true/false depending on if it is if constexpr with non-dependent constant expression with bool type. * g++.dg/cpp2a/is-constant-evaluated15.C: New test.
2024-04-09Fix up duplicated words mostly in comments, part 2Jakub Jelinek28-36/+36
Another patch from eyeballing git grep -v 'long long\|optab optab\|template template\|double double' | grep ' \([a-zA-Z]\+\) \1 ' output, this time in gcc/ subdirectory. 2024-04-09 Jakub Jelinek <jakub@redhat.com> gcc/ * expr.cc (convert_mode_scalar): Fix duplicated words in comment; into into -> it into. * function.h (function::cond_uids): Fix duplicated words in comment; same same -> same. * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): Fix duplicated words in comment; model model -> model. * config/riscv/riscv-vector-builtins-shapes.cc (build_base): Fix duplicated words in comment; for for -> for. * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Fix duplicated words in comment; more more -> more. * config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Fix duplicated words in comment; be be -> be. * tree-profile.cc (masking_vectors): Fix duplicated words in comment; has has -> has, the the -> the. * value-range.cc (irange::set_range_from_bitmask): Fix duplicated words in comment; the the -> the. * gcov.cc (add_condition_counts): Fix duplicated words in comment; to to -> to. * vr-values.cc (get_scev_info): Fix duplicated words in comment; the the -> to the. * tree-vrp.cc (fully_replaceable): Fix duplicated words in comment; by by -> by. * mode-switching.cc (single_succ_confluence_n): Fix duplicated words in comment; the the -> the. * tree-ssa-phiopt.cc (value_replacement): Fix duplicated words in comment; can can -> we can. * gimple-range-phi.cc (phi_analyzer::process_phi): Fix duplicated words in comment; it it -> it is. * tree-ssa-sccvn.cc (visit_phi): Fix duplicated words in comment; to to -> to. * rtl-ssa/accesses.h (use_info::next_debug_insn_use): Fix duplicated words in comment; if if -> if. * doc/options.texi (InverseMask): Fix duplicated words; and and -> and. Change take to takes. * doc/invoke.texi (fanalyzer-undo-inlining): Fix duplicated words; be be -> be. (-minline-memops-threshold): Likewise. gcc/analyzer/ * analyzer.opt (Wanalyzer-undefined-behavior-strtok): Fix duplicated words; in in -> in. * program-state.cc (sm_state_map::replay_call_summary): Fix duplicated words in comment; to to -> to. (program_state::replay_call_summary): Likewise. * region-model.cc (region_model::replay_call_summary): Likewise. gcc/c/ * c-decl.cc (previous_tag): Fix duplicated words in comment; the the -> the. (diagnose_mismatched_decls): Fix duplicated words in comment; about about -> about. gcc/cp/ * constexpr.cc (build_new_constexpr_heap_type): Fix duplicated words in comment; is is -> is. * cp-tree.def (CO_RETURN_EXPR): Fix duplicated words in comment; for for -> for. * parser.cc (fixup_blocks_walker): Fix duplicated words in comment; is is -> is. * semantics.cc (fixup_template_type): Fix duplicated words in comment; for for -> for. (finish_omp_for): Fix duplicated words in comment; the the -> the. * pt.cc (more_specialized_fn): Fix duplicated words in comment; think think -> think. (type_targs_deducible_from): Fix duplicated words in comment; the the -> the. gcc/jit/ * docs/topics/expressions.rst (Constructor expressions): Fix duplicated words; have have -> have.
2024-04-09bitint: Don't move debug stmts from before returns_twice calls [PR114628]Jakub Jelinek2-2/+36
Debug stmts are allowed by the verifier before the returns_twice calls. More importantly, they don't have a lhs, so the current handling of arg_stmts statements to force them on the edges ICEs. The following patch just keeps them where they were before. 2024-04-09 Jakub Jelinek <jakub@redhat.com> PR middle-end/114628 * gimple-lower-bitint.cc (gimple_lower_bitint): Keep debug stmts before returns_twice calls as is, don't push them into arg_stmts vector/move to edges. * gcc.dg/bitint-105.c: New test.
2024-04-09libgcc: Add basic support for aarch64-gnu (GNU/Hurd on AArch64)Sergey Bugaev3-2/+47
There is currently no unwinding implementation. libgcc/ChangeLog: * config.host: Recognize aarch64*-*-gnu* hosts. * config/aarch64/gnu-unwind.h: New file. * config/aarch64/heap-trampoline.c (allocate_trampoline_page): Support GNU/Hurd. Signed-off-by: Sergey Bugaev <bugaevc@gmail.com>
2024-04-09aarch64: Add support for aarch64-gnu (GNU/Hurd on AArch64)Sergey Bugaev2-0/+74
Coupled with a corresponding binutils patch, this produces a toolchain that can sucessfully build working binaries targeting aarch64-gnu. gcc/Changelog: * config.gcc: Recognize aarch64*-*-gnu* targets. * config/aarch64/aarch64-gnu.h: New file. Signed-off-by: Sergey Bugaev <bugaevc@gmail.com>
2024-04-09Move GNU/Hurd startfile spec from config/i386/gnu.h to config/gnu.hSergey Bugaev2-11/+16
Since it's not i386-specific; this makes it possible to reuse it for other architectures. Also, add a warning for the case gnu.h is specified before gnu-user.h, which would cause gnu-user's version of the spec to override gnu's, and not the other way around as it's intended. The i?86-gnu target currently specifies them in the right order, but it's easy to accidentally put them in a wrong order. gcc/Changelog: * config/i386/gnu.h: Move GNU/Hurd STARTFILE_SPEC from here... * config/gnu.h: ...to here. Signed-off-by: Sergey Bugaev <bugaevc@gmail.com>
2024-04-09middle-end/114604 - ranger allocates bitmap without initialized obstackRichard Biener1-0/+4
The following fixes ranger bitmap allocation when invoked from IPA context where the global bitmap obstack possibly isn't initialized. Instead of trying to use one of the ranger obstacks the following simply initializes the global bitmap obstack around an active ranger. PR middle-end/114604 * gimple-range.cc (enable_ranger): Initialize the global bitmap obstack. (disable_ranger): Release it.
2024-04-09RTEMS: Add multilib configuration for aarch64Sebastian Huber2-0/+43
Add a multilib with workarounds for Cortex-A53 errata. gcc/ChangeLog: * config.gcc (aarch64-*-rtems*): Add target makefile fragment t-aarch64-rtems. * config/aarch64/t-aarch64-rtems: New file.
2024-04-09libquadmath: Use soft-fp for sqrtq finite positive arguments [PR114623]Jakub Jelinek2-1/+78
sqrt should be 0.5ulp precise, but the current implementation is less precise than that. The following patch uses the soft-fp code (like e.g. glibc for x86) for it if possible. I didn't want to replicate the libgcc infrastructure for choosing the right sfp-machine.h, so the patch just uses a single generic implementation. As the code is used solely for the finite positive arguments, it shouldn't generate NaNs (so the exact form of canonical QNaN/SNaN is irrelevant), and sqrt for these shouldn't produce underflows/overflows either, for < 1.0 arguments it always returns larger values than the argument and for > 1.0 smaller values than the argument. 2024-04-09 Jakub Jelinek <jakub@redhat.com> PR libquadmath/114623 * sfp-machine.h: New file. * math/sqrtq.c: Include from libgcc/soft-fp also soft-fp.h and quad.h if possible. (USE_SOFT_FP): Define in that case. (sqrtq): Use soft-fp based implementation for the finite positive arguments if possible.
2024-04-08x86: Define __APX_INLINE_ASM_USE_GPR32__H.J. Lu2-0/+8
Define __APX_INLINE_ASM_USE_GPR32__ for -mapx-inline-asm-use-gpr32. When __APX_INLINE_ASM_USE_GPR32__ is defined, inline asm statements should contain only instructions compatible with r16-r31. gcc/ PR target/114587 * config/i386/i386-c.cc (ix86_target_macros_internal): Define __APX_INLINE_ASM_USE_GPR32__ for -mapx-inline-asm-use-gpr32. gcc/testsuite/ PR target/114587 * gcc.target/i386/apx-3.c: Likewise.
2024-04-08testsuite: Add profile_update_atomic check to gcov-20.c [PR114614]Kewen Lin1-0/+1
As PR114614 shows, the newly added test case gcov-20.c by commit r14-9789-g08a52331803f66 failed on targets which do not support atomic profile update, there would be a message like: warning: target does not support atomic profile update, single mode is selected Since the test case adopts -fprofile-update=atomic, it requires effective target check profile_update_atomic, this patch is to add the check accordingly. PR testsuite/114614 gcc/testsuite/ChangeLog: * gcc.misc-tests/gcov-20.c: Add effective target check profile_update_atomic.
2024-04-08rs6000: Fix wrong align passed to build_aligned_type [PR88309]Kewen Lin4-3/+33
As the comments in PR88309 show, there are two oversights in rs6000_gimple_fold_builtin that pass align in bytes to build_aligned_type but which actually requires align in bits, it causes unexpected ICE or hanging in function is_miss_rate_acceptable due to zero align_unit value. This patch is to fix them by converting bytes to bits, add an assertion on positive align_unit value and notes function build_aligned_type requires align measured in bits in its function comment. PR target/88309 Co-authored-by: Andrew Pinski <quic_apinski@quicinc.com> gcc/ChangeLog: * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Fix wrong align passed to function build_aligned_type. * tree-ssa-loop-prefetch.cc (is_miss_rate_acceptable): Add an assertion to ensure align_unit should be positive. * tree.cc (build_qualified_type): Update function comments. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr88309.c: New test.
2024-04-09PR modula2/114648 cc1gm2 by default does not handle C pre-processor file and ↵Gaius Mulley4-1/+50
line directives This patch fixes the default behavior of cc1gm2 to the description in the documentation. By default cc1gm2 will allow C preprocessor directives (they can be turned off via -fno-cpp). gcc/m2/ChangeLog: PR modula2/114648 * gm2-compiler/M2Options.mod (LineDirectives): Initially set to true. gcc/testsuite/ChangeLog: PR modula2/114648 * gm2/cpp/default/pass/AdvParse.def: New test. * gm2/cpp/default/pass/AdvParse.mod: New test. * gm2/cpp/default/pass/cpp-default-pass.exp: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-04-09Daily bump.GCC Administrator8-1/+273
2024-04-08combine: Fix ICE in try_combine on pr112494.c [PR112560]Uros Bizjak2-5/+15
The compiler, configured with --enable-checking=yes,rtl,extra ICEs with: internal compiler error: RTL check: expected elt 0 type 'e' or 'u', have 'E' (rtx unspec) in try_combine, at combine.cc:3237 This is 3236 /* Just replace the CC reg with a new mode. */ 3237 SUBST (XEXP (*cc_use_loc, 0), newpat_dest); 3238 undobuf.other_insn = cc_use_insn; in combine.cc, where *cc_use_loc is (unspec:DI [ (reg:CC 17 flags) ] UNSPEC_PUSHFL) combine assumes CC must be used inside of a comparison and uses XEXP (..., 0) without checking on the RTX type of the argument. Replace cc_use_loc with the entire new RTX only in case cc_use_loc satisfies COMPARISON_P predicate. Otherwise scan the entire cc_use_loc RTX for CC reg to be updated with a new mode. PR rtl-optimization/112560 gcc/ChangeLog: * combine.cc (try_combine): Replace cc_use_loc with the entire new RTX only in case cc_use_loc satisfies COMPARISON_P predicate. Otherwise scan the entire cc_use_loc RTX for CC reg to be updated with a new mode. * config/i386/i386.md (@pushf<mode>2): Allow all CC modes for operand 1.
2024-04-08GCN: '--param=gcn-preferred-vectorization-factor=[default,32,64]'Thomas Schwinge36-2/+107
..., and specify '--param=gcn-preferred-vectorization-factor=64' for 'gcc.target/gcn/[...]' test cases with 'scan-assembler' directives that are specific to 64-lane vectors. This resolves regressions introduced in commit 6dedafe166cc02ae87b6a0699ad61ce3ffc46803 "amdgcn: Prefer V32 on RDNA devices". gcc/ * config/gcn/gcn.opt (--param=gcn-preferred-vectorization-factor): New. * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode) Use it. * doc/invoke.texi (Optimize Options): Document it. gcc/testsuite/ * gcc.target/gcn/cond_fmaxnm_1.c: Specify '--param=gcn-preferred-vectorization-factor=64'. * gcc.target/gcn/cond_fmaxnm_2.c: Likewise. * gcc.target/gcn/cond_fmaxnm_3.c: Likewise. * gcc.target/gcn/cond_fmaxnm_4.c: Likewise. * gcc.target/gcn/cond_fmaxnm_5.c: Likewise. * gcc.target/gcn/cond_fmaxnm_6.c: Likewise. * gcc.target/gcn/cond_fmaxnm_7.c: Likewise. * gcc.target/gcn/cond_fmaxnm_8.c: Likewise. * gcc.target/gcn/cond_fminnm_1.c: Likewise. * gcc.target/gcn/cond_fminnm_2.c: Likewise. * gcc.target/gcn/cond_fminnm_3.c: Likewise. * gcc.target/gcn/cond_fminnm_4.c: Likewise. * gcc.target/gcn/cond_fminnm_5.c: Likewise. * gcc.target/gcn/cond_fminnm_6.c: Likewise. * gcc.target/gcn/cond_fminnm_7.c: Likewise. * gcc.target/gcn/cond_fminnm_8.c: Likewise. * gcc.target/gcn/cond_shift_3.c: Likewise. * gcc.target/gcn/cond_shift_4.c: Likewise. * gcc.target/gcn/cond_shift_8.c: Likewise. * gcc.target/gcn/cond_shift_9.c: Likewise. * gcc.target/gcn/cond_smax_1.c: Likewise. * gcc.target/gcn/cond_smin_1.c: Likewise. * gcc.target/gcn/cond_umax_1.c: Likewise. * gcc.target/gcn/cond_umin_1.c: Likewise. * gcc.target/gcn/simd-math-1.c: Likewise. * gcc.target/gcn/simd-math-5-char.c: Likewise. * gcc.target/gcn/simd-math-5-long.c: Likewise. * gcc.target/gcn/simd-math-5-short.c: Likewise. * gcc.target/gcn/simd-math-5.c: Likewise. * gcc.target/gcn/smax_1.c: Likewise. * gcc.target/gcn/smin_1.c: Likewise. * gcc.target/gcn/umax_1.c: Likewise. * gcc.target/gcn/umin_1.c: Likewise.
2024-04-08New effective-target 'asm_goto_with_outputs'Thomas Schwinge15-15/+31
After commit e16f90be2dc8af6c371fe79044c3e668fa3dda62 "testsuite: Fix up lra effective target", we get for nvptx target: -PASS: gcc.c-torture/compile/asmgoto-2.c -O0 (test for excess errors) +ERROR: gcc.c-torture/compile/asmgoto-2.c -O0 : no files matched glob pattern "lra1020113.c.[0-9][0-9][0-9]r.reload" for " dg-do 2 compile { target lra } " Etc. However, nvptx appears to support 'asm goto' with outputs, including the new execution test case: PASS: gcc.dg/pr107385.c execution test Therefore, generally use new effective-target 'asm_goto_with_outputs' instead of 'lra'. One exceptions is 'gcc.dg/pr110079.c', which doesn't use 'asm goto' with outputs, and continues using effective-target 'lra', with special-casing nvptx target, to avoid ERROR for 'lra'. gcc/ * doc/sourcebuild.texi (Effective-Target Keywords): Document 'asm_goto_with_outputs'. Add comment to 'lra'. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_lra): Add comment. (check_effective_target_asm_goto_with_outputs): New. * gcc.c-torture/compile/asmgoto-2.c: Use it. * gcc.c-torture/compile/asmgoto-5.c: Likewise. * gcc.c-torture/compile/asmgoto-6.c: Likewise. * gcc.c-torture/compile/pr98096.c: Likewise. * gcc.dg/pr100590.c: Likewise. * gcc.dg/pr107385.c: Likewise. * gcc.dg/pr108095.c: Likewise. * gcc.dg/pr97954.c: Likewise. * gcc.dg/torture/pr100329.c: Likewise. * gcc.dg/torture/pr100398.c: Likewise. * gcc.dg/torture/pr100519.c: Likewise. * gcc.dg/torture/pr110422.c: Likewise. * gcc.dg/pr110079.c: Special-case nvptx target.
2024-04-08GCN, nvptx: Errors during device probing are fatalThomas Schwinge3-7/+12
Currently, we silently disable libgomp GCN and nvptx plugins/devices in presence of certain error conditions during device probing, thus typically silently resorting to host-fallback execution. Make such errors fatal, similar as for any other device access later on, so that we early and reliably notice when things go wrong. (Keep just two cases non-fatal: (a) libgomp GCN or nvptx plugins are available but 'libhsa-runtime64.so.1' or 'libcuda.so.1' are not, and (b) those are available, but the corresponding devices are not.) This resolves the issue that we've got execution test cases unexpectedly PASSing, despite: libgomp: GCN fatal error: Run-time could not be initialized Runtime message: HSA_STATUS_ERROR_OUT_OF_RESOURCES: The runtime failed to allocate the necessary resources. This error may also occur when the core runtime library needs to spawn threads or create internal OS-specific events. ..., and therefore they were not offloaded to the GCN device, but ran in host-fallback execution mode. What happend in that scenario is that in 'init_hsa_context' during the initial 'GOMP_OFFLOAD_get_num_devices' we ran into 'HSA_STATUS_ERROR_OUT_OF_RESOURCES', but it wasn't fatal, but just silently disabled the libgomp plugin/device. Especially "entertaining" were cases where such unintended host-fallback execution happened during effective-target checks like 'offload_device_available' (host-fallback execution there meaning: no offload device available), but actual test cases then were running with an offload device available, and therefore mis-configured. include/ * cuda/cuda.h (CUresult): Add 'CUDA_ERROR_NO_DEVICE'. libgomp/ * plugin/plugin-gcn.c (init_hsa_context): Add and handle 'bool probe' parameter. Adjust all users; errors during device probing are fatal. * plugin/plugin-nvptx.c (nvptx_get_num_devices): Aside from 'CUDA_ERROR_NO_DEVICE', errors during device probing are fatal.
2024-04-08Fortran: Accept again tab as alternative to space as separator [PR114304]Tobias Burnus2-1/+83
This fixes a side-effect of/regression caused by r14-9822-g93adf88cc6744a, which was for the same PR. PR libfortran/114304 libgfortran/ChangeLog: * io/list_read.c (eat_separator): Accept tab as alternative to space. gcc/testsuite/ChangeLog: * gfortran.dg/pr114304-2.f90: New test.
2024-04-08Update gcc fr.poJoseph Myers1-731/+536
* fr.po: Update.
2024-04-08ICF&SRA: Make ICF and SRA agree on paddingMartin Jambor14-55/+999
PR 113359 shows that (at least with -fno-strict-aliasing) ICF can unify two functions which copy an aggregate type of the same size but then SRA, through its total scalarization, can copy the aggregate by pieces, skipping paddding, but the padding was not the same in the two original functions that ICF unified. This patch enhances SRA with the ability to collect padding information which then can be compared from within ICF. Unfortunately SRA uses OPTION_SET_P when determining its limits, so ICF needs to switch cfuns at least once to figure it out too. gcc/ChangeLog: 2024-03-27 Martin Jambor <mjambor@suse.cz> PR ipa/113359 * ipa-icf-gimple.h (func_checker): New members safe_for_total_scalarization_p, m_total_scalarization_limit_known_p and m_total_scalarization_limit. (func_checker::func_checker): Initialize new member variables. * ipa-icf-gimple.cc: Include tree-sra.h. (func_checker::func_checker): Initialize new member variables. (func_checker::safe_for_total_scalarization_p): New function. (func_checker::compare_operand): Use the new function. * tree-sra.h (sra_get_max_scalarization_size): Declare. (sra_total_scalarization_would_copy_same_data_p): Likewise. * tree-sra.cc (prepare_iteration_over_array_elts): New function. (class sra_padding_collecting): New. (sra_padding_collecting::record_padding): Likewise. (scalarizable_type_p): Rename to totally_scalarizable_type_p. Add ability to record padding when requested. (totally_scalarize_subtree): Split out gathering information necessary to iterate over array elements to prepare_iteration_over_array_elts. Fix errornous early exit. (analyze_all_variable_accesses): Adjust the call to totally_scalarizable_type_p. Move determining of total scalariation size limit... (sra_get_max_scalarization_size): ...here. (check_ts_and_push_padding_to_vec): New function. (sra_total_scalarization_would_copy_same_data_p): Likewise. gcc/testsuite/ChangeLog: 2024-03-27 Martin Jambor <mjambor@suse.cz> PR ipa/113359 * gcc.dg/lto/pr113359-1_0.c: New. * gcc.dg/lto/pr113359-1_1.c: Likewise. * gcc.dg/lto/pr113359-2_0.c: Likewise. * gcc.dg/lto/pr113359-2_1.c: Likewise. * gcc.dg/lto/pr113359-3_0.c: Likewise. * gcc.dg/lto/pr113359-3_1.c: Likewise. * gcc.dg/lto/pr113359-4_0.c: Likewise. * gcc.dg/lto/pr113359-4_1.c: Likewise. * gcc.dg/lto/pr113359-5_0.c: Likewise. * gcc.dg/lto/pr113359-5_1.c: Likewise.
2024-04-08ipa: Compare jump functions in ICF (PR 113907)Martin Jambor8-1/+267
In PR 113907 comment #58, Honza found a case where ICF thinks bodies of functions are equivalent but becaise of difference in aliases in a memory access, different aggregate jump functions are associated with supposedly equivalent call statements. This patch adds a way to compare jump functions and plugs it into ICF to avoid the issue. gcc/ChangeLog: 2024-03-20 Martin Jambor <mjambor@suse.cz> PR ipa/113907 * ipa-prop.h (class ipa_vr): Declare new overload of a member function equal_p. (ipa_jump_functions_equivalent_p): Declare. * ipa-prop.cc (ipa_vr::equal_p): New function. (ipa_agg_pass_through_jf_equivalent_p): Likewise. (ipa_agg_jump_functions_equivalent_p): Likewise. (ipa_jump_functions_equivalent_p): Likewise. * ipa-cp.h (values_equal_for_ipcp_p): Declare. * ipa-cp.cc (values_equal_for_ipcp_p): Make function public. * ipa-icf-gimple.cc: Include alloc-pool.h, symbol-summary.h, sreal.h, ipa-cp.h and ipa-prop.h. (func_checker::compare_gimple_call): Comapre jump functions. gcc/testsuite/ChangeLog: 2024-03-20 Martin Jambor <mjambor@suse.cz> PR ipa/113907 * gcc.dg/lto/pr113907_0.c: New. * gcc.dg/lto/pr113907_1.c: Likewise. * gcc.dg/lto/pr113907_2.c: Likewise.
2024-04-08libstdc++: Use char for _Utf8_view if char8_t isn't available [PR114519]Jonathan Wakely2-2/+5
Instead of just omitting the definition of __unicode::_Utf8_view when char8_t is disabled, we can make it use char instead. libstdc++-v3/ChangeLog: PR libstdc++/114519 * include/bits/unicode.h (_Utf8_view) [!__cpp_char8_t]: Define using char instead of char8_t. * testsuite/ext/unicode/view.cc: Use u8""sv literals to create string views, instead of std::u8string_view.
2024-04-08libstdc++: Fix tests that fail with -fno-char8_tJonathan Wakely15-18/+26
Adjust expected errors or skip tests as UNSUPPORTED if -fno-char8_t is used in the test flags. libstdc++-v3/ChangeLog: * testsuite/20_util/integer_comparisons/equal_neg.cc: Use no-opts selector for errors that depend on -fchar8_t. * testsuite/20_util/integer_comparisons/greater_equal_neg.cc: Likewise. * testsuite/20_util/integer_comparisons/greater_neg.cc: Likewise. * testsuite/20_util/integer_comparisons/in_range_neg.cc: Likewise. * testsuite/20_util/integer_comparisons/less_equal_neg.cc: Likewise. * testsuite/20_util/integer_comparisons/less_neg.cc: Likewise. * testsuite/20_util/integer_comparisons/not_equal_neg.cc: Likewise. * testsuite/21_strings/basic_string/hash/hash_char8_t.cc: Skip if -fno-char8_t is used. * testsuite/21_strings/headers/cuchar/functions_std_cxx20.cc: Likewise. * testsuite/27_io/basic_ostream/inserters_character/char/deleted.cc: Likewise. * testsuite/27_io/basic_ostream/inserters_character/wchar_t/deleted.cc: Likewise. * testsuite/27_io/filesystem/path/factory/u8path-depr.cc: Use char for u8 literal if char8_t is not available. * testsuite/27_io/headers/iosfwd/synopsis.cc: Check __cpp_char8_t. * testsuite/29_atomics/atomic_integral/wait_notify.cc: Likewise. * testsuite/29_atomics/headers/atomic/types_std_c++20_neg.cc: Remove check for _GLIBCXX_USE_CHAR8_T.
2024-04-08libstdc++: Combine two std::from_chars tests into oneJonathan Wakely2-43/+7
We don't need separate tests for the C++17 and C++20 cases, we can just have one test that uses __cpp_char8_t to adjust whether it tests char8_t or not. This means the C++20 one doesn't fail if -fno-char8_t is used. libstdc++-v3/ChangeLog: * testsuite/20_util/from_chars/1_neg.cc: Add char8_t cases, using a struct of that name if -fno-char8_t is active. * testsuite/20_util/from_chars/1_c++20_neg.cc: Removed.
2024-04-08aarch64: Fix expansion of svsudot [PR114607]Richard Sandiford2-5/+5
Not sure how this happend, but: svsudot is supposed to be expanded as USDOT with the operands swapped. However, a thinko in the expansion of svsudot meant that the arguments weren't in fact swapped; the attempted swap was just a no-op. And the testcases blithely accepted that. gcc/ PR target/114607 * config/aarch64/aarch64-sve-builtins-base.cc (svusdot_impl::expand): Fix botched attempt to swap the operands for svsudot. gcc/testsuite/ PR target/114607 * gcc.target/aarch64/sve/acle/asm/sudot_s32.c: New test.
2024-04-08RISC-V: Implement TLS Descriptors.Tatsuyuki Ishi11-11/+115
This implements TLS Descriptors (TLSDESC) as specified in [1]. The 4-instruction sequence is implemented as a single RTX insn for simplicity, but this can be revisited later if instruction scheduling or more flexible RA is desired. The default remains to be the traditional TLS model, but can be configured with --with-tls={trad,desc}. The choice can be revisited once toolchain and libc support ships. [1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373. gcc/ChangeLog: * config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor. * config.gcc: Add --with-tls configuration option to change the default TLS flavor. * config/riscv/riscv.h: Add TARGET_TLSDESC determined from -mtls-dialect and with_tls defaults. * config/riscv/riscv-opts.h: Define enum riscv_tls_type for the two TLS flavors. * config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type. * config/riscv/riscv.md: Add instruction sequence for TLSDESC. * config/riscv/riscv.cc (riscv_symbol_insns): Add instruction sequence length data for TLSDESC. (riscv_legitimize_tls_address): Add lowering of TLSDESC. * doc/install.texi: Document --with-tls for RISC-V. * doc/invoke.texi: Document -mtls-dialect for RISC-V. gcc/testsuite/ChangeLog: * gcc.target/riscv/tls_1.x: Add TLSDESC GD test case. * gcc.target/riscv/tlsdesc.c: Same as above.
2024-04-08s390: Fix s390_const_int_pool_entry_p and movdi peephole2 [PR114605]Jakub Jelinek3-2/+59
The following testcase is miscompiled, because we have initially a movti which loads the 0x3f8000003f800000ULL TImode constant from constant pool. Later on we split it into a pair of DImode loads. Now, for the first load (why just that?, though not stage4 material) we trigger the peephole2 which uses s390_const_int_pool_entry_p. That function doesn't check at all the constant pool mode though, sees the constant pool at that address has a CONST_INT value and just assumes that is the value to return, which is especially wrong for big-endian, if it is a DImode load from offset 0, it should be loading 0 rather than 0x3f8000003f800000ULL. The following patch adds checks if we are extracing a MODE_INT mode, if the constant pool has MODE_INT mode as well, punts if constant pool has smaller mode size than the extraction one (then it would be UB), if it has the same mode as before keeps using what it did before, if constant pool has a larger mode than the one being extracted, uses simplify_subreg. I'd have used avoid_constant_pool_reference instead which can handle also offsets into the constant pool constants, but it can't handle UNSPEC_LTREF. Another thing is that once that is fixed, we ICE when we extract constant like 0, ior insn predicate require non-0 constant. So, the patch also fixes the peephole2 so that if either 32-bit half is zero, it uses a mere load of the constant into register rather than a pair of such load and ior. 2024-04-08 Jakub Jelinek <jakub@redhat.com> PR target/114605 * config/s390/s390.cc (s390_const_int_pool_entry_p): Punt if mem doesn't have MODE_INT mode, or pool constant doesn't have MODE_INT mode, or if pool constant mode is smaller than mem mode. If mem mode is different from pool constant mode, try to simplify subreg. If that doesn't work, punt, if it does, use the simplified constant instead of the constant pool constant. * config/s390/s390.md (movdi from const pool peephole): If either low or high 32-bit part is zero, just emit move insn instead of move + ior. * gcc.dg/pr114605.c: New test.
2024-04-08aarch64: Fix vld1/st1_x4 intrinsic testSwinney, Jonathan1-3/+7
The test for this intrinsic was failing silently and so it failed to report the bug reported in 114521. This patch modifes the test to report the result. Bug report: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114521 Signed-off-by: Jonathan Swinney <jswinney@amazon.com> gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: Exit with a nonzero code if the test fails.
2024-04-08ChangeLog: Add by hand ChangeLog entry for PR114361 revert.Jakub Jelinek2-0/+19
This commit has been added to IGNORED_COMMITS, because it contained bogus explanation of the standardized git revert message.
2024-04-08Daily bump.GCC Administrator14-1/+476
2024-04-08contrib: Add 8057f9aa1f7e70490064de796d7a8d42d446caf8 to ignored commits.Jakub Jelinek1-1/+2
This commit unfortunately added explanation to the git revert generated message, breaking ChangeLog generation. 2024-04-08 Jakub Jelinek <jakub@redhat.com> * gcc-changelog/git_update_version.py: Add 8057f9aa1f7e70490064de796d7a8d42d446caf8 to IGNORED_COMMITS.
2024-04-08tree-optimization/114624 - fix use-after-free in SCCPRichard Biener2-2/+22
We're inspecting the replaced PHI node after releasing it. PR tree-optimization/114624 * tree-scalar-evolution.cc (final_value_replacement_loop): Get at the PHI arg location before releasing the PHI node. * gcc.dg/torture/pr114624.c: New testcase.
2024-04-08RISC-V: Refine the error msg for RVV intrinisc required extPan Li15-19/+210
The RVV intrinisc API has sorts of required extension from both the march or target attribute. It will have error message similar to below: built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension However, it is not accurate as we have many additional sub extenstion besides v extension. For example, zvbb, zvbk, zvbc ... etc. This patch would like to refine the error message with a friendly hint for the required extension. For example as below: vuint64m1_t __attribute__((target("arch=+v"))) test_1 (vuint64m1_t op_1, vuint64m1_t op_2, size_t vl) { return __riscv_vclmul_vv_u64m1 (op_1, op_2, vl); } When compile with march=rv64gc and target arch=+v, we will have error message as below: error: built-in function '__riscv_vclmul_vv_u64m1(op_1, op_2, vl)' requires the 'zvbc' ISA extension Then the end-user will get the point that the *zvbc* extension is missing for the intrinisc API easily. The below tests are passed for this patch. * The riscv fully regression tests. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Pass required_ext arg when invoke add function. (build_th_loadstore): Ditto. (struct vcreate_def): Ditto. (struct read_vl_def): Ditto. (struct vlenb_def): Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::add_function): Introduce new arg required_ext to fill in the register func. (function_builder::add_unique_function): Ditto. (function_builder::add_overloaded_function): Ditto. (expand_builtin): Leverage required_extensions_specified to check if the required extension is provided. * config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name): New func impl to convert the required_ext enum to the extension name. (required_extensions_specified): New func impl to predicate if the required extension is well feeded. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c: Adjust the error message for v extension. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c: Ditto. * gcc.target/riscv/rvv/base/intrinsic_required_ext-1.c: New test. * gcc.target/riscv/rvv/base/intrinsic_required_ext-10.c: New test. * gcc.target/riscv/rvv/base/intrinsic_required_ext-2.c: New test. * gcc.target/riscv/rvv/base/intrinsic_required_ext-3.c: New test. * gcc.target/riscv/rvv/base/intrinsic_required_ext-4.c: New test. * gcc.target/riscv/rvv/base/intrinsic_required_ext-5.c: New test. * gcc.target/riscv/rvv/base/intrinsic_required_ext-6.c: New test. * gcc.target/riscv/rvv/base/intrinsic_required_ext-7.c: New test. * gcc.target/riscv/rvv/base/intrinsic_required_ext-8.c: New test. * gcc.target/riscv/rvv/base/intrinsic_required_ext-9.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-08Darwin: Sync coverage specs with gcc/gcc.cc.Iain Sandoe1-1/+1
The specs for coverage ere out of date leading to test fails for fcondition-coverage cases. Fixed by updating to match the specs in gcc/gcc.cc. gcc/ChangeLog: * config/darwin.h (LINK_COMMAND_SPEC_A): Update coverage specs. Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
2024-04-08RISC-V: Minor fix for max_pointdemin.han1-1/+1
The program points start from 1, so max_point should be equal to length(). Tested on RV64 and no regression. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc: Use length() Signed-off-by: demin.han <demin.han@starfivetech.com>
2024-04-08RISC-V: Allow RVV intrinsic for more function targetPan Li65-442/+1886
In previous, we allowed the target(("arch=+v")) for a function with rv64gc build. This patch would like to support more arch options as below: * zve32x * zve32f * zve64x * zve64f * zve64d * zvfhmin * zvfh * zvk* * zvbb For example, we have sample code as below. vfloat32m1_t __attribute__((target("arch=+zve64f"))) test_9 (vfloat32m1_t a, vfloat32m1_t b, size_t vl) { return __riscv_vfadd_vv_f32m1 (a, b, vl); } It will generate the asm code when build with -O3 -march=rv64gc test_9: vsetvli zero,a0,e32,m1,ta,ma vfadd.vv v8,v8,v9 ret Meanwhile, this patch introduces more error handling for the target attribute. Take arch=+zve32x with vfloat32m1_t will have error message "'vfloat32m1_t' requires the zve32f, zve64f or zve64d ISA extension". And take arch=+zve32f with vfloat16m1_t will have error message "'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension". By default, all the RVV types includes the cmdline march will be registered when include the riscv_vector.h. And we have sorts of check during args and return types. Below test are passed for this patch: * The riscv fully regression test. gcc/ChangeLog: * config/riscv/riscv-c.cc (struct pragma_intrinsic_flags): New struct to hold all intrinisc related flags. (riscv_pragma_intrinsic_flags_pollute): New func to pollute the intrinsic flags and backup original flags. (riscv_pragma_intrinsic_flags_restore): New func to restore the flags from the backup intrinsic flags. (riscv_pragma_intrinsic): Pollute the flags and register all possible builtin types and functions, then restore and reinit. * config/riscv/riscv-protos.h (reinit_builtins): New func decl to reinit after flags pollution. (riscv_option_override): New extern func decl. * config/riscv/riscv-vector-builtins.cc (register_builtin_types_on_null): New func to register builtin types if null. (DEF_RVV_TYPE): Ditto. (DEF_RVV_TUPLE_TYPE): Ditto. (reinit_builtins): New func impl to reinit after flags pollution. (expand_builtin): Return target rtx after error_at. * config/riscv/riscv.cc (riscv_vector_int_type_p): New predicate func to tell one tree type is integer or not. (riscv_vector_float_type_p): New predicate func to tell one tree type is float or not. (riscv_vector_element_bitsize): New func to get the element bitsize of a vector tree type. (riscv_vector_required_min_vlen): New func to get the required min vlen of a vector tree type. (riscv_validate_vector_type): New func to validate the tree type is valid on flags. (riscv_return_value_is_vector_type_p): Leverage the func riscv_validate_vector_type to do the tree type validation. (riscv_arguments_is_vector_type_p): Ditto. (riscv_override_options_internal): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr109479-1.c: Adjust the existing test scenarios and add new error check tests. * gcc.target/riscv/rvv/base/pr109479-2.c: Ditto. * gcc.target/riscv/rvv/base/pr109479-3.c: Ditto. * gcc.target/riscv/rvv/base/pr109479-4.c: Diito. * gcc.target/riscv/rvv/base/pr109479-5.c: Diito. * gcc.target/riscv/rvv/base/pr109479-6.c: Diito. * gcc.target/riscv/rvv/base/user-10.c: Ditto. * gcc.target/riscv/rvv/base/user-12.c: Ditto. * gcc.target/riscv/rvv/base/user-13.c: Ditto. * gcc.target/riscv/rvv/base/user-14.c: Ditto. * gcc.target/riscv/rvv/base/user-15.c: Ditto. * gcc.target/riscv/rvv/base/user-2.c: Ditto. * gcc.target/riscv/rvv/base/user-3.c: Ditto. * gcc.target/riscv/rvv/base/user-5.c: Ditto. * gcc.target/riscv/rvv/base/user-6.c: Ditto. * gcc.target/riscv/rvv/base/user-9.c: Ditto. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-30.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-31.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-32.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-33.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-34.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-35.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-36.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-37.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-38.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-40.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-41.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-47.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-48.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-49.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-50.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-51.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-52.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-53.c: New test. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-04-08LoongArch: Set default alignment for functions jumps and loops [PR112919].Lulu Cheng3-16/+36
Xi Ruoyao set the alignment rules under LA464 in commit r14-1839, but the macro ASM_OUTPUT_ALIGN_WITH_NOP was removed in R14-4674, which affected the alignment rules. So I set different aligns on LA464 and LA664 again to test the performance of spec2006, and modify the alignment based on the test results. gcc/ChangeLog: PR target/112919 * config/loongarch/loongarch-def.cc (la664_align): Newly defined function that sets alignment rules under the LA664 microarchitecture. * config/loongarch/loongarch-opts.cc (loongarch_target_option_override): If not optimizing for size, set the default alignment to what the target wants. * config/loongarch/loongarch-tune.h (struct loongarch_align): Add new member variables jump and loop.
2024-04-06PR modula2/114617 gm2 unable to resolve const expressions using relop ICEGaius Mulley12-104/+738
This patch allows cc1gm2 to resolve constant expressions which use relative operators. Previous to the patch the result of a relop was stored in a temporary variable set by an if then else quadruple sequence. This patch marks a const expression in the quadruples and then reduces this sequence of quadruples into a single assignment to an internal constant. gcc/m2/ChangeLog: PR modula2/114617 * gm2-compiler/M2GenGCC.mod (CodeStatememt): Add quad trace. (ResolveConstantExpressions): Add parameter p to FoldIfLess, FoldIfGre, FoldIfLessEqu, FoldIfGreEqu, FoldIfEqu, FoldIfNotEqu, FoldIfIn and FoldIfNotIn. (CodeInline): Add constExpr variable and pass it to GetQuadOtok. (CodeReturnValue): Ditto. (CodeParam): Ditto. (FoldStringLength): Ditto. (FoldStringConvertM2nul): Ditto. (FoldStringConvertCnul): Ditto. (DeclaredOperandsBecomes): Ditto. (TypeCheckBecomes): Ditto. (PerformFoldBecomes): Ditto. (CodeBecomes): Ditto. (CheckElementSetTypes): Ditto. (CodeBinarySet): Ditto. (PerformCodeIfLess): Ditto. (PerformCodeIfGre): Ditto. (PerformCodeIfLessEqu): Ditto. (PerformCodeIfGreEqu): Ditto. (PerformCodeIfEqu): Ditto. (PerformCodeIfNotEqu): Ditto. (IsValidExpressionRelOp): Ditto. (PerformCodeIfIn): Ditto. (PerformCodeIfNotIn): Ditto. (CodeXIndr): Ditto. (QuadCondition): New procedure function. (IsBooleanRelOpPattern): Ditto. (FoldBooleanRelopPattern): Ditto. (FoldIfGre): Check for boolean relop constant expression and add parameter p. (FoldIfLessEqu): Ditto. (FoldIfIn): Ditto. (FoldIfEqu): Ditto. (FoldIfNotIn): Ditto. (FoldIfGreEqu): New procedure. (FoldIfNotEqu): Ditto. * gm2-compiler/M2Optimize.mod (ReduceBranch): Add constExpr variable and pass it to GetQuadOtok. * gm2-compiler/M2Quads.def (IsBecomes): New procedure function. (IsDummy): Ditto. (IsQuadConstExpr): Ditto. (SetQuadConstExpr): Ditto. (GetQuadDest): New procedure. (GetQuadOp1): New procedure. (GetQuadOp2): New procedure. (GetQuadOp3): New procedure. (GetQuadOtok): New procedure. (GetQuadOTypetok): New procedure. (PutQuadOtok): New procedure. (IsInConstParameters): New procedure function. * gm2-compiler/M2Quads.mod (IsBecomes): New procedure function. (IsDummy): Ditto. (IsQuadConstExpr): Ditto. (SetQuadConstExpr): Ditto. (GetQuadDest): New procedure. (GetQuadOp1): New procedure. (GetQuadOp2): New procedure. (GetQuadOp3): New procedure. (GetQuadOtok): New procedure. (GetQuadOTypetok): New procedure. (PutQuadOtok): New procedure. (IsInConstParameters): New procedure function. (ConstStack): Remove to ... (ConstExprStack): ... this. (ConstParamStack): New variable and initialize. (QuadFrame): New field ConstExpr. (GetQuadOtok): Add parameter constExpr and assign. (PutQuadOtok): Add constExpr parameter and assign. (PutQuadOType): Ditto. (GetQuadOTypetok): Ditto. (EraseQuad): Assign ConstExpr to FALSE. (FoldSubrange): Set ConstExpr to FALSE in BecomesOp. (PushInConstParameters): New procedure. (PopInConstParameters): New procedure. (IsInConstParameters): New procedure function. * gm2-compiler/M2SymInit.mod (IssueConditional): Add constExpr boolean variable. (CheckReadBeforeInitQuad): Ditto. (trashParam): Ditto. * gm2-compiler/P3Build.bnf (ConstExpression): Call PushInConstExpression and PopInConstExpression. (ConstSetOrQualidentOrFunction): Call PushInConstParameters and PopInConstParameters. * gm2-compiler/PCBuild.bnf (ConstExpression): Call PushInConstExpression and PopInConstExpression. * gm2-compiler/PHBuild.bnf: Ditto * gm2-gcc/m2expr.cc (m2expr_BuildCondIfExpression): New function. * gm2-gcc/m2expr.def (BuildCondIfExpression): New prototype. * gm2-gcc/m2expr.h (m2expr_BuildCondIfExpression): New function. gcc/testsuite/ChangeLog: PR modula2/114617 * gm2/iso/const/pass/iso-const-pass.exp: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-04-06libfortran: Fix handling of formatted separators.Jerry DeLisle3-7/+152
PR libfortran/114304 PR libfortran/105473 libgfortran/ChangeLog: * io/list_read.c (eat_separator): Add logic to handle spaces preceding a comma or semicolon such that that a 'null' read occurs without error at the end of comma or semicolon terminated input lines. Add check and error message for ';'. (list_formatted_read_scalar): Treat comma as a decimal point when specified by the decimal mode on the first item. gcc/testsuite/ChangeLog: * gfortran.dg/pr105473.f90: Modify to verify new error message. * gfortran.dg/pr114304.f90: New test.
2024-04-06d: Merge upstream dmd, druntime b65767825f, phobos 92dc5a4e9.Iain Buclaw8-10/+68
Synchronizing with the upstream release of v2.108.0. D front-end changes: - Import dmd v2.108.0. D runtime changes: - Import druntime v2.108.0. Phobos changes: - Import phobos v2.108.0. gcc/d/ChangeLog: * dmd/MERGE: Merge upstream dmd b65767825f. * dmd/VERSION: Bump version to v2.108.0. libphobos/ChangeLog: * libdruntime/MERGE: Merge upstream druntime b65767825f. * src/MERGE: Merge upstream phobos 92dc5a4e9.
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