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This patch fixes a crash in the compiler whereby calculating the accessibility
level of of a local variable whose original expression is an 'First on an
array type led to an error during compilation.
gcc/ada/
* accessibility.adb (Accessibility_Level): Add cases for 'First
and 'Last.
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This patch relaxes the restriction on 'Super such that it can apply to abstract
type objects.
gcc/ada/
* sem_attr.adb (Analyze_Attribute): Remove restriction on 'Super
for abstract types.
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Several of the implementation-defined attributes were wrongly recognized
as defined by the Ada RM.
This change only affects code with restriction
No_Implementation_Attributes.
gcc/ada/
* sem_attr.ads (Attribute_Impl_Def): Fix list of
implementation-defined attributes.
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Recognize references to attributes Old, Overlaps_Storage and Result as
language-defined in Ada 2012 and implementation-defined in earlier
versions of Ada. Other attributes introduced by Ada 2012 RM are
correctly categorized.
This change only affects code with restriction
No_Implementation_Attributes.
gcc/ada/
* sem_attr.adb (Attribute_12): Add attributes Old,
Overlaps_Storage and Result.
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Restriction No_Implementation_Attributes must not be applied to nodes
that come from expansion. In particular, it must not be applied to
Object_Size, which is implementation-defined attribute before Ada 2022,
but appears in expansion of tagged types since Ada 95.
gcc/ada/
* sem_attr.adb (Analyze_Attribute): Move IF statement that
checks restriction No_Implementation_Attributes for Ada 2005,
2012 and Ada 2022 attributes inside Comes_From_Source condition
that checks the same restriction for Ada 83 attributes.
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Code cleanup; semantics is unaffected.
gcc/ada/
* sem_attr.adb (Analyze_Attribute): Remove condition that is
already checked by an enclosing IF statement.
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Code cleanup.
gcc/ada/
* sem_attr.ads (Universal_Type_Attribute): Simplify using
array aggregate syntax with discrete choice list.
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Code cleanup.
gcc/ada/
* sem_attr.ads (Attribute_Impl_Def): Fix style in comment.
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This patch changes the task initialization subprograms on POSIX
platforms so that the thread ID of an ATCB is only set once.
This has the advantage of getting rid of the Atomic aspect on
the corresponding record component, and silences a Helgrind
warning about a data race.
gcc/ada/
* libgnarl/s-taprop__linux.adb (Enter_Task): Move setting
of thread ID out of Enter_Task.
(Initialize): Set thread ID for the environment task.
(Create_Task): Remove now unnecessary Unrestricted_Access
attribute and add justification for a memory write.
* libgnarl/s-taprop__posix.adb: Likewise.
* libgnarl/s-taprop__qnx.adb: Likewise.
* libgnarl/s-taprop__rtems.adb: Likewise.
* libgnarl/s-taprop__solaris.adb: Likewise.
* libgnarl/s-taspri__posix.ads: Remove pragma Atomic for
Private_Data.Thread, and update documentation comment.
* libgnarl/s-taspri__lynxos.ads: Likewise.
* libgnarl/s-taspri__posix-noaltstack.ads: Likewise.
* libgnarl/s-taspri__solaris.ads: Likewise.
* libgnarl/s-tporft.adb (Register_Foreign_Thread): Adapt to
Enter_Task not setting the thread ID anymore.
* libgnarl/s-tassta.adb (Task_Wrapper): Update comment.
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When an aggregate that needs to be converted into a series of assignments is
present in an expression of a parent aggregate, or in the expression of an
allocator, an object declaration, or an assignment in very specific cases,
its expansion is delayed until its parent itself is expanded. This makes
it possible to avoid creating a superfluous temporary for the aggregate.
This change extends the delaying mechanism in the case of record aggregates
to intermediate conditional expressions, that is to say, to the conditional
expressions that are present between the parent and the aggregate, provided
that the aggregate be a dependent expression, directly or recursively. This
again makes it possible to avoid creating a temporary for the aggregate.
gcc/ada/
* exp_aggr.ads (Is_Delayed_Conditional_Expression): New predicate.
* exp_aggr.adb (Convert_To_Assignments.Known_Size): Likewise.
(Convert_To_Assignments): Climb the parent chain, looking through
qualified expressions and dependent expressions of conditional
expressions, to find out whether the expansion may be delayed.
Call Known_Size for this in the case of an object declaration.
If so, set Expansion_Delayed on the aggregate as well as all the
intermediate conditional expressions.
(Initialize_Component): Reset the Analyzed flag on an initialization
expression that is a conditional expression whose expansion has been
delayed.
(Is_Delayed_Conditional_Expression): New predicate.
* exp_ch3.adb (Expand_N_Object_Declaration): Handle initialization
expressions that are conditional expressions whose expansion has
been delayed.
* exp_ch4.adb (Build_Explicit_Assignment): New procedure.
(Expand_Allocator_Expression): Handle initialization expressions
that are conditional expressions whose expansion has been delayed.
(Expand_N_Case_Expression): Deal with expressions whose expansion
has been delayed by waiting for the rewriting of their parent as
an assignment statement and then optimizing the assignment.
(Expand_N_If_Expression): Likewise.
(Expand_N_Qualified_Expression): Do not apply a predicate check to
an operand that is a delayed aggregate or conditional expression.
* gen_il-gen-gen_nodes.adb (N_If_Expression): Add Expansion_Delayed
semantic flag.
(N_Case_Expression): Likewise.
* sinfo.ads (Expansion_Delayed): Document extended usage.
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This change set addresses various compilation and execution problems
encountered in the draft ACATS tests for container aggregates:
C435001 (container aggregates with Assign_Indexed)
C435002 (container aggregates with Add_Unnamed)
C435003 (container aggregates with Add_Named)
C435004 (container aggregates with Assign_Indexed and Add_Unnamed)
gcc/ada/
* exp_aggr.adb (Expand_Container_Aggregate): Add top-level
variables Choice_{Lo|Hi} and Int_Choice_{Lo|Hi} used for
determining the low and high bounds of component association
choices. Replace code for determining whether we have an indexed
aggregate with call to new function Sem_Aggr.Is_Indexed_Aggregate.
Remove test of whether Empty_Subp is a function, since it must be
a function. Move Default and Count_Type to be locals of a new
block enclosing the code that creates the object to hold the
aggregate length, and set them according to the default and type
of the Empty function's parameter when present (and to Empty and
Standard_Natural otherwise). Use Siz_Exp for the aggregate length
when set, and use Empty's default length when available, and use
zero for the length otherwise. In generating the call to the
New_Indexed function, use the determined lower and upper bounds if
determined earlier by Aggregate_Size, and otherwise compute those
from the index type's lower bound and the determined aggregate
length. In the case where a call to Empty is generated and the
function has a formal parameter, pass the value saved in Siz_Decl
(otherwise the parameter list is empty). Remove code specific to
making a parameterless call to the Empty function. Extend the code
for handling positional container aggregates to account for types
that define Assign_Indexed, rather than just Add_Unnamed, and in
the case of indexed aggregates, create a temporary object to hold
values of the aggregate's key index, and initialize and increment
that temporary for each call generated to the Assign_Indexed
procedure. For named container aggregates that have key choices
given by ranges, call Expand_Range_Component to generate a loop
that will call the appropriate insertion procedure for each value
of the range. For indexed aggregates with a Component_Associations
list, set and use the Assign_Indexed procedure for each component
association, whether or not there's an iterator specification.
(Add_Range_Size): Add code to determine the low and high bounds of
the range and capture those in up-level variables when their value
is less than or greater than (respectively) the current minimum
and maximum bounds values.
(Aggregate_Size): Separately handle the case where a single choice
is of a discrete type, and call Add_Range_Size to take its value
into consideration for determination of min and max bounds of the
aggregate. Add comments in a couple of places.
(Build_Siz_Exp): Remove the last sentence and "???" from the
comment that talks about accumulating nonstatic sizes, since that
sentence seems to be obsolete. Record the low and high bound
values in Choice_Lo and Choice_Hi in the case of a nonstatic
range.
(Expand_Iterated_Component): Set the Defining_Identifier of the
iterator specification to the Loop_Id in the
N_Iterated_Component_Association case.
(Expand_Range_Component): Procedure unnested from the block
handling indexed aggregates in Expand_Container_Aggregate, and
moved to top level of that procedure so it can also be called for
Add_Named cases. A formal parameter Insert_Op is added, and
existing calls to this procedure are changed to pass the
appropriate insertion procedure's Entity.
* sem_aggr.ads: Add with_clause for Sinfo.Nodes.
(Is_Indexed_Aggregate): New function for use by
Resolve_Container_Aggregate and Expand_Container_Aggregate.
* sem_aggr.adb: Add with_clause for Sem_Ch5. Move with_clause for
Sinfo.Nodes to sem_aggr.ads.
(Is_Indexed_Aggregate): New function to determine whether a
container aggregate is a container aggregate (replacing local
variable of the same name in Resolve_Container_Aggregate).
(Resolve_Iterated_Association): Remove part of comment saying that
a Key_Expression is always present. Set Parent field of the copy
of a component association with a loop parameter specification. On
the setting of Loop_Param_Id, account for a
Loop_Parameter_Specification being changed into an
Iterator_Specification as a result of being analyzed. Only call
Preanalyze_And_Resolve on Key_Expr when a key expression is
actually present. Remove loop for handling choices for the case of
an N_Component_Association with a Defining_Identifier (there
shouldn't be more than one choice in this case, and add an
assertion to ensure that). Also add code here to handle the case
where the choice is a function call, creating an
iterator_specification analyzing it, and call
Resolve_Iterated_Association recursively to process it. Add error
check to enforce RM22 4.3.5(27), which requires that the type of
the loop parameter must be the same as the key type when there is
no key expression and the aggregate is an indexed aggregate or has
an Add_Named op.
(Resolve_Container_Aggregate): In the Add_Unnamed case, call
Resolve_Iterated_Association for both
N_Iterated_Element_Association and N_Component_Association (rather
than just the latter). Remove error check for nonstatic choices in
component associations in Add_Named cases (multiple named
nonstatic associations are fine except in indexed aggregates).
Remove local variable Is_Indexed_Aggregate, replaced with new
library-level function of the same name, and add test of
Is_Indexed_Aggregate in the case where the aggregate type has an
Assign_Indexed operation, as a guard for doing error checks for
indexed aggregates. For indexed aggregate resolution, do not call
Analyze_And_Resolve on the expression of an
N_Component_Association in the "box association" case. Move error
checks for indexed aggregates with iterated associations that flag
cases where an association is a loop_parameter_specification with
an iterator filter or a key expression (violation of RM22
4.3.5(28/5)), from the loop that checks for contiguous and
nonoverlapping choices and into the preceding association loop
after the call to Resolve_Iterated_Association. The RM reference
is added to the error-message strings.
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Before this patch, on Linux, the procedure
System.Task_Primitives.Operations.Set_Task_Affinity called CPU_FREE on
instances of cpu_set_t_ptr that it didn't own when the obsolescent
Task_Info pragma was in play. This patch fixes that issue.
gcc/ada/
* libgnarl/s-taprop__linux.adb (Set_Task_Affinity): Fix
decision about whether to call CPU_FREE.
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This eliminates a few more oddities present in the expander for allocators
and aggregates nested in allocators and other constructs:
- Convert_Aggr_In_Allocator takes both the N_Allocator and the aggregate
as parameters, while the sibling procedures Convert_Aggr_In_Assignment
and Convert_Aggr_In_Object_Decl only take the former. This changes the
first to be consistent with the two others and propagates the change to
Convert_Array_Aggr_In_Allocator.
- Convert_Aggr_In_Object_Decl contains an awkward code structure with a
useless inner block statement.
- In_Place_Assign_OK and Convert_To_Assignments have some declarations of
local variables not in the right place.
No functional changes (presumably).
gcc/ada/
* exp_aggr.ads (Convert_Aggr_In_Allocator): Remove Aggr parameter
and adjust description.
(Convert_Aggr_In_Object_Decl): Adjust description.
* exp_aggr.adb (Convert_Aggr_In_Allocator): Remove Aggr parameter
and add local variable of the same name instead. Adjust call to
Convert_Array_Aggr_In_Allocator.
(Convert_Aggr_In_Object_Decl): Add comment for early return and
remove useless inner block statement.
(Convert_Array_Aggr_In_Allocator): Remove Aggr parameter and add
local variable of the same name instead.
(In_Place_Assign_OK): Move down declarations of local variables.
(Convert_To_Assignments): Put all declarations of local variables
in the same place. Fix typo in comment. Replace T with Full_Typ.
* exp_ch4.adb (Expand_Allocator_Expression): Call Unqualify instead
of Expression on the qualified expression of the allocator for the
sake of consistency. Adjust call to Convert_Aggr_In_Allocator.
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Fix a short-circuit folding of 'Img for enumeration type, which wrongly
ignored Discard_Names and exposed enumeration literals.
gcc/ada/
* sem_attr.adb (Eval_Attribute): Handle enumeration type with
Discard_Names.
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Fix computation of attribute 'Width for enumeration types with
Discard_Name aspect enabled.
gcc/ada/
* exp_imgv.adb (Expand_Width_Attribute): Fix for 'Width that
is computed at run time.
* sem_attr.adb (Eval_Attribute): Fix for 'Width that is computed
at compilation time.
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Some architectures don't let us convert
System.Storage_Elements.Integer_Address back to a valid System.Address.
Using the arithmetic operations on System.Address from
System.Storage_Elements prevents the problem while leaving semantics
unchanged.
gcc/ada/
* libgnat/s-pooglo.adb (Allocate): Use arithmetic on
System.Address to compute the aligned address.
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For a discrete (or fixed-point) type T, GNAT requires that T'Object_Size
shall be a multiple of T'Alignment * 8 .
GNAT also requires that T'Object_Size shall be no larger than
Standard'Max_Integer_Size.
For a sufficiently-large alignment specification, these requirements can
conflict.
The conflict is resolved by rejecting such alignment specifications (which
were previously accepted in some cases).
gcc/ada/
* freeze.adb (Adjust_Esize_For_Alignment): Assert that a valid
Alignment specification cannot result in adjusting the given
type's Esize to be larger than System_Max_Integer_Size.
* sem_ch13.adb (Analyze_Attribute_Definition_Clause): In analyzing
an Alignment specification, enforce the rule that a specified
Alignment value for a discrete or fixed-point type shall not be
larger than System_Max_Integer_Size / 8 .
gcc/testsuite/ChangeLog:
* gnat.dg/specs/alignment2.ads: Adjust.
* gnat.dg/specs/alignment2_bis.ads: New test.
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It is needed on PowerPC platforms because of specific calling conventions.
gcc/ada/
* libgnat/g-sothco.ads (In_Addr): Add aspect Universal_Aliasing.
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Use of duplicated representation aspect is detected elsewhere
so we do not try to detect them here to avoid repetition of
messages.
gcc/ada/
* sem_prag.adb (Analyze_Pragma): Exclude detection of duplicates
because they are detected elsewhere.
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Enforce Max_Entry_Queue_Length (and its
synonym Max_Entry_Queue_Depth) when applied to individual
protected entries.
gcc/ada/
* exp_ch9.adb (Expand_N_Protected_Type_Declaration): Clarify
comments.
* sem_prag.adb (Analyze_Pragma): Check for duplicates
Max_Entry_Queue_Length, Max_Entry_Queue_Depth and Max_Queue_Length
for the same protected entry.
* sem_util.adb (Get_Max_Queue_Length): Take into account all three
representation aspects that can be used to set this restriction.
(Has_Max_Queue_Length): Likewise.
* doc/gnat_rm/implementation_defined_pragmas.rst:
(pragma Max_Queue_Length): Fix pragma in example.
* gnat_rm.texi: Regenerate.
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It has been made possible by recent changes.
gcc/ada/
* libgnat/s-finpri.ads (Collection_Node): Move to private part.
(Collection_Node_Ptr): Likewise.
(Header_Alignment): Change to declaration and move completion to
private part.
(Header_Size): Likewise.
(Lock_Type): Delete.
(Finalization_Collection): Move Lock component and remove default
value for Finalization_Started component.
* libgnat/s-finpri.adb (Initialize): Reorder statements.
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The documentation was originally centered around pragma No_Strict_Aliasing
and pragma Universal_Aliasing was mentioned only as an afterthought. It
also contained a warning about the usage of overlays implemented by means
of address clauses that has been obsolete for long.
gcc/ada/
* doc/gnat_rm/implementation_defined_pragmas.rst
(Universal_Aliasing): Remove reference to No_Strict_Aliasing.
* doc/gnat_ugn/gnat_and_program_execution.rst
(Optimization and Strict Aliasinng): Simplify first example and
make it more consistent with the second. Add description of the
effects of pragma Universal_Aliasing and document new warning
issued for unchecked conversions. Remove obsolete stuff.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.
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PR target/113955
The `-mlra` option was introduced in 2014 for MIPS, and was set to
default since then. It's time for us to drop no-lra support by
dropping -m(no-)lra options.
gcc:
* config/mips/mips.cc(mips_option_override):
Drop mips_lra_flag variable;
(mips_lra_p): Removed.
(TARGET_LRA_P): Remove definition here to use the default one.
* config/mips/mips.md(*mul_acc_si, *mul_acc_si_r3900, *mul_sub_si):
Drop mips_lra_flag variable.
* config/mips/mips.opt(-mlra): Removed.
* config/mips/mips.opt.urls(mlra): Removed.
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PR fortran/115150
gcc/fortran/ChangeLog:
* trans-intrinsic.cc (gfc_conv_intrinsic_bound): Fix SHAPE
for zero-size arrays
gcc/testsuite/ChangeLog:
* gfortran.dg/shape_12.f90: New test.
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gcc/fortran/ChangeLog:
* invoke.texi (fcoarray): Link to OpenCoarrays.org;
mention libcaf_single.
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gcc/ChangeLog:
* common/config/i386/cpuinfo.h
(get_intel_cpu): Remove Xeon Phi cpus.
(get_available_features): Remove Xeon Phi ISAs.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA_AVX512PF_SET): Removed.
(OPTION_MASK_ISA_AVX512ER_SET): Ditto.
(OPTION_MASK_ISA2_AVX5124FMAPS_SET): Ditto.
(OPTION_MASK_ISA2_AVX5124VNNIW_SET): Ditto.
(OPTION_MASK_ISA_PREFETCHWT1_SET): Ditto.
(OPTION_MASK_ISA_AVX512F_UNSET): Remove AVX512PF and AVX512ER.
(OPTION_MASK_ISA_AVX512PF_UNSET): Removed.
(OPTION_MASK_ISA_AVX512ER_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX5124FMAPS_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX5124VNNIW_UNSET): Ditto.
(OPTION_MASK_ISA_PREFETCHWT1_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX512F_UNSET): Remove AVX5124FMAPS and
AVX5125VNNIW.
(ix86_handle_option): Remove Xeon Phi options.
(processor_names): Remove Xeon Phi cpus.
(processor_alias_table): Ditto.
* common/config/i386/i386-cpuinfo.h
(enum processor_types): Ditto.
(enum processor_features): Remove Xeon Phi ISAs.
* common/config/i386/i386-isas.h: Ditto.
* config.gcc: Remove Xeon Phi cpus and ISAs.
* config/i386/avx5124fmapsintrin.h: Remove intrin support.
* config/i386/avx5124vnniwintrin.h: Ditto.
* config/i386/avx512erintrin.h: Ditto.
* config/i386/avx512pfintrin.h: Ditto.
* config/i386/cpuid.h (bit_AVX512PF): Removed.
(bit_AVX512ER): Ditto.
(bit_PREFETCHWT1): Ditto.
(bit_AVX5124VNNIW): Ditto.
(bit_AVX5124FMAPS): Ditto.
* config/i386/driver-i386.cc
(host_detect_local_cpu): Remove Xeon Phi.
* config/i386/i386-builtin-types.def: Remove unused types.
* config/i386/i386-builtin.def (BDESC): Remove builtins.
* config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins): Ditto.
* config/i386/i386-c.cc (ix86_target_macros_internal): Remove Xeon
Phi cpus and ISAs.
* config/i386/i386-expand.cc (ix86_expand_builtin): Remove Xeon Phi
related handlers.
(ix86_emit_swdivsf): Ditto.
(ix86_emit_swsqrtsf): Ditto.
* config/i386/i386-isa.def: Remove Xeon Phi ISAs.
* config/i386/i386-options.cc (m_KNL): Removed.
(m_KNM): Ditto.
(isa2_opts): Remove Xeon Phi ISAs.
(isa_opts): Ditto.
(processor_cost_table): Remove Xeon Phi cpus.
(ix86_valid_target_attribute_inner_p): Remove Xeon Phi ISAs.
(ix86_option_override_internal): Remove Xeon Phi related handlers.
* config/i386/i386-rust.cc (ix86_rust_target_cpu_info): Remove Xeon
Phi ISAs.
* config/i386/i386.cc (ix86_hard_regno_mode_ok): Remove Xeon Phi
related handler.
* config/i386/i386.h (TARGET_EMIT_VZEROUPPER): Removed.
(enum processor_type): Remove Xeon Phi cpus.
* config/i386/i386.md (prefetch): Remove PREFETCHWT1.
(*prefetch_3dnow): Ditto.
(*prefetch_prefetchwt1): Removed.
* config/i386/i386.opt: Remove Xeon Phi ISAs.
* config/i386/immintrin.h: Ditto.
* config/i386/sse.md (VF1_AVX512ER_128_256): Removed.
(rsqrt<mode>2): Change iterator from VF1_AVX512ER_128_256 to
VF1_128_256.
(GATHER_SCATTER_SF_MEM_MODE): Removed.
(avx512pf_gatherpf<mode>sf): Ditto.
(*avx512pf_gatherpf<VI48_512:mode>sf_mask): Ditto.
(avx512pf_gatherpf<mode>df): Ditto.
(*avx512pf_gatherpf<VI4_256_8_512:mode>df_mask): Ditto.
(avx512pf_scatterpf<mode>sf): Ditto.
(*avx512pf_scatterpf<VI48_512:mode>sf_mask): Ditto.
(avx512pf_scatterpf<mode>df): Ditto.
(*avx512pf_scatterpf<VI4_256_8_512:mode>df_mask): Ditto.
(exp2<mode>2): Ditto.
(avx512er_exp2<mode><mask_name><round_saeonly_name>): Ditto.
(<mask_codefor>avx512er_rcp28<mode><mask_name><round_saeonly_name>):
Ditto.
(avx512er_vmrcp28<mode><mask_name><round_saeonly_name>): Ditto.
(<mask_codefor>avx512er_rsqrt28<mode><mask_name><round_saeonly_name>):
Ditto.
(avx512er_vmrsqrt28<mode><mask_name><round_saeonly_name>): Ditto.
(IMOD4): Ditto.
(imod4_narrow): Ditto.
(mov<mode>): Ditto.
(*mov<mode>_internal): Ditto.
(avx5124fmaddps_4fmaddps): Ditto.
(avx5124fmaddps_4fmaddps_mask): Ditto.
(avx5124fmaddps_4fmaddps_maskz): Ditto.
(avx5124fmaddps_4fmaddss): Ditto.
(avx5124fmaddps_4fmaddss_mask): Ditto.
(avx5124fmaddps_4fmaddss_maskz): Ditto.
(avx5124fmaddps_4fnmaddps): Ditto.
(avx5124fmaddps_4fnmaddps_mask): Ditto.
(avx5124fmaddps_4fnmaddps_maskz): Ditto.
(avx5124fmaddps_4fnmaddss): Ditto.
(avx5124fmaddps_4fnmaddss_mask): Ditto.
(avx5124fmaddps_4fnmaddss_maskz): Ditto.
(avx5124vnniw_vp4dpwssd): Ditto.
(avx5124vnniw_vp4dpwssd_mask): Ditto.
(avx5124vnniw_vp4dpwssd_maskz): Ditto.
(avx5124vnniw_vp4dpwssds): Ditto.
(avx5124vnniw_vp4dpwssds_mask): Ditto.
(avx5124vnniw_vp4dpwssds_maskz): Ditto.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Remove Xeon Phi cpus.
(ix86_adjust_cost): Ditto.
* config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Ditto.
(X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto.
(X86_TUNE_MOVX): Ditto.
(X86_TUNE_MEMORY_MISMATCH_STALL): Ditto.
(X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto.
(X86_TUNE_FOUR_JUMP_LIMIT): Ditto.
(X86_TUNE_USE_INCDEC): Ditto.
(X86_TUNE_INTEGER_DFMODE_MOVES): Ditto.
(X86_TUNE_OPT_AGU): Ditto.
(X86_TUNE_AVOID_LEA_FOR_ADDR): Ditto.
(X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE): Ditto.
(X86_TUNE_USE_SAHF): Ditto.
(X86_TUNE_USE_CLTD): Ditto.
(X86_TUNE_USE_BT): Ditto.
(X86_TUNE_ONE_IF_CONV_INSN): Ditto.
(X86_TUNE_EXPAND_ABS): Ditto.
(X86_TUNE_USE_SIMODE_FIOP): Ditto.
(X86_TUNE_EXT_80387_CONSTANTS): Ditto.
(X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto.
(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto.
(X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS): Ditto.
(X86_TUNE_SLOW_PSHUFB): Ditto.
(X86_TUNE_EMIT_VZEROUPPER): Removed.
* config/i386/xmmintrin.h (enum _mm_hint): Remove _MM_HINT_ET1.
* doc/extend.texi: Remove Xeon Phi.
* doc/invoke.texi: Ditto.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Remove Xeon Phi ISAs.
* g++.dg/other/i386-3.C: Ditto.
* g++.target/i386/mv28.C: Ditto.
* gcc.target/i386/builtin_target.c: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/sse-26.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fmaddps-1.c: Removed.
* gcc.target/i386/avx5124fmadd-v4fmaddps-2.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fmaddss-1.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddps-1.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddps-2.c: Ditto.
* gcc.target/i386/avx5124fmadd-v4fnmaddss-1.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssd-1.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssd-2.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssds-1.c: Ditto.
* gcc.target/i386/avx5124vnniw-vp4dpwssds-2.c: Ditto.
* gcc.target/i386/avx512er-check.h: Ditto.
* gcc.target/i386/avx512er-vexp2pd-1.c: Ditto.
* gcc.target/i386/avx512er-vexp2pd-2.c: Ditto.
* gcc.target/i386/avx512er-vexp2ps-1.c: Ditto.
* gcc.target/i386/avx512er-vexp2ps-2.c: Ditto.
* gcc.target/i386/avx512er-vrcp28pd-1.c: Ditto.
* gcc.target/i386/avx512er-vrcp28pd-2.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ps-1.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ps-2.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ps-3.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ps-4.c: Ditto.
* gcc.target/i386/avx512er-vrcp28sd-1.c: Ditto.
* gcc.target/i386/avx512er-vrcp28sd-2.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ss-1.c: Ditto.
* gcc.target/i386/avx512er-vrcp28ss-2.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28pd-1.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28pd-2.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-1.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-2.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-3.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-4.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-5.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ps-6.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28sd-1.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28sd-2.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ss-1.c: Ditto.
* gcc.target/i386/avx512er-vrsqrt28ss-2.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf0dpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf0dps-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf0qpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf0qps-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf1dpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf1dps-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf1qpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vgatherpf1qps-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf0dpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf0dps-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf0qpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf0qps-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf1dpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf1dps-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf1qpd-1.c: Ditto.
* gcc.target/i386/avx512pf-vscatterpf1qps-1.c: Ditto.
* gcc.target/i386/pr104448.c: Ditto.
* gcc.target/i386/pr82941-2.c: Ditto.
* gcc.target/i386/pr82942-2.c: Ditto.
* gcc.target/i386/pr82990-1.c: Ditto.
* gcc.target/i386/pr82990-3.c: Ditto.
* gcc.target/i386/pr82990-6.c: Ditto.
* gcc.target/i386/pr82990-7.c: Ditto.
* gcc.target/i386/pr89523-5.c: Ditto.
* gcc.target/i386/pr89523-6.c: Ditto.
* gcc.target/i386/pr91033.c: Ditto.
* gcc.target/i386/prefetchwt1-1.c: Ditto.
|
|
We allowed vector type for get_stored_val when read is less than or
equal to store in previous. Unfortunately, the valididate_subreg
treats the vector type's size is less than vector register as
invalid. Then we will have ICE here.
This patch would like to fix it by filter-out the invalid type size,
and make sure the subreg is valid for both the read_mode and store_mode
before perform the real gen_lowpart.
The below test suites are passed for this patch:
* The x86 bootstrap test.
* The x86 regression test.
* The riscv rv64gcv regression test.
* The riscv rv64gc regression test.
* The aarch64 regression test.
gcc/ChangeLog:
* dse.cc (get_stored_val): Make sure read_mode/write_mode
is valid subreg before gen_lowpart.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/bug-6.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
|
|
|
|
shift-add insn
The circumstances which triggered this weren't something that should appear in
the wild (-ftree-ter, without optimization enabled). So I wasn't planning to
backport. Obviously if it shows up in another context we can revisit that
decision.
I've run this through my rv32gcv and rv64gc tester. Waiting on the CI system before committing.
PR target/115142
gcc/
* config/riscv/riscv.cc (mem_shadd_or_shadd_rtx_p): Make sure
shifted argument is a register.
gcc/testsuite
* gcc.target/riscv/pr115142.c: New test.
|
|
For Darwin, non-weak functions defined in a TU always bind locally
and so cxa_atexit-6.C is not applicable here.
PR testsuite/114982
gcc/testsuite/ChangeLog:
* g++.dg/tree-ssa/cxa_atexit-6.C: Skip for Darwin.
Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
|
|
In the current Darwin implementation, we do not use .cfi_ insns
and emitted EH frames contain 'coalesced' section designations
which interfere with the scan asm.
gcc/testsuite/ChangeLog:
* gcc.dg/darwin-weakimport-3.c: Suppress unwind frames.
Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
|
|
gcc/
* optabs-query.cc (can_mult_highpart_p): Test for the existence of
a wider mode instead of requiring it.
|
|
The result of a POPCOUNT operation in RTL should have the same mode
as its operand. This corrects the specification of popcount in
the nvptx backend, splitting the current generic define_insn into
two, one for popcountsi2 and the other for popcountdi2 (the latter
with an explicit truncate).
2024-05-19 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/nvptx/nvptx.md (popcount<mode>2): Split into...
(popcountsi2): define_insn handling SImode popcount.
(popcountdi2): define_insn handling DImode popcount, with an
explicit truncate:SI to produce an SImode result.
|
|
Some processors from T-Head don't implement the `fence.tso` instruction
natively and instead trap to firmware. This breaks some users who
haven't yet updated the firmware and one could imagine it breaking users
who are trying to build firmware if they're using the C memory model.
So just add an option to disable emitting it, in a similar fashion to
how we allow users to forbid other instructions.
Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1070959
---
I've just smoke tested this one, but
void func(void) { __atomic_thread_fence(__ATOMIC_ACQ_REL); }
generates `fence.tso` without the argument and `fence rw,rw` with
`-mno-fence-tso`, so it seems to be at least mostly there. I figured
I'd just send it up for comments before putting together the DG bits:
it's kind of a pain to carry around these workarounds for unimplemented
instructions, but it's in HW so there's not much we can do about that.
gcc/ChangeLog:
* config/riscv/riscv.opt: Add -mno-fence-tso.
* config/riscv/sync-rvwmo.md (mem_thread_fence_rvwmo): Respect
-mno-fence-tso.
* doc/invoke.texi (RISC-V): Document -mno-fence-tso.
|
|
So this is a minor fix/improvement for shift-add sequences. This was
supposed to help xz in a minor way IIRC.
Combine may present us with (x + C2') << C1 which was canonicalized from
(x << C1) + C2.
Depending on the precise values of C2 and C2' one form may be better
than the other. We can (somewhat awkwardly) use riscv_const_insns to
test for which sequence would be preferred.
Tested on Ventana's CI system as well as my own. Waiting on CI results
from Rivos's tester before moving forward.
Jeff
gcc/
* config/riscv/riscv.md: Add new patterns to allow selection
between (x << C1) + C2 vs (x + C2') << C1 depending on the
cost C2 vs C2'.
gcc/testsuite
* gcc.target/riscv/shift-add-1.c: New test.
|
|
The libgcc implementation of __clzhi2 can be tweaked by
one cycle in some situations by re-arranging the instructions.
It also reduces the WCET by 1 cycle.
libgcc/
PR target/115065
* config/avr/lib1funcs.S (__clzhi2): Tweak.
|
|
1 According to unpriv-isa spec:
<https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-221bd85-2024-05-14/unpriv-isa-asciidoc.pdf>
1.1 "FMV.H.X moves the half-precision value encoded in IEEE 754-2008
standard encoding from the lower 16 bits of integer register rs1
to the floating-point register rd, NaN-boxing the result."
1.2 "FMV.W.X moves the single-precision value encoded in IEEE 754-2008
standard encoding from the lower 32 bits of integer register rs1
to the floating-point register rd. The bits are not modified in the
transfer, and in particular, the payloads of non-canonical NaNs are preserved."
2 When (!TARGET_ZFHMIN == true && TARGET_HARD_FLOAT == true), instruction needs
to be added to complete the Nan-box, as done in
"RISC-V: Nan-box the result of movhf on soft-fp16":
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=057dc349021660c40699fb5c98fd9cac8e168653>
3 Consider the "RISC-V: Nan-box the result of movbf on soft-bf16" in:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=ce51e6727c9d69bbab0e766c449e60fd41f5f2f9>
It ignores that both hf16 and bf16 are 16bits floating-point.
4 zfbfmin -> zfhmin in:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Optimize movbf
with Nan-boxing value.
* config/riscv/riscv.md (*movhf_softfloat_boxing): Expand movbf
with Nan-boxing value.
(*mov<HFBF:mode>_softfloat_boxing): Ditto.
with Nan-boxing value.
(*movbf_softfloat_boxing): Delete abandon pattern.
|
|
According to the description in:
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367>,
the type representation symbol of BF16 has been corrected.
Kito Cheng pointed out relevant information in the email:
<https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651850.html>
gcc/ChangeLog:
* config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
Modify _Bfloat16 to __bf16.
* config/riscv/riscv.cc (riscv_mangle_type): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/_Bfloat16-nanboxing.c: Move to...
* gcc.target/riscv/__bf16-nanboxing.c: ...here.
* gcc.target/riscv/bf16_arithmetic.c: Modify _Bfloat16 to __bf16.
* gcc.target/riscv/bf16_call.c: Ditto.
* gcc.target/riscv/bf16_comparison.c: Ditto.
* gcc.target/riscv/bf16_float_libcall_convert.c: Ditto.
* gcc.target/riscv/bf16_integer_libcall_convert.c: Ditto.
|
|
The patch implement the SAT_ADD in the riscv backend as the
sample for both the scalar and vector. Given below vector
as example:
void vec_sat_add_u64 (uint64_t *out, uint64_t *x, uint64_t *y, unsigned n)
{
unsigned i;
for (i = 0; i < n; i++)
out[i] = (x[i] + y[i]) | (- (uint64_t)((uint64_t)(x[i] + y[i]) < x[i]));
}
Before this patch:
vec_sat_add_u64:
...
vsetvli a5,a3,e64,m1,ta,ma
vle64.v v0,0(a1)
vle64.v v1,0(a2)
slli a4,a5,3
sub a3,a3,a5
add a1,a1,a4
add a2,a2,a4
vadd.vv v1,v0,v1
vmsgtu.vv v0,v0,v1
vmerge.vim v1,v1,-1,v0
vse64.v v1,0(a0)
...
After this patch:
vec_sat_add_u64:
...
vsetvli a5,a3,e64,m1,ta,ma
vle64.v v1,0(a1)
vle64.v v2,0(a2)
slli a4,a5,3
sub a3,a3,a5
add a1,a1,a4
add a2,a2,a4
vsaddu.vv v1,v1,v2 <= Vector Single-Width Saturating Add
vse64.v v1,0(a0)
...
The below test suites are passed for this patch.
* The riscv fully regression tests.
* The aarch64 fully regression tests.
* The x86 bootstrap tests.
* The x86 fully regression tests.
PR target/51492
PR target/112600
gcc/ChangeLog:
* config/riscv/autovec.md (usadd<mode>3): New pattern expand for
the unsigned SAT_ADD in vector mode.
* config/riscv/riscv-protos.h (riscv_expand_usadd): New func decl
to expand usadd<mode>3 pattern.
(expand_vec_usadd): Ditto but for vector.
* config/riscv/riscv-v.cc (emit_vec_saddu): New func impl to emit
the vsadd insn.
(expand_vec_usadd): New func impl to expand usadd<mode>3 for vector.
* config/riscv/riscv.cc (riscv_expand_usadd): New func impl to
expand usadd<mode>3 for scalar.
* config/riscv/riscv.md (usadd<mode>3): New pattern expand for
the unsigned SAT_ADD in scalar mode.
* config/riscv/vector.md: Allow VLS mode for vsaddu.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary.h: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: New test.
* gcc.target/riscv/sat_arith.h: New test.
* gcc.target/riscv/sat_u_add-1.c: New test.
* gcc.target/riscv/sat_u_add-2.c: New test.
* gcc.target/riscv/sat_u_add-3.c: New test.
* gcc.target/riscv/sat_u_add-4.c: New test.
* gcc.target/riscv/sat_u_add-run-1.c: New test.
* gcc.target/riscv/sat_u_add-run-2.c: New test.
* gcc.target/riscv/sat_u_add-run-3.c: New test.
* gcc.target/riscv/sat_u_add-run-4.c: New test.
* gcc.target/riscv/scalar_sat_binary.h: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
|
|
The recent changes made to the runtime library broke its build on Solaris
because it uses Solaris threads instead of POSIX threads on this platform.
gcc/ada/
PR ada/115133
* libgnarl/s-osinte__solaris.ads (mutex_t): Fix typo.
* libgnarl/s-taprop__solaris.adb (Record_Lock): Add conversion.
(Check_Sleep): Likewise.
(Record_Wakeup): Likewise.
(Check_Unlock): Likewise.
* libgnarl/s-tasini.adb (Initialize_RTS_Lock): Add pragma Import
on the overlaid variable.
(Finalize_RTS_Lock): Likewise.
(Acquire_RTS_Lock): Likewise.
(Release_RTS_Lock): Likewise.
* libgnarl/s-taspri__solaris.ads (To_RTS_Lock_Ptr): New instance
of Ada.Unchecked_Conversion.
* libgnat/s-oslock__solaris.ads: Add with clause for
Ada.Unchecked_Conversion.
(array_type_9): Add missing name qualification.
(record_type_3): Likewise.
(mutex_t): Fix formatting.
|
|
I forgot to do this for r15-636-g770657d02c986c.
gcc/ChangeLog:
* common.opt.urls: Regenerate to add
fdiagnostics-show-event-links.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
|
|
This patch makes segment loads and stores more expensive. It adds
segment_permute_2 as well as 3 to 8 cost fields to the common vector
costs and adds handling to adjust_stmt_cost.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (struct common_vector_cost): Add
segment_permute cost.
* config/riscv/riscv-vector-costs.cc (costs::adjust_stmt_cost):
Handle segment loads/stores.
* config/riscv/riscv.cc: Initialize segment_permute_[2-8] to 1.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Adjust test.
|
|
In order to directly use constants this patch removes force_regs
in the vcond_mask expander.
gcc/ChangeLog:
PR middle-end/113474
* internal-fn.cc (expand_vec_cond_mask_optab_fn): Remove
force_regs.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr113474.c: New test.
|
|
DWARF is not especially clear on the distinction between
DW_TAG_namespace and DW_TAG_module, but I think that DW_TAG_module is
more appropriate for Ada. This patch changes the compiler to do this.
Note that the Ada compiler does not yet create NAMESPACE_DECLs.
gcc
* dwarf2out.cc (gen_namespace_die): Use DW_TAG_module for Ada.
|
|
This patch adds some ability for links between labelled ranges when
quoting the user's source code, and uses this to add links between
events when printing diagnostic_paths, chopping them up further into
event ranges that can be printed together.
It adds links to the various "from..." - "...to" events in the
analyzer.
For example, previously we emitted this for
c-c++-common/analyzer/infinite-loop-linked-list.c's
while_loop_missing_next':
infinite-loop-linked-list.c:30:10: warning: infinite loop [CWE-835] [-Wanalyzer-infinite-loop]
30 | while (n)
| ^
'while_loop_missing_next': events 1-5
30 | while (n)
| ^
| |
| (1) infinite loop here
| (2) when 'n' is non-NULL: always following 'true' branch...
| (5) ...to here
31 | {
32 | sum += n->val;
| ~~~~~~~~~~~~~
| | |
| | (3) ...to here
| (4) looping back...
whereas with the patch we now emit:
infinite-loop-linked-list.c:30:10: warning: infinite loop [CWE-835] [-Wanalyzer-infinite-loop]
30 | while (n)
| ^
'while_loop_missing_next': events 1-3
30 | while (n)
| ^
| |
| (1) infinite loop here
| (2) when 'n' is non-NULL: always following 'true' branch... ->-+
| |
| |
|+------------------------------------------------------------------------+
31 || {
32 || sum += n->val;
|| ~~~~~~
|| |
|+------------->(3) ...to here
'while_loop_missing_next': event 4
32 | sum += n->val;
| ~~~~^~~~~~~~~
| |
| (4) looping back... ->-+
| |
'while_loop_missing_next': event 5
| |
|+---------------------------------+
30 || while (n)
|| ^
|| |
|+-------->(5) ...to here
which I believe is easier to understand.
The patch also implements the use of unicode characters and colorization
for the lines (not shown in the above example).
There is a new option -fno-diagnostics-show-event-links for getting
back the old behavior (added to -fdiagnostics-plain-output).
gcc/analyzer/ChangeLog:
* checker-event.h (checker_event::connect_to_next_event_p):
Implement new diagnostic_event::connect_to_next_event_p vfunc.
(start_cfg_edge_event::connect_to_next_event_p): Likewise.
(start_consolidated_cfg_edges_event::connect_to_next_event_p):
Likewise.
* infinite-loop.cc (class looping_back_event): New subclass.
(infinite_loop_diagnostic::add_final_event): Use it.
gcc/ChangeLog:
* common.opt (fdiagnostics-show-event-links): New option.
* diagnostic-label-effects.h: New file.
* diagnostic-path.h (diagnostic_event::connect_to_next_event_p):
New pure virtual function.
(simple_diagnostic_event::connect_to_next_event_p): Implement it.
(simple_diagnostic_event::connect_to_next_event): New.
(simple_diagnostic_event::m_connected_to_next_event): New field.
(simple_diagnostic_path::connect_to_next_event): New decl.
* diagnostic-show-locus.cc: Include "text-art/theme.h" and
"diagnostic-label-effects.h".
(colorizer::set_cfg_edge): New.
(layout::m_fallback_theme): New field.
(layout::m_theme): New field.
(layout::m_effect_info): New field.
(layout::m_link_lhs_state): New enum and field.
(layout::m_link_rhs_column): New field.
(layout_range::has_in_edge): New.
(layout_range::has_out_edge): New.
(layout::layout): Add "effect_info" optional param. Initialize
m_theme, m_link_lhs_state, and m_link_rhs_column.
(layout::maybe_add_location_range): Remove stray "FIXME" from
leading comment.
(layout::print_source_line): Replace space after margin with a
call to print_leftmost_column.
(layout::print_leftmost_column): New.
(layout::start_annotation_line): Make non-const. Gain
responsibility for printing the leftmost column after the margin.
(layout::print_annotation_line): Drop pp_space, as this is now
added by start_annotation_line.
(line_label::line_label): Add "has_in_edge" and "has_out_edge"
params and initialize...
(line_label::m_has_in_edge): New field.
(line_label::m_has_out_edge): New field.
(layout::print_any_labels): Pass edge information to line_label
ctor. Keep track of in-edges and out-edges, adding visualizations
of these links between labels.
(layout::print_leading_fixits): Drop pp_character, as this is now
added by start_annotation_line.
(layout::print_trailing_fixits): Fix off-by-one errors in column
calculation.
(layout::move_to_column): Add comment about debugging.
(layout::show_ruler): Make non-const. Drop pp_space calls, as
this is now added by start_annotation_line.
(layout::print_line): Call print_any_right_to_left_edge_lines.
(layout::print_any_right_to_left_edge_lines): New.
(layout::update_any_effects): New.
(gcc_rich_location::add_location_if_nearby): Initialize
loc_range.m_label.
(diagnostic_context::maybe_show_locus): Add "effects" param and
pass it to diagnostic_context::show_locus.
(diagnostic_context::show_locus): Add "effects" param, passing it
to layout's ctor. Call update_any_effects on the layout after
printing the lines.
(selftest::test_layout_x_offset_display_utf8): Update expected
result for eliminated trailing newline.
(selftest::test_layout_x_offset_display_utf8): Likewise.
(selftest::test_layout_x_offset_display_tab): Likewise.
* diagnostic.cc (diagnostic_context::initialize): Initialize
m_source_printing.show_event_links_p.
(simple_diagnostic_path::connect_to_next_event): New.
(simple_diagnostic_event::simple_diagnostic_event): Initialize
m_connected_to_next_event.
* diagnostic.h (class diagnostic_source_effect_info): New forward
decl.
(diagnostic_source_printing_options::show_event_links_p): New
field.
(diagnostic_context::maybe_show_locus): Add optional "effect_info"
param.
(diagnostic_context::show_locus): Add "effect_info" param.
(diagnostic_show_locus): Add optional "effect_info" param.
* doc/invoke.texi: Add -fno-diagnostics-show-event-links.
* lto-wrapper.cc (merge_and_complain): Add
OPT_fdiagnostics_show_event_links to switch.
(append_compiler_options): Likewise.
(append_diag_options): Likewise.
* opts-common.cc (decode_cmdline_options_to_array): Add
"-fno-diagnostics-show-event-links" to -fdiagnostics-plain-output.
* opts.cc (common_handle_option): Add case for
OPT_fdiagnostics_show_event_links.
* text-art/theme.cc (ascii_theme::get_cppchar): Handle
cell_kind::CFG_*.
(unicode_theme::get_cppchar): Likewise.
* text-art/theme.h (theme::cell_kind): Add CFG_*.
* toplev.cc (general_init): Initialize
global_dc->m_source_printing.show_event_links_p.
* tree-diagnostic-path.cc: Define INCLUDE_ALGORITHM,
INCLUDE_MEMORY, and INCLUDE_STRING. Include
"diagnostic-label-effects.h".
(path_label::path_label): Initialize m_effects.
(path_label::get_effects): New.
(class path_label::path_label_effects): New.
(path_label::m_effects): New field.
(class per_thread_summary): Add "friend struct event_range;".
(per_thread_summary::per_thread_summary): Initialize m_last_event.
(per_thread_summary::m_last_event): New field.
(struct event_range::per_source_line_info): New.
(event_range::event_range): Make "t" non-const. Add
"show_event_links" param and use it to initialize
m_show_event_links. Add info for initial event.
(event_range::get_per_source_line_info): New.
(event_range::maybe_add_event): Verify compatibility of the new
label and existing labels with respect to the link-printing code.
Update per-source-line info when an event is added.
(event_range::print): Add"effect_info" param and pass to
diagnostic_show_locus.
(event_range::m_per_thread_summary): Make non-const.
(event_range::m_source_line_info_map): New field.
(event_range::m_show_event_links): New field.
(path_summary::path_summary): Add "show_event_links" optional
param, passing it to event_range ctor calls. Update
pts.m_last_event.
(thread_event_printer::print_swimlane_for_event_range): Add
"effect_info" param and pass it to range->print.
(print_path_summary_as_text): Keep track of the column for any
out-edges at the end of printing each event_range and use as
the leading in-edge for the next event_range.
(default_tree_diagnostic_path_printer): Pass in show_event_links_p
to path_summary ctor.
(selftest::path_events_have_column_data_p): New.
(class selftest::control_flow_test): New.
(selftest::test_control_flow_1): New.
(selftest::test_control_flow_2): New.
(selftest::test_control_flow_3): New.
(selftest::assert_cfg_edge_path_streq): New.
(ASSERT_CFG_EDGE_PATH_STREQ): New macro.
(selftest::test_control_flow_4): New.
(selftest::test_control_flow_5): New.
(selftest::test_control_flow_6): New.
(selftest::control_flow_tests): New.
(selftest::tree_diagnostic_path_cc_tests): Disable colorization on
global_dc's printer. Convert event_pp to a std::unique_ptr. Call
control_flow_tests via for_each_line_table_case.
(gen_command_line_string): Likewise.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/event-links-ascii.c: New test.
* gcc.dg/analyzer/event-links-color.c: New test.
* gcc.dg/analyzer/event-links-disabled.c: New test.
* gcc.dg/analyzer/event-links-unicode.c: New test.
libcpp/ChangeLog:
* include/rich-location.h (class label_effects): New forward decl.
(range_label::get_effects): New vfunc.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
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ChangeLog:
* MAINTAINERS: Add myself.
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Rename <sse2_avx2>_<insn><mode>3<mask_name> expander to a standard ssadd,
usadd, sssub and ussub name to enable corresponding optab expansion.
Also add named expander for MMX modes.
PR middle-end/112600
gcc/ChangeLog:
* config/i386/mmx.md (<insn><mode>3): New expander.
* config/i386/sse.md
(<sse2_avx2>_<sat_plusminus:insn><mode>3<mask_name>):
Rename expander to <sat_plusminus:insn><mode>3<mask_name>.
(<umaxmin:code><mode>3): Update for rename.
* config/i386/i386-builtin.def: Update for rename.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr112600-1a.c: New test.
* gcc.target/i386/pr112600-1b.c: New test.
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2024-05-17 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/114874
* gfortran.h: Add 'assoc_name_inferred' to gfc_namespace.
* match.cc (gfc_match_select_type): Set 'assoc_name_inferred'
in select type namespace if the selector has inferred type.
* primary.cc (gfc_match_varspec): If a select type temporary
is apparently scalar and a left parenthesis has been detected,
check the current namespace has 'assoc_name_inferred' set. If
so, set inferred_type.
* resolve.cc (resolve_variable): If the namespace of a select
type temporary is marked with 'assoc_name_inferred' call
gfc_fixup_inferred_type_refs to ensure references are OK.
(gfc_fixup_inferred_type_refs): Catch invalid array refs..
gcc/testsuite/
PR fortran/114874
* gfortran.dg/pr114874_1.f90: New test for valid code.
* gfortran.dg/pr114874_2.f90: New test for invalid code.
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If the intersection of the bitmasks made the range span the entire
domain, normalize the range to VARYING.
gcc/ChangeLog:
PR middle-end/115131
* value-range.cc (prange::intersect): Set VARYING if intersection
of bitmasks made the range span the entire domain.
(range_tests_misc): New test.
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