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2024-07-28PR modula2/116048 ICE when encountering wrong kind of qualidentGaius Mulley13-56/+645
Following on from PR-115957 further ICEs can be generated by using the wrong kind of qualident symbol. For example using a variable instead of a type or using a type instead of a const. This fix tracks the expected qualident kind state when parsing const, type and variable declarations. If the error is unrecoverable then a detailed message explaining the context of the qualident (and why the seen qualident is wrong) is generated. gcc/m2/ChangeLog: PR modula2/116048 * Make-lang.in (GM2-COMP-BOOT-DEFS): Add M2StateCheck.def. (GM2-COMP-BOOT-MODS): Add M2StateCheck.mod. (GM2-COMP-DEFS): Add M2StateCheck.def. (GM2-COMP-MODS): Add M2StateCheck.mod. * gm2-compiler/M2Quads.mod (StartBuildWith): Generate unrecoverable error is the qualident type is NulSym. Replace MetaError1 with MetaErrorT1 and position the error to the qualident. * gm2-compiler/P3Build.bnf (M2StateCheck): Import procedures. (seenError): New variable. (WasNoError): Remove variable. (BlockState): New variable. (ErrorString): Rewrite using seenError. (CompilationUnit): Ditto. (QualidentCheck): New rule. (ConstantDeclaration): Bookend with InclConst and ExclConst. (Constructor): Add InclConstructor, ExclConstructor and call CheckQualident. (ConstActualParameters): Call PushState, PopState, InclConstFunc and CheckQualident. (TypeDeclaration): Bookend with InclType and ExclType. (SimpleType): Call QualidentCheck. (CaseTag): Ditto. (OptReturnType): Ditto. (VariableDeclaration): Bookend with InclVar and ExclVar. (Designator): Call QualidentCheck. (Formal;Type): Ditto. * gm2-compiler/PCBuild.bnf (M2StateCheck): Import procedures. (ConstantDeclaration): Rewrite using InclConst and ExclConst. (Constructor): Bookend with InclConstructor and ExclConstructor. Call CheckQualident. (ConstructorOrConstActualParameters): Rewrite and cal l CheckQualident. (ConstActualParameters): Bookend with PushState PopState. Call InclConstFunc and CheckQualident. * gm2-gcc/init.cc (_M2_M2StateCheck_init): New declaration. (_M2_P3Build_init): New declaration. (init_PerCompilationInit): Call _M2_M2StateCheck_init and _M2_P3Build_init. * gm2-compiler/M2StateCheck.def: New file. * gm2-compiler/M2StateCheck.mod: New file. gcc/testsuite/ChangeLog: PR modula2/116048 * gm2/errors/fail/errors-fail.exp: Remove -Wstudents and add -Wuninit-variable-checking=all. Replace gm2_init_pim with gm2_init_iso. * gm2/errors/fail/testfio.mod: Modify test code to provoke an error in the first basic block. * gm2/errors/fail/testparam.mod: Ditto. * gm2/errors/fail/array1.mod: Ditto. * gm2/errors/fail/badtype.mod: New test. * gm2/errors/fail/badvar.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2024-07-28cp/coroutines: add a test for PR c++/103953Arsen Arsenović1-0/+75
This PR seems to have been fixed by a fix for a seemingly unrelated PR. Lets add a regression test to make sure it stays fixed. PR c++/103953 - Leak of coroutine return object PR c++/103953 gcc/testsuite/ChangeLog: * g++.dg/coroutines/torture/pr103953.C: New test. Reviewed-by: Iain Sandoe <iain@sandoe.co.uk>
2024-07-28install.texi (gcn): Suggest newer commit for NewlibTobias Burnus1-3/+3
Newlib 4.4.0 lacks two commits: 7dd4eb1db (2024-03-25) to fix device console output for GFX10/GFX11 and ed50a50b9 (2024-04-04) to make the added lock.h compilable with C++. This commit mentiones now also the second commit. gcc/ChangeLog: * doc/install.texi (amdgcn-x-amdhsa): Suggest newer git version for newlib.
2024-07-28report message for operator %a on unaddressible operandJiufu Guo3-1/+37
Hi, For PR96866, when printing asm code for modifier "%a", an addressable operand is required. While the constraint "X" allow any kind of operand even which is hard to get the address directly. e.g. extern symbol whose address is in TOC. An error message would be reported to indicate the invalid asm operand. Compare with previous version, test case is updated with -mno-pcrel. Bootstrap&regtest pass on ppc64{,le}. Is this ok for trunk? BR, Jeff(Jiufu Guo) PR target/96866 gcc/ChangeLog: * config/rs6000/rs6000.cc (print_operand_address): Emit message for unsupported operand. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr96866-1.c: New test. * gcc.target/powerpc/pr96866-2.c: New test.
2024-07-28testsuite: Disable finite math only for test [PR115826]Torbjörn SVENSSON1-0/+3
As the test case requires +-Inf and NaN to work and -ffast-math is added by default for arm-none-eabi, re-enable non-finite math. gcc/testsuite/ChangeLog: PR testsuite/115826 * gcc.dg/vect/tsvc/vect-tsvc-s1281.c: Use -fno-finite-math-only. Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
2024-07-28tree-optimization/116002 - PTA solving slow with degenerate graphRichard Biener1-0/+12
When the constraint graph consists of N nodes with only complex constraints and no copy edges we have to be lucky to arrive at a constraint solving order that requires the optimal number of iterations. What happens in the testcase is that we bottle-neck on computing the visitation order but propagate changes only very slowly. Luckily the testcase complex constraints are all copy-with-offset and those do provide a way to order visitation. The following adds this which reduces the iteration count to one. PR tree-optimization/116002 * tree-ssa-structalias.cc (topo_visit): Also consider SCALAR = SCALAR complex constraints as edges.
2024-07-28libstdc++: Use [[maybe_unused]] attribute in src/c++23/print.ccJonathan Wakely1-2/+2
This avoids some warnings when the preprocessor conditions are not met. libstdc++-v3/ChangeLog: * src/c++23/print.cc (__open_terminal): Use [[maybe_unused]] on parameter.
2024-07-28libstdc++: Do not use isatty on avr [PR115482]Detlef Vollmann1-2/+2
avrlibc has an incomplete unistd.h that doesn't have isatty. So building libstdc++ fails when compiling c++23/print.cc. As a workaround I added a check for AVR. libstdc++-v3/ChangeLog: PR libstdc++/115482 * src/c++23/print.cc (__open_terminal) [__AVR__]: Do not use isatty.
2024-07-28ssa: Fix up maybe_rewrite_mem_ref_base complex type handling [PR116034]Jakub Jelinek2-1/+26
The folding into REALPART_EXPR is correct, used only when the mem_offset is zero, but for IMAGPART_EXPR it didn't check the exact offset value (just that it is not 0). The following patch fixes that by using IMAGPART_EXPR only if the offset is right and using BITFIELD_REF or whatever else otherwise. 2024-07-23 Jakub Jelinek <jakub@redhat.com> Andrew Pinski <quic_apinski@quicinc.com> PR tree-optimization/116034 * tree-ssa.cc (maybe_rewrite_mem_ref_base): Only use IMAGPART_EXPR if MEM_REF offset is equal to element type size. * gcc.dg/pr116034.c: New test.
2024-07-28c++: Remove CHECK_CONSTRJakub Jelinek6-51/+0
On Mon, Jul 22, 2024 at 11:48:51AM -0400, Patrick Palka wrote: > FWIW this tree code seems to be a vestige of the initial Concepts TS > implementation and is effectively unused, we can remove it outright. Here is a patch which removes that. 2024-07-23 Jakub Jelinek <jakub@redhat.com> * cp-tree.def (CHECK_CONSTR): Remove. * cp-tree.h (CHECK_CONSTR_CONCEPT, CHECK_CONSTR_ARGS): Remove. * cp-objcp-common.cc (cp_common_init_ts): Don't handle CHECK_CONSTR. * tree.cc (cp_tree_equal): Likewise. * error.cc (dump_expr): Likewise. * cxx-pretty-print.cc (cxx_pretty_printer::expression): Likewise. (pp_cxx_check_constraint): Remove. (pp_cxx_constraint): Don't handle CHECK_CONSTR.
2024-07-28[v2] rtl-optimization/116002 - cselib hash is badRichard Biener1-102/+122
The following addresses the bad hash function of cselib which uses integer plus for merging. This causes a huge number of collisions for the testcase in the PR and thus very large compile-time. The following rewrites it to use inchash, eliding duplicate mixing of RTX code and mode in some cases and more consistently avoiding a return value of zero as well as treating zero as fatal. An important part is to preserve mixing of hashes of commutative operators as commutative. For cselib_hash_plus_const_int this removes the apparent attempt of making sure to hash the same as a PLUS as cselib_hash_rtx makes sure to dispatch to cselib_hash_plus_const_int consistently. This reduces compile-time for the testcase in the PR from unknown to 22s and for a reduced testcase from 73s to 9s. There's another pending patchset to improve the speed of inchash mixing, but it's not in the profile for this testcase (PTA pops up now). The generated code is equal. I've also compared cc1 builds with and without the patch and they are now commparing equal after retaining commutative hashing for commutative operators. PR rtl-optimization/116002 * cselib.cc (cselib_hash_rtx): Use inchash to get proper mixing. Consistently avoid a zero return value when hashing successfully. Consistently treat a zero hash value from recursing as fatal. Use hashval_t where appropriate. (cselib_hash_plus_const_int): Likewise. (new_cselib_val): Use hashval_t. (cselib_lookup_1): Likewise.
2024-07-28Relax ix86_hardreg_mov_ok after split1.liuhongt2-3/+13
ix86_hardreg_mov_ok is added by r11-5066-gbe39636d9f68c4 > The solution proposed here is to have the x86 backend/recog prevent > early RTL passes composing instructions (that set likely_spilled hard > registers) that they (combine) can't simplify, until after reload. > We allow sets from pseudo registers, immediate constants and memory > accesses, but anything more complicated is performed via a temporary > pseudo. Not only does this simplify things for the register allocator, > but any remaining register-to-register moves are easily cleaned up > by the late optimization passes after reload, such as peephole2 and > cprop_hardreg. The restriction is mainly for rtl optimization passes before pass_combine. But split1 splits ``` (insn 17 13 18 2 (set (reg/i:V4SI 20 xmm0) (vec_merge:V4SI (const_vector:V4SI [ (const_int -1 [0xffffffffffffffff]) repeated x4 ]) (const_vector:V4SI [ (const_int 0 [0]) repeated x4 ]) (unspec:QI [ (reg:V4SF 106) (reg:V4SF 102) (const_int 0 [0]) ] UNSPEC_PCMP))) "/app/example.cpp":20:1 2929 {*avx_cmpv4sf3_1} (expr_list:REG_DEAD (reg:V4SF 102) (expr_list:REG_DEAD (reg:V4SF 106) (nil)))) ``` into: ``` (insn 23 13 24 2 (set (reg:V4SF 107) (unspec:V4SF [ (reg:V4SF 106) (reg:V4SF 102) (const_int 0 [0]) ] UNSPEC_PCMP)) "/app/example.cpp":20:1 -1 (nil)) (insn 24 23 18 2 (set (reg/i:V4SI 20 xmm0) (subreg:V4SI (reg:V4SF 107) 0)) "/app/example.cpp":20:1 -1 (nil)) ``` There're many splitters generating MOV insn with SUBREG and would have same problem. Instead of changing those splitters one by one, the patch relaxes ix86_hard_mov_ok to allow mov subreg to hard register after split1. ix86_pre_reload_split () is used to replace !reload_completed && ira_in_progress. gcc/ChangeLog: * config/i386/i386.cc (ix86_hardreg_mov_ok): Relax mov subreg to hard register after split1. gcc/testsuite/ChangeLog: * g++.target/i386/pr115982.C: New test.
2024-07-28rs6000: Update option set in rs6000_inner_target_options [PR115713]Kewen Lin2-1/+24
When function rs6000_inner_target_options parsing target options, it updates the explicit option set information for rs6000_opt_masks by rs6000_isa_flags_explicit, but it misses to update that information for rs6000_opt_vars, and it can result in some unexpected consequence as the associated test case shows. This patch is to fix rs6000_inner_target_options to update the option set for rs6000_opt_vars as well. PR target/115713 gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_inner_target_options): Update option set information for rs6000_opt_vars. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr115713-2.c: New test.
2024-07-28rs6000: Consider explicitly set options in target option parsing [PR115713]Kewen Lin3-3/+26
In rs6000_inner_target_options, when enabling VSX we enable altivec and disable -mavoid-indexed-addresses implicitly, but it doesn't consider the case that the options altivec and avoid-indexed-addresses can be explicitly disabled. As the test case in PR115713#c1 shows, with target attribute "no-altivec,vsx", it results in that VSX unexpectedly set altivec flag and there isn't an expected error. This patch is to avoid the automatic enablement when they are explicitly specified. With this change, an existing test case ppc-target-4.c also requires an adjustment by specifying explicit altivec in target attribute (since it requires altivec feature and command line is specifying no-altivec). PR target/115713 gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_inner_target_options): Avoid to enable altivec or disable avoid-indexed-addresses automatically when they get specified explicitly. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr115713-1.c: New test. * gcc.target/powerpc/ppc-target-4.c: Adjust by specifying altivec in target attribute.
2024-07-28rs6000: Escalate warning to error for VSX with explicit no-altivec etc.Kewen Lin2-20/+24
As the discussion in PR115688, for now when users specify -mvsx and -mno-altivec explicitly, compiler emits warning rather than error, but considering both options are given explicitly, emitting hard error should be better. So this patch is to escalate some related warning to error when both are incompatible. PR target/115713 gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_option_override_internal): Emit error messages when explicit VSX encounters explicit soft-float, no-altivec or avoid-indexed-addresses. gcc/testsuite/ChangeLog: * gcc.target/powerpc/warn-1.c: Move to ... * gcc.target/powerpc/error-1.c: ... here. Adjust dg-warning with dg-error and remove ineffective scan.
2024-07-28i386: Change prefetchi output templateHaochen Jiang2-3/+3
For prefetchi instructions, RIP-relative address is explicitly mentioned for operand and assembler obeys that rule strictly. This makes instruction like: prefetchit0 bar got illegal for assembler, which should be a broad usage for prefetchi. Change to %a to explicitly add (%rip) after function label to make it legal in assembler so that it could pass to linker to get the real address. gcc/ChangeLog: * config/i386/i386.md (prefetchi): Change to %a. gcc/testsuite/ChangeLog: * gcc.target/i386/prefetchi-1.c: Check (%rip).
2024-07-28[5/n][PR rtl-optimization/115877] Fix handling of input/output operandsJeff Law1-5/+26
So in this patch we're correcting a failure to mark objects live in scenarios like (set (dest) (plus (dest) (src)) When handling set pseudos, we transfer the liveness information from LIVENOW into LIVE_TMP. LIVE_TMP is subsequently used to narrow what bit groups are live for the inputs. The first time we process the block we may not have DEST in the LIVENOW set (it may be live across the loop, but not live after the loop). Thus we can totally miss making certain objects live, resulting in incorrect code. The fix is pretty simple. If LIVE_TMP is empty, then we should go ahead and mark all the bit groups for the set object in LIVE_TMP. This also removes an invalid gcc_assert on the state of the liveness bitmaps. This showed up on pru, rl78 and/or msp430 in the testsuite. So no new test. Bootstrapped and regression tested on x86_64 and also run through my tester on all the cross platforms. Pushing to the trunk. PR rtl-optimization/115877 gcc/ * ext-dce.cc (ext_dce_process_sets): Reasonably handle input/output operands. (ext_dce_rd_transfer_n): Drop bogus assertion.
2024-07-28[powerpc] [testsuite] reorder dg directives [PR106069]Alexandre Oliva1-1/+1
The dg-do directive appears after dg-require-effective-target in g++.target/powerpc/pr106069.C. That doesn't work the way that was presumably intended. Both of these directives set dg-do-what, but dg-do does so fully and unconditionally, overriding any decisions recorded there by earlier directives. Reorder the directives more canonically, so that both take effect. for gcc/testsuite/ChangeLog PR target/106069 * g++.target/powerpc/pr106069.C: Reorder dg directives.
2024-07-28c++/coroutines: correct passing *this to promise type [PR104981]Patrick Palka3-15/+84
When passing *this to the promise type ctor (or to its operator new) (as per [dcl.fct.def.coroutine]/4), we add an explicit cast to lvalue reference. But this is unnecessary since *this is already always an lvalue. And doing so means we need to call convert_from_reference afterward to lower the reference expression to an implicit dereference, which we're currently neglecting to do and which causes overload resolution to get confused when computing argument conversions. So this patch removes this unneeded reference cast when passing *this to the promise ctor, and removes both the cast and implicit deref when passing *this to operator new, for consistency. While we're here, use cp_build_fold_indirect_ref instead of directly building INDIRECT_REF. PR c++/104981 PR c++/115550 gcc/cp/ChangeLog: * coroutines.cc (morph_fn_to_coro): Remove unneeded calls to convert_to_reference and convert_from_reference when passing *this. Use cp_build_fold_indirect_ref instead of directly building INDIRECT_REF. gcc/testsuite/ChangeLog: * g++.dg/coroutines/pr104981-preview-this.C: New test. * g++.dg/coroutines/pr115550-preview-this.C: New test. Reviewed-by: Iain Sandoe <iain@sandoe.co.uk> Reviewed-by: Jason Merrill <jason@redhat.com>
2024-07-28RISC-V: Implement the .SAT_TRUNC for scalarPan Li13-0/+259
This patch would like to implement the simple .SAT_TRUNC pattern in the riscv backend. Aka: Form 1: #define DEF_SAT_U_TRUC_FMT_1(NT, WT) \ NT __attribute__((noinline)) \ sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \ { \ bool overflow = x > (WT)(NT)(-1); \ return ((NT)x) | (NT)-overflow; \ } DEF_SAT_U_TRUC_FMT_1(uint32_t, uint64_t) Before this patch: __attribute__((noinline)) uint8_t sat_u_truc_uint16_t_to_uint8_t_fmt_1 (uint16_t x) { _Bool overflow; unsigned char _1; unsigned char _2; unsigned char _3; uint8_t _6; ;; basic block 2, loop depth 0 ;; pred: ENTRY overflow_5 = x_4(D) > 255; _1 = (unsigned char) x_4(D); _2 = (unsigned char) overflow_5; _3 = -_2; _6 = _1 | _3; return _6; ;; succ: EXIT } After this patch: __attribute__((noinline)) uint8_t sat_u_truc_uint16_t_to_uint8_t_fmt_1 (uint16_t x) { uint8_t _6; ;; basic block 2, loop depth 0 ;; pred: ENTRY _6 = .SAT_TRUNC (x_4(D)); [tail call] return _6; ;; succ: EXIT } The below tests suites are passed for this patch 1. The rv64gcv fully regression test. 2. The rv64gcv build with glibc gcc/ChangeLog: * config/riscv/iterators.md (ANYI_DOUBLE_TRUNC): Add new iterator for int double truncation. (ANYI_DOUBLE_TRUNCATED): Add new attr for int double truncation. (anyi_double_truncated): Ditto but for lowercase. * config/riscv/riscv-protos.h (riscv_expand_ustrunc): Add new func decl for expanding ustrunc * config/riscv/riscv.cc (riscv_expand_ustrunc): Add new func impl to expand ustrunc. * config/riscv/riscv.md (ustrunc<mode><anyi_double_truncated>2): Impl the new pattern ustrunc<m><n>2 for int. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add test helper macro. * gcc.target/riscv/sat_arith_data.h: New test. * gcc.target/riscv/sat_u_trunc-1.c: New test. * gcc.target/riscv/sat_u_trunc-2.c: New test. * gcc.target/riscv/sat_u_trunc-3.c: New test. * gcc.target/riscv/sat_u_trunc-run-1.c: New test. * gcc.target/riscv/sat_u_trunc-run-2.c: New test. * gcc.target/riscv/sat_u_trunc-run-3.c: New test. * gcc.target/riscv/scalar_sat_unary.h: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-07-28Daily bump.GCC Administrator5-1/+399
2024-07-28Fix handling of ICF_NOVOPS in ipa-modrefJan Hubicka1-15/+21
As shown in somewhat convoluted testcase, ipa-modref is mistreating ECF_NOVOPS as "having no side effects". This come from time when modref cared only about memory accesses and thus it was possible to shortcut on it. This patch removes (hopefully) all those bad shortcuts. Bootstrapped/regtested x86_64-linux, comitted. gcc/ChangeLog: PR ipa/109985 * ipa-modref.cc (modref_summary::useful_p): Fix handling of ECF_NOVOPS. (modref_access_analysis::process_fnspec): Likevise. (modref_access_analysis::analyze_call): Likevise. (propagate_unknown_call): Likevise. (modref_propagate_in_scc): Likevise. (modref_propagate_flags_in_scc): Likewise. (ipa_merge_modref_summary_after_inlining): Likewise.
2024-07-28c++: Some cp-tree.def comment fixesJakub Jelinek1-12/+11
While reading the fold expression and concept tree comments, I found various spots referring to non-existent macros etc. The following patch attempts to sync that with what is actually implemented. 2024-07-22 Jakub Jelinek <jakub@redhat.com> * cp-tree.def (UNARY_LEFT_FOLD_EXPR): Use FOLD_EXPR_MODIFY_P instead of FOLD_EXPR_MOD_P or FOLDEXPR_MOD_P in the comment. Comment formatting fixes. (ATOMIC_CONSTEXPR): Use CONSTR_INFO instead of ATOMIC_CONSTR_INFO and ATOMIC_CONSTR_MAP instead of ATOMIC_CONSTR_PARMS in the comment. Comment formatting fixes. (CONJ_CONSTR): Remove comment about third operand. Use CONSTR_INFO instead of CONJ_CONSTR_INFO and DISJ_CONSTR_INFO. (CHECK_CONSTR): Use CHECK_CONSTR_ARGS instead of CHECK_CONSTR_ARGUMENTS.
2024-07-28Fix modref's iteraction with store mergingJan Hubicka2-0/+32
Hi, this patch fixes wrong code in case store-merging introduces load of function parameter that was previously write-only (which happens for bitfields). Without this, the whole store-merged area is consdered to be killed. PR ipa/111613 gcc/ChangeLog: * ipa-modref.cc (analyze_parms): Do not preserve EAF_NO_DIRECT_READ and EAF_NO_INDIRECT_READ from past flags. gcc/testsuite/ChangeLog: * gcc.c-torture/pr111613.c: New test.
2024-07-28Add -mcpu=power11 support.Michael Meissner21-90/+171
This patch adds the power11 option to the -mcpu= and -mtune= switches. This patch treats the power11 like a power10 in terms of costs and reassociation width. This patch issues a ".machine power11" to the assembly file if you use -mcpu=power11. This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. This patch allows GCC to be configured with the --with-cpu=power11 and --with-tune=power11 options. This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. This patch adds support for using "power11" in the __builtin_cpu_is built-in function. 2024-07-22 Michael Meissner <meissner@linux.ibm.com> gcc/ * config.gcc (powerpc*-*-*): Add support for power11. * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/driver-rs6000.cc (asm_names): Likewise. * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define. * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define _ARCH_PWR11 if -mcpu=power11. * config/rs6000/rs6000-cpus.def (POWER11_MASKS_SERVER): New define. (POWERPC_MASKS): Add power11. (power11 cpu): Add power11 definition. * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11 support. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power11. * config/rs6000/rs6000.opt (-mpower11): Add internal power11 flag. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. * config/rs6000/power10.md (all reservations): Add power11 support. gcc/testsuite/ * gcc.target/powerpc/power11-1.c: New test. * gcc.target/powerpc/power11-2.c: Likewise. * gcc.target/powerpc/power11-3.c: Likewise.
2024-07-28[4/n][PR rtl-optimization/115877] Correct SUBREG handling in a destinationJeff Law1-3/+10
If we encounter something during SET handling that we can not handle, the safe thing to do is to ignore the destination and continue the loop. We've actually been trying to do slightly better with SUBREG destinations by iterating into SUBREG_REG. It turns out that wasn't working as expected. The problem is once we "continue" we lose the state that we were inside the SET and thus we ended up ignoring the destination completely rather than tracking the SUBREG_REG object. This could be fixed by restarting SET processing, but I just don't see this as all that important to handle. So rather than leave the code as-is, not working per design, I'm twiddling it to use the common 'skip subrtxs and continue' idiom used elsewhere. This is a prerequisite for another patch in this series. Specifically I have a patch that explicitly tracks if we skipped a destination rather than trying to imply it from the state of LIVE_TMP. So this is probably NFC right now, but that's a short-lived NFC. Bootstrapped and regression tested on x86 and also run as part of a larger kit on the crosses in my tester. PR rtl-optimization/115877 gcc/ * ext-dce.cc (ext_dce_process_sets): More correctly handle SUBREG destinations.
2024-07-28Fix modref_eaf_analysis::analyze_ssa_name handling of values dereferenced to ↵Jan Hubicka2-2/+39
function call parameters modref_eaf_analysis::analyze_ssa_name misinterprets EAF flags. If dereferenced parameter is passed (to map_iterator in the testcase) it can be returned indirectly which in turn makes it to escape into the next function call. PR ipa/115033 gcc/ChangeLog: * ipa-modref.cc (modref_eaf_analysis::analyze_ssa_name): Fix checking of EAF flags when analysing values dereferenced as function parameters. gcc/testsuite/ChangeLog: * gcc.c-torture/execute/pr115033.c: New test.
2024-07-28Fix accounting of offsets in unadjusted_ptr_and_unit_offsetJan Hubicka2-2/+25
unadjusted_ptr_and_unit_offset accidentally throws away the offset computed by get_addr_base_and_unit_offset. Instead of passing extra_offset it passes offset. PR ipa/114207 gcc/ChangeLog: * ipa-prop.cc (unadjusted_ptr_and_unit_offset): Fix accounting of offsets in ADDR_EXPR. gcc/testsuite/ChangeLog: * gcc.c-torture/execute/pr114207.c: New test.
2024-07-28Compare loop bounds in ipa-icfJan Hubicka2-0/+32
Hi, this testcase shows another poblem with missing comparators for metadata in ICF. With value ranges available to loop optimizations during early opts we can estimate number of iterations based on guarding condition that can be split away by the fnsplit pass. This patch disables ICF when number of iteraitons does not match. Bootstrapped/regtesed x86_64-linux, will commit it shortly gcc/ChangeLog: PR ipa/115277 * ipa-icf-gimple.cc (func_checker::compare_loops): compare loop bounds. gcc/testsuite/ChangeLog: * gcc.c-torture/compile/pr115277.c: New test.
2024-07-28rtl-ssa: Avoid using a stale splay tree root [PR116009]Richard Sandiford2-1/+25
In the fix for PR115928, I'd failed to notice that "root" was used later in the function, so needed to be updated. gcc/ PR rtl-optimization/116009 * rtl-ssa/accesses.cc (function_info::add_def): Set the root local variable after removing the old clobber group. gcc/testsuite/ PR rtl-optimization/116009 * gcc.c-torture/compile/pr116009.c: New test.
2024-07-28rtl-ssa: Add debug routines for def_splay_treeRichard Sandiford2-0/+18
This patch adds debug routines for def_splay_tree, which I found useful while debugging PR116009. gcc/ * rtl-ssa/accesses.h (rtl_ssa::pp_def_splay_tree): Declare. (dump, debug): Add overloads for def_splay_tree. * rtl-ssa/accesses.cc (rtl_ssa::pp_def_splay_tree): New function. (dump, debug): Add overloads for def_splay_tree.
2024-07-28aarch64: Tighten aarch64_simd_mem_operand_p [PR115969]Richard Sandiford2-2/+11
aarch64_simd_mem_operand_p checked for a memory with a POST_INC or REG address, but it didn't check what kind of register was being used. This meant that it allowed DImode FPRs as well as GPRs. I wondered about rewriting it to use aarch64_classify_address, but this one-line fix seemed simpler. The structure then mirrors the existing early exit in aarch64_classify_address itself: /* On LE, for AdvSIMD, don't support anything other than POST_INC or REG addressing. */ if (advsimd_struct_p && TARGET_SIMD && !BYTES_BIG_ENDIAN && (code != POST_INC && code != REG)) return false; gcc/ PR target/115969 * config/aarch64/aarch64.cc (aarch64_simd_mem_operand_p): Require the operand to be a legitimate memory_operand. gcc/testsuite/ PR target/115969 * gcc.target/aarch64/pr115969.c: New test.
2024-07-28[NFC][PR rtl-optimization/115877] Avoid setting irrelevant bit groups as ↵Jeff Law1-7/+57
live in ext-dce Another patch to refine liveness computations. This should be NFC and is designed to help debugging. In simplest terms the patch avoids setting bit groups outside the size of a pseudo as live. Consider a HImode pseudo, bits 16..63 for such a pseudo don't really have meaning, yet we often set bit groups related to bits 16.63 on in the liveness bitmaps. This makes debugging harder than it needs to be by simply having larger bitmaps to verify when walking through the code in a debugger. This has been bootstrapped and regression tested on x86_64. It's also been tested on the crosses in my tester without regressions. Pushing to the trunk, PR rtl-optimization/115877 gcc/ * ext-dce.cc (group_limit): New function. (mark_reg_live): Likewise. (ext_dce_process_sets): Use new functions. (ext_dce_process_uses): Likewise. (ext_dce_init): Likewise.
2024-07-28Fix hash of WIDEN_*_EXPRRichard Biener1-1/+1
We're hashing operand 2 to the temporary hash. * fold-const.cc (operand_compare::hash_operand): Fix hash of WIDEN_*_EXPR.
2024-07-28constify inchashRichard Biener1-3/+3
The following constifies parts of inchash. * inchash.h (inchash::end): Make const. (inchash::merge): Take const reference hash argument. (inchash::add_commutative): Likewise.
2024-07-28Fix Rejects allocatable coarray passed as a dummy argument [88624]Andre Vehreschild3-10/+48
Coarray parameters of procedures/functions need to be dereffed, because they are references to the descriptor but the routine expected the descriptor directly. PR fortran/88624 gcc/fortran/ChangeLog: * trans-expr.cc (gfc_conv_procedure_call): Treat pointers/references (e.g. from parameters) correctly by derefing them. gcc/testsuite/ChangeLog: * gfortran.dg/coarray/dummy_1.f90: Add calling function trough function. * gfortran.dg/pr88624.f90: New test.
2024-07-28AArch64: implement TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE ↵Tamar Christina5-0/+112
[PR115531]. This implements the new target hook indicating that for AArch64 when possible we prefer masked operations for any type vs doing LOAD + SELECT or SELECT + STORE. Thanks, Tamar gcc/ChangeLog: PR tree-optimization/115531 * config/aarch64/aarch64.cc (aarch64_conditional_operation_is_expensive): New. (TARGET_VECTORIZE_CONDITIONAL_OPERATION_IS_EXPENSIVE): New. gcc/testsuite/ChangeLog: PR tree-optimization/115531 * gcc.dg/vect/vect-conditional_store_1.c: New test. * gcc.dg/vect/vect-conditional_store_2.c: New test. * gcc.dg/vect/vect-conditional_store_3.c: New test. * gcc.dg/vect/vect-conditional_store_4.c: New test.
2024-07-28middle-end: Implement conditonal store vectorizer pattern [PR115531]Tamar Christina6-0/+189
This adds a conditional store optimization for the vectorizer as a pattern. The vectorizer already supports modifying memory accesses because of the pattern based gather/scatter recognition. Doing it in the vectorizer allows us to still keep the ability to vectorize such loops for architectures that don't have MASK_STORE support, whereas doing this in ifcvt makes us commit to MASK_STORE. Concretely for this loop: void foo1 (char *restrict a, int *restrict b, int *restrict c, int n, int stride) { if (stride <= 1) return; for (int i = 0; i < n; i++) { int res = c[i]; int t = b[i+stride]; if (a[i] != 0) res = t; c[i] = res; } } today we generate: .L3: ld1b z29.s, p7/z, [x0, x5] ld1w z31.s, p7/z, [x2, x5, lsl 2] ld1w z30.s, p7/z, [x1, x5, lsl 2] cmpne p15.b, p6/z, z29.b, #0 sel z30.s, p15, z30.s, z31.s st1w z30.s, p7, [x2, x5, lsl 2] add x5, x5, x4 whilelo p7.s, w5, w3 b.any .L3 which in gimple is: vect_res_18.9_68 = .MASK_LOAD (vectp_c.7_65, 32B, loop_mask_67); vect_t_20.12_74 = .MASK_LOAD (vectp.10_72, 32B, loop_mask_67); vect__9.15_77 = .MASK_LOAD (vectp_a.13_75, 8B, loop_mask_67); mask__34.16_79 = vect__9.15_77 != { 0, ... }; vect_res_11.17_80 = VEC_COND_EXPR <mask__34.16_79, vect_t_20.12_74, vect_res_18.9_68>; .MASK_STORE (vectp_c.18_81, 32B, loop_mask_67, vect_res_11.17_80); A MASK_STORE is already conditional, so there's no need to perform the load of the old values and the VEC_COND_EXPR. This patch makes it so we generate: vect_res_18.9_68 = .MASK_LOAD (vectp_c.7_65, 32B, loop_mask_67); vect__9.15_77 = .MASK_LOAD (vectp_a.13_75, 8B, loop_mask_67); mask__34.16_79 = vect__9.15_77 != { 0, ... }; .MASK_STORE (vectp_c.18_81, 32B, mask__34.16_79, vect_res_18.9_68); which generates: .L3: ld1b z30.s, p7/z, [x0, x5] ld1w z31.s, p7/z, [x1, x5, lsl 2] cmpne p7.b, p7/z, z30.b, #0 st1w z31.s, p7, [x2, x5, lsl 2] add x5, x5, x4 whilelo p7.s, w5, w3 b.any .L3 gcc/ChangeLog: PR tree-optimization/115531 * tree-vect-patterns.cc (vect_cond_store_pattern_same_ref): New. (vect_recog_cond_store_pattern): New. (vect_vect_recog_func_ptrs): Use it. * target.def (conditional_operation_is_expensive): New. * doc/tm.texi: Regenerate. * doc/tm.texi.in: Document it. * targhooks.cc (default_conditional_operation_is_expensive): New. * targhooks.h (default_conditional_operation_is_expensive): New.
2024-07-28testsuite: powerpc: fix dg-do run typoSam James1-1/+1
'dg-run' is not a valid dejagnu directive, 'dg-do run' is needed here for the test to be executed. PR target/108699 gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr108699.c: Fix 'dg-run' typo. Signed-off-by: Sam James <sam@gentoo.org>
2024-07-28RISC-V: Rearrange the test helper files for vector .SAT_*Pan Li184-262/+262
Rearrange the test help header files, as well as align the name conventions. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary.h: Move to... * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvv_run.h: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_scalar.h: Move to... * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vvx_run.h: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h: Move to... * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx_run.h: ...here. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust the include file names. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-1.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-2.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-3.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-4.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-5.c: Ditto * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-run-6.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Move to... * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: ...here. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-07-28Daily bump.GCC Administrator5-1/+45
2024-07-28Fortran: Fix regression caused by r14-10477 [PR59104]Paul Thomas4-1/+36
2024-07-21 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/59104 * gfortran.h : Add decl_order to gfc_symbol. * symbol.cc : Add static next_decl_order.. (gfc_set_sym_referenced): Set symbol decl_order. * trans-decl.cc : Include dependency.h. (decl_order): Replace symbol declared_at.lb->location with decl_order. gcc/testsuite/ PR fortran/59104 * gfortran.dg/dependent_decls_3.f90: New test.
2024-07-28[PR rtl-optimization/115877][2/n] Improve liveness computation for constant ↵Jeff Law1-0/+1
initialization While debugging pr115877, I noticed we were failing to remove the destination register from LIVENOW bitmap when it was set to a constant value. ie (set (dest) (const_int)). This was a trivial oversight in safe_for_live_propagation. I don't have an example of this affecting code generation, but it certainly could. More importantly, by making LIVENOW more accurate it's easier to debug when LIVENOW differs from expectations. As with the prior patch this has been tested as part of a larger patchset with the crosses as well as individually on x86_64. Pushing to the trunk, PR rtl-optimization/115877 gcc/ * ext-dce.cc (safe_for_live_propagation): Handle RTX_CONST_OBJ.
2024-07-28[PR rtl-optimization/115877] Fix livein computation for ext-dceJeff Law1-0/+2
So I'm not yet sure how I'm going to break everything down, but this is easy enough to break out as 1/N of ext-dce fixes/improvements. When handling uses in an insn, we first determine what bits are set in the destination which is represented in DST_MASK. Then we use that to refine what bits are live in the source operands. In the source operand handling section we *modify* DST_MASK if the source operand is a SUBREG (ugh!). So if the first operand is a SUBREG, then we can incorrectly compute which bit groups are live in the second operand, especially if it is a SUBREG as well. This was seen when testing a larger set of patches on the rl78 port (builtin-arith-overflow-p-7 & pr71631 execution failures), so no new test for this bugfix. Run through my tester (in conjunction with other ext-dce changes) on the various cross targets. Run individually through a bootstrap and regression test cycle on x86_64 as well. Pushing to the trunk. PR rtl-optimization/115877 gcc/ * ext-dce.cc (ext_dce_process_uses): Restore the value of DST_MASK for reach operand.
2024-07-28gcc: stop adding -fno-common for checking buildsSam James4-16/+5
Originally added in r0-44646-g204250d2fcd084 and r0-44627-gfd350d241fecf6 whic moved -fno-common from all builds to just checking builds. Since r10-4867-g6271dd984d7f92, GCC defaults to -fno-common. There's no need to pass it specially for checking builds. We could keep it for older bootstrap compilers with checking but I don't see much value in that, it was already just a bonus before. gcc/ChangeLog: * Makefile.in (NOCOMMON_FLAG): Delete. (GCC_WARN_CFLAGS): Drop NOCOMMON_FLAG. (GCC_WARN_CXXFLAGS): Drop NOCOMMON_FLAG. * configure.ac: Ditto. * configure: Regenerate. gcc/d/ChangeLog: * Make-lang.in (WARN_DFLAGS): Drop NOCOMMON_FLAG.
2024-07-24Got some basic arithmetic working, test case now run-time.Thomas Koenig8-30/+97
2024-07-22Very first program compiles.Thomas Koenig12-1/+223
2024-07-21Initial version - add do-nothing -funsigned option and BT_UNSIGNED.Thomas Koenig4-0/+15
2024-07-21SH: Fix outage caused by recently added 2nd combine pass after reg allocOleg Endo1-1/+9
I've also confirmed on the CSiBE set that the secondary combine pass is actually beneficial on SH. It does result in some code size reductions. gcc/CHangeLog: * config/sh/sh.md (mov_neg_si_t): Allow insn and split after register allocation. (*treg_noop_move): New insn.
2024-07-21Daily bump.GCC Administrator6-1/+179
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