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2024-06-17c-family: Fix -Warray-compare warning ICE [PR115290]Jakub Jelinek2-4/+22
The warning code uses %D to print the ARRAY_REF first operands. That works in the most common case where those operands are decls, but as can be seen on the following testcase, they can be other expressions with array type. Just changing %D to %E isn't enough, because then the diagnostics can suggest something like note: use '&(x) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0] == &(y) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0]' to compare the addresses which is a bad suggestion, the %E printing doesn't know that the warning code will want to add & before it and [0] after it. So, the following patch adds ()s around the operand as well, but does that only for non-decls, for decls keeps it as &arr[0] like before. 2024-06-17 Jakub Jelinek <jakub@redhat.com> PR c/115290 * c-warn.cc (do_warn_array_compare): Use %E rather than %D for printing op0 and op1; if those operands aren't decls, also print parens around them. * c-c++-common/Warray-compare-3.c: New test.
2024-06-17c++: Fix up floating point conversion rank comparison for _Float32 and float ↵Jakub Jelinek2-0/+29
if float/double are same size [PR115511] On AVR and SH with some options sizeof (float) == sizeof (double) and the 2 types have the same set of values. http://eel.is/c++draft/conv.rank#2.2 for this says that double still has bigger rank than float and http://eel.is/c++draft/conv.rank#2.2 says that extended type with the same set of values as more than one standard floating point type shall have the same rank as double. I've implemented the latter rule as if (cnt > 1 && mv2 == long_double_type_node) return -2; with the _Float64/double/long double case having same mode case (various targets with -mlong-double-64) in mind. But never thought there are actually targets where float and double are the same, that needs handling too, if cnt > 1 (that is the extended type mv1 has same set of values as 2 or 3 of float/double/long double) and mv2 is float, we need to return 2, because mv1 in that case should have same rank as double and double has bigger rank than float. 2024-06-17 Jakub Jelinek <jakub@redhat.com> PR target/111343 PR c++/115511 * typeck.cc (cp_compare_floating_point_conversion_ranks): If an extended floating point type mv1 has same set of values as more than one standard floating point type and mv2 is float, return 2. * g++.dg/cpp23/ext-floating18.C: New test.
2024-06-17RISC-V: Add configure check for Zaamo/Zalrsc assembler supportPatrick O'Neill4-0/+53
Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure check to prevent emitting Zaamo/Zalrsc in the arch string when the assember does not support it. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): Skip zaamo/zalrsc when not supported by the assembler. * config.in: Regenerate. * configure: Regenerate. * configure.ac: Add zaamo/zalrsc assmeber check. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> # RISC-V Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # RISC-V
2024-06-17doc: Mark up __cxa_atexit as @code.Gerald Pfeifer1-4/+4
gcc: * doc/install.texi (Configuration): Mark up __cxa_atexit as @code.
2024-06-17rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]Peter Bergner2-5/+21
We currently only compute the offset for the ROP hash save location in the stack frame for Altivec compiles. For non-Altivec compiles when we emit ROP mitigation instructions, we use a default offset of zero which corresponds to the backchain save location which will get clobbered on any call. The fix is to compute the ROP hash save location for all compiles. 2024-06-14 Peter Bergner <bergner@linux.ibm.com> gcc/ PR target/115389 * config/rs6000/rs6000-logue.cc (rs6000_stack_info): Compute rop_hash_save_offset for non-Altivec compiles. gcc/testsuite PR target/115389 * gcc.target/powerpc/pr115389.c: New test.
2024-06-17[to-be-committed,RISC-V] Improve variable bit set for rv64Jeff Law2-0/+24
Another case of being able to safely use bset for 1 << n. In this case the (1 << n) is explicitly zero extended from SI to DI. Two things to keep in mind. The (1 << n) is done in SImode. So it doesn't directly define bits 32..63 and those bits are cleared by the explicit zero extension. Second if N is out of SImode's range, then the original source level construct was undefined. Thus we can use bset with x0 as our source input. I think this testcase was from the RAU team. It doesn't immediately look like something from SPEC, but that's where they were primarily focused. This has been through Ventana's CI system in the past. I've also recently added zbs testing to my own tester and naturally this passed there as well. I'll wait for the pre-commit CI to do its thing before moving forward. The plan would be to commit after passing. gcc/ * config/riscv/bitmanip.md (bsetdi_2): New pattern. gcc/testsuite/ * gcc.target/riscv/zbs-zext-2.c: New test.
2024-06-17tree-optimization/115508 - fix ICE with SLP scheduling and extern vectorRichard Biener2-0/+16
When there's a permute after an extern vector we can run into a case that didn't consider the scheduled node being a permute which lacks a representative. PR tree-optimization/115508 * tree-vect-slp.cc (vect_schedule_slp_node): Guard check on representative. * gcc.target/i386/pr115508.c: New testcase.
2024-06-17Testcase for PR115492Richard Biener1-0/+19
This adds a testcase for the PR fixed with reversal of r15-204-g7c469a9fc78550. PR tree-optimization/115492 * gcc.dg/torture/pr115492.c: New testcase.
2024-06-17Revert "tree-optimization/100923 - re-do VN with contextual PTA info fix"Richard Biener1-25/+33
This reverts commit 7c469a9fc785505dc350aba60311812c2bb0c1b5.
2024-06-17Rename Value_Range to value_range.Aldy Hernandez33-241/+241
Now that all remaining users of value_range have been renamed to int_range<>, we can reclaim value_range as a temporary, thus removing the annoying CamelCase. gcc/ChangeLog: * data-streamer-in.cc (streamer_read_value_range): Rename Value_Range to value_range. * data-streamer.h (streamer_read_value_range): Same. * gimple-pretty-print.cc (dump_ssaname_info): Same. * gimple-range-cache.cc (ssa_block_ranges::dump): Same. (ssa_lazy_cache::merge): Same. (block_range_cache::dump): Same. (ssa_cache::merge_range): Same. (ssa_cache::dump): Same. (ranger_cache::edge_range): Same. (ranger_cache::propagate_cache): Same. (ranger_cache::fill_block_cache): Same. (ranger_cache::resolve_dom): Same. (ranger_cache::range_from_dom): Same. (ranger_cache::register_inferred_value): Same. * gimple-range-fold.cc (op1_range): Same. (op2_range): Same. (fold_relations): Same. (fold_using_range::range_of_range_op): Same. (fold_using_range::range_of_phi): Same. (fold_using_range::range_of_call): Same. (fold_using_range::condexpr_adjust): Same. (fold_using_range::range_of_cond_expr): Same. (fur_source::register_outgoing_edges): Same. * gimple-range-fold.h (gimple_range_type): Same. (gimple_range_ssa_p): Same. * gimple-range-gori.cc (gori_compute::compute_operand_range): Same. (gori_compute::logical_combine): Same. (gori_compute::refine_using_relation): Same. (gori_compute::compute_operand1_range): Same. (gori_compute::compute_operand2_range): Same. (gori_compute::compute_operand1_and_operand2_range): Same. (gori_calc_operands): Same. (gori_name_helper): Same. * gimple-range-infer.cc (gimple_infer_range::check_assume_func): Same. (gimple_infer_range::gimple_infer_range): Same. (infer_range_manager::maybe_adjust_range): Same. (infer_range_manager::add_range): Same. * gimple-range-infer.h: Same. * gimple-range-op.cc (gimple_range_op_handler::gimple_range_op_handler): Same. (gimple_range_op_handler::calc_op1): Same. (gimple_range_op_handler::calc_op2): Same. (gimple_range_op_handler::maybe_builtin_call): Same. * gimple-range-path.cc (path_range_query::internal_range_of_expr): Same. (path_range_query::ssa_range_in_phi): Same. (path_range_query::compute_ranges_in_phis): Same. (path_range_query::compute_ranges_in_block): Same. (path_range_query::add_to_exit_dependencies): Same. * gimple-range-trace.cc (debug_seed_ranger): Same. * gimple-range.cc (gimple_ranger::range_of_expr): Same. (gimple_ranger::range_on_entry): Same. (gimple_ranger::range_on_edge): Same. (gimple_ranger::range_of_stmt): Same. (gimple_ranger::prefill_stmt_dependencies): Same. (gimple_ranger::register_inferred_ranges): Same. (gimple_ranger::register_transitive_inferred_ranges): Same. (gimple_ranger::export_global_ranges): Same. (gimple_ranger::dump_bb): Same. (assume_query::calculate_op): Same. (assume_query::calculate_phi): Same. (assume_query::dump): Same. (dom_ranger::range_of_stmt): Same. * ipa-cp.cc (ipcp_vr_lattice::meet_with_1): Same. (ipa_vr_operation_and_type_effects): Same. (ipa_value_range_from_jfunc): Same. (propagate_bits_across_jump_function): Same. (propagate_vr_across_jump_function): Same. (ipcp_store_vr_results): Same. * ipa-cp.h: Same. * ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same. (evaluate_properties_for_edge): Same. * ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Same. (ipa_vr::get_vrange): Same. (ipa_vr::streamer_read): Same. (ipa_vr::streamer_write): Same. (ipa_vr::dump): Same. (ipa_set_jfunc_vr): Same. (ipa_compute_jump_functions_for_edge): Same. (ipcp_get_parm_bits): Same. (ipcp_update_vr): Same. (ipa_record_return_value_range): Same. (ipa_return_value_range): Same. * ipa-prop.h (ipa_return_value_range): Same. (ipa_record_return_value_range): Same. * range-op.h (range_cast): Same. * tree-ssa-dom.cc (dom_opt_dom_walker::set_global_ranges_from_unreachable_edges): Same. (cprop_operand): Same. * tree-ssa-loop-ch.cc (loop_static_stmt_p): Same. * tree-ssa-loop-niter.cc (record_nonwrapping_iv): Same. * tree-ssa-loop-split.cc (split_at_bb_p): Same. * tree-ssa-phiopt.cc (value_replacement): Same. * tree-ssa-strlen.cc (get_range): Same. * tree-ssa-threadedge.cc (hybrid_jt_simplifier::simplify): Same. (hybrid_jt_simplifier::compute_exit_dependencies): Same. * tree-ssanames.cc (set_range_info): Same. (duplicate_ssa_name_range_info): Same. * tree-vrp.cc (remove_unreachable::handle_early): Same. (remove_unreachable::remove_and_update_globals): Same. (execute_ranger_vrp): Same. * value-query.cc (range_query::value_of_expr): Same. (range_query::value_on_edge): Same. (range_query::value_of_stmt): Same. (range_query::value_on_entry): Same. (range_query::value_on_exit): Same. (range_query::get_tree_range): Same. * value-range-storage.cc (vrange_storage::set_vrange): Same. * value-range.cc (Value_Range::dump): Same. (value_range::dump): Same. (debug): Same. * value-range.h (enum value_range_discriminator): Same. (class vrange): Same. (class Value_Range): Same. (class value_range): Same. (Value_Range::Value_Range): Same. (value_range::value_range): Same. (Value_Range::~Value_Range): Same. (value_range::~value_range): Same. (Value_Range::set_type): Same. (value_range::set_type): Same. (Value_Range::init): Same. (value_range::init): Same. (Value_Range::operator=): Same. (value_range::operator=): Same. (Value_Range::operator==): Same. (value_range::operator==): Same. (Value_Range::operator!=): Same. (value_range::operator!=): Same. (Value_Range::supports_type_p): Same. (value_range::supports_type_p): Same. * vr-values.cc (simplify_using_ranges::fold_cond_with_ops): Same. (simplify_using_ranges::legacy_fold_cond): Same.
2024-06-17[APX ZU] Fix test for target-support checkLingling Kong2-0/+9
gcc/testsuite/ChangeLog: * gcc.target/i386/apx-zu-1.c: Add attribute for noinline, and target apx. * gcc.target/i386/apx-zu-2.c: Add target-support check.
2024-06-17i386: Refine all cvtt* instructions with UNSPEC instead of FIX/UNSIGNED_FIX.Hu, Lin13-64/+464
gcc/ChangeLog: PR target/115161 * config/i386/i386-builtin.def: Change CODE_FOR_* for cvtt*'s builtins. * config/i386/sse.md: (unspec_avx512fp16_fix<vcvtt_uns_suffix> _trunc<mode>2<mask_name><round_saeonly_name>): Use UNSPEC instead of FIX/UNSIGNED_FIX. (unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<mask_name>): Ditto. (unspec_avx512fp16_fix<vcvtt_uns_suffix>_truncv2di2<mask_name>): Ditto. (unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<round_saeonly_name>): Ditto. (unspec_sse_cvttps2pi): Ditto. (unspec_sse_cvttss2si<rex64namesuffix><round_saeonly_name>): Ditto. (unspec_fix<vcvtt_uns_suffix>_truncv16sfv16si2<mask_name><round_saeonly_name>): Ditto. (unspec_fix_truncv8sfv8si2<mask_name>): Ditto. (unspec_fix_truncv4sfv4si2<mask_name>): Ditto. (unspec_sse2_cvttpd2pi): Ditto. (unspec_fixuns_truncv2dfv2si2): Ditto. (unspec_avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>): Ditto. (unspec_avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>): Ditto. (unspec_sse2_cvttsd2si<rex64namesuffix><round_saeonly_name>): Ditto. (unspec_fix<vcvtt_uns_suffix>_truncv8dfv8si2<mask_name><round_saeonly_name>): Ditto. (*unspec_fixuns_truncv2dfv2si2): Ditto. (unspec_fixuns_truncv2dfv2si2_mask): Ditto. (unspec_fix_truncv4dfv4si2<mask_name>): Ditto. (unspec_fixuns_truncv4dfv4si2<mask_name>): Ditto. (unspec_fix<vcvtt_uns_suffix> _trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>): Ditto. (unspec_fix<vcvtt_uns_suffix> _trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>): Ditto. (unspec_avx512dq_fix<vcvtt_uns_suffix>_truncv2sfv2di2<mask_name>): Ditto. (<mask_codefor>unspec_fixuns_trunc<mode><sseintvecmodelower>2<mask_name>): Ditto. (unspec_sse2_cvttpd2dq<mask_name>): Ditto. gcc/testsuite/ChangeLog: PR target/115161 * gcc.target/i386/pr115161-1.c: New test.
2024-06-17Fix ICE when compiling with -fcoarray=single, when derefing a non-array.Andre Vehreschild3-4/+4
PR fortran/96418 PR fortran/103112 gcc/fortran/ChangeLog: * trans.cc (gfc_deallocate_with_status): Check that object to deref is an array, before applying array deref. gcc/testsuite/ChangeLog: * gfortran.dg/coarray_alloc_comp_3.f08: Moved to... * gfortran.dg/coarray/alloc_comp_8.f90: ...here. Should be tested for both -fcoarray=single and lib, resp. * gfortran.dg/coarray_alloc_comp_4.f08: Fix program name.
2024-06-17x86: Emit cvtne2ps2bf16 for odd increasing perm in __builtin_shufflevectorLevy Hsu4-2/+75
This patch updates the GCC x86 backend to efficiently handle odd, incrementally increasing permutations of BF16 vectors using the cvtne2ps2bf16 instruction. It modifies ix86_vectorize_vec_perm_const to support these operations and adds a specific predicate to ensure proper sequence handling. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_vectorize_vec_perm_const): Convert BF to HI using subreg. * config/i386/predicates.md (vcvtne2ps2bf_parallel): New define_insn_and_split. * config/i386/sse.md (vpermt2_sepcial_bf16_shuffle_<mode>): New predicates matches odd increasing perm. gcc/testsuite/ChangeLog: * gcc.target/i386/vpermt2-special-bf16-shufflue.c: New test.
2024-06-17s390: Delete mistakenly added testsStefan Schulze Frielinghaus9-928/+0
gcc/testsuite/ChangeLog: * gcc.target/s390/vector/vgm-df-1.c: Removed. * gcc.target/s390/vector/vgm-di-1.c: Removed. * gcc.target/s390/vector/vgm-hi-1.c: Removed. * gcc.target/s390/vector/vgm-int128-1.c: Removed. * gcc.target/s390/vector/vgm-longdouble-1.c: Removed. * gcc.target/s390/vector/vgm-qi-1.c: Removed. * gcc.target/s390/vector/vgm-sf-1.c: Removed. * gcc.target/s390/vector/vgm-si-1.c: Removed. * gcc.target/s390/vector/vgm-ti-1.c: Removed.
2024-06-17s390: Extend two element float vectorStefan Schulze Frielinghaus11-0/+974
This implements a V2SF -> V2DF extend. gcc/ChangeLog: * config/s390/vector.md (*vmrhf_half<mode>): New. (extendv2sfv2df2): New. gcc/testsuite/ChangeLog: * gcc.target/s390/vector/vec-extend-3.c: New test.
2024-06-17s390: Extend two/four element integer vectorsStefan Schulze Frielinghaus4-5/+162
For the moment I deliberately left out one-element QHS vectors since it is unclear whether these are pathological cases or whether they are really used. If we ever get an extend for V1DI -> V1TI we should reconsider this. As a side-effect this fixes PR115261. gcc/ChangeLog: PR target/115261 * config/s390/s390.md (any_extend,extend_insn,zero_extend): New code attributes and code iterator. * config/s390/vector.md (V_EXTEND): New mode iterator. (<extend_insn><V_EXTEND:mode><vec_2x_wide>2): New insn. gcc/testsuite/ChangeLog: * gcc.target/s390/vector/vec-extend-1.c: New test. * gcc.target/s390/vector/vec-extend-2.c: New test.
2024-06-17s390: testsuite: Fix nobp-table-jump-*.cStefan Schulze Frielinghaus4-84/+84
Starting with r14-5628-g53ba8d669550d3 interprocedural VRP became strong enough in order to render these tests useless. Fixed by disabling IPA. gcc/testsuite/ChangeLog: * gcc.target/s390/nobp-table-jump-inline-z10.c: Do not perform IPA. * gcc.target/s390/nobp-table-jump-inline-z900.c: Dito. * gcc.target/s390/nobp-table-jump-z10.c: Dito. * gcc.target/s390/nobp-table-jump-z900.c: Dito.
2024-06-17s390: testsuite: Fix ifcvt-one-insn-bool.cStefan Schulze Frielinghaus1-1/+1
With the change of r15-787-g57e04879389f9c I forgot to also update this test. gcc/testsuite/ChangeLog: * gcc.target/s390/ifcvt-one-insn-bool.c: Fix loc.
2024-06-16m2: Remove uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZEKewen Lin1-3/+4
Joseph pointed out "floating types should have their mode, not a poorly defined precision value" in the discussion[1], as he and Richi suggested, the existing macros {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE will be replaced with a hook mode_for_floating_type. To be prepared for that, this patch is to remove uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE in m2. Currently they are used for assertion and can be replaced with TYPE_SIZE check on the corresponding type node, since we dropped the call to layout_type which would early return once TYPE_SIZE is set and this assertion ensures it's safe to drop that call. [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651209.html gcc/m2/ChangeLog: * gm2-gcc/m2type.cc (build_m2_short_real_node): Adjust assertion with TYPE_SIZE check. (build_m2_real_node): Likewise. (build_m2_long_real_node): Add assertion with TYPE_SIZE check.
2024-06-17Daily bump.GCC Administrator4-1/+42
2024-06-16libbacktrace: it's OK if zstd decompressor sees no backward bitsIan Lance Taylor1-8/+1
* elf.c (elf_fetch_bits_backward) Don't fail if no bits are available.
2024-06-16aarch64: Fix reg_is_wrapped_separately array size [PR100211]Andrew Pinski1-1/+1
Currrently the size of the array reg_is_wrapped_separately is LAST_SAVED_REGNUM. But LAST_SAVED_REGNUM could be regno that is being saved. So the size needs to be `LAST_SAVED_REGNUM + 1` like aarch64_frame->reg_offset is. Committed as obvious after a bootstrap/test for aarch64-linux-gnu. gcc/ChangeLog: PR target/100211 * config/aarch64/aarch64.h (machine_function): Fix the size of reg_is_wrapped_separately. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2024-06-16[to-be-committed] [RISC-V] Improve (1 << N) | C for rv64Jeff Law2-0/+46
Another improvement for generating Zbs instructions. In this case we're looking at stuff like (1 << N) | C where N varies and C is a single bit constant. In this pattern the (1 << N) happens in SImode, but is zero extended out to DImode before the bit manipulation. The fact that we're modifying a DImode object in the logical op is important as it means we don't have to worry about whether or not the resulting value is sign extended from SI to DI. This has run through Ventana's CI system. I'll wait for it to roll through pre-commit CI before moving forward. gcc/ * config/riscv/bitmanip.md ((1 << N) | C): New splitter for IOR/XOR of a single bit an a DImode object. gcc/testsuite/ * gcc.target/riscv/zbs-zext.c: New test.
2024-06-15[committed] Fix minor SH scan-asm failure after recent IOR->ADD changesJeff Law1-0/+19
This fixes minor fallout from the IOR->ADD change for rotates that I installed a little while ago. Basically the SH backend has a special pattern for setting the T register that has elements similar to a rotate. With the IOR->ADD change that pattern no longer matches and we get scan-asm failures. Fixing isn't a trivial case of just replacing IOR with ADD as the IOR->ADD change changes some of the simplifications/canonicalizations along the way. The net is we need a pattern with a slightly different structure. I've regression tested this on sh3[eb]-linux-gnu and bootstrapped sh4-linux-gnu (without a regression test). gcc/ * config/sh/sh.md (neg_zero_extract_4b): New pattern.
2024-06-16pretty-print: Don't translate escape sequences to windows console APIPeter Damianov1-2/+3
Modern versions of windows (after windows 10 v1511) support VT100 escape sequences, so translation for them is not necessary. The translation also mangles embedded warning documentation links. gcc/ChangeLog: * pretty-print.cc (mingw_ansi_fputs): Don't translate escape sequences if the console has ENABLE_VIRTUAL_TERMINAL_PROCESSING. Signed-off-by: Peter Damianov <peter0x44@disroot.org>
2024-06-16diagnostics: Don't hardcode auto_enable_urls to false for mingw hostsPeter Damianov1-4/+15
Windows terminal and mintty both have support for link escape sequences, and so auto_enable_urls shouldn't be hardcoded to false. For older versions of the windows console, mingw_ansi_fputs's console API translation logic does mangle these sequences, but there's nothing useful it could do even if this weren't the case, so check if the ansi escape sequences are supported at all. conhost.exe doesn't support link escape sequences, but printing them does not cause any problems. gcc/ChangeLog: * diagnostic-color.cc (auto_enable_urls): Don't hardcode to return false on mingw hosts. (auto_enable_urls): Return true if console supports ansi escape sequences. Signed-off-by: Peter Damianov <peter0x44@disroot.org>
2024-06-16diagnostics: Enable escape sequence processing on windows consolesPeter Damianov1-5/+16
Since windows 10 release v1511, the windows console has had support for VT100 escape sequences. We should try to enable this, and utilize it where possible. gcc/ChangeLog: * diagnostic-color.cc (should_colorize): Enable processing of VT100 escape sequences on windows consoles Signed-off-by: Peter Damianov <peter0x44@disroot.org>
2024-06-16Daily bump.GCC Administrator3-1/+47
2024-06-15RISC-V: Add testcases for vector unsigned SAT_SUB form 2Pan Li8-0/+379
The previous RISC-V backend .SAT_SUB enabling patch missed the form 2 testcases of vector modes. Aka: Form 2: #define DEF_VEC_SAT_U_SUB_FMT_2(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = (x - y) & (-(T)(x > y)); \ } \ } This patch would like to make it up to ensure form 2 of .SAT_SUB vector is covered. Passed the rv64gcv rvv.exp tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-15riscv: Allocate enough space to strcpy() stringChristoph Müllner1-3/+3
I triggered an ICE on Ubuntu 24.04 when compiling code that uses function attributes. Looking into the sources shows that we have a systematic issue in the attribute handling code: * we determine the length with strlen() (excluding the terminating null) * we allocate a buffer with this length * we copy the original string using strcpy() (incl. the terminating null) To quote the man page of strcpy(): "The programmer is responsible for allocating a destination buffer large enough, that is, strlen(src) + 1." The ICE looks like this: *** buffer overflow detected ***: terminated xtheadmempair_bench.c:14:1: internal compiler error: Aborted 14 | { | ^ 0xaf3b99 crash_signal /home/ubuntu/src/gcc/scaleff/gcc/toplev.cc:319 0xe5b957 strcpy /usr/include/riscv64-linux-gnu/bits/string_fortified.h:79 0xe5b957 riscv_process_target_attr /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:339 0xe5baaf riscv_process_target_attr /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:314 0xe5bc5f riscv_option_valid_attribute_p(tree_node*, tree_node*, tree_node*, int) /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:389 0x6a31e5 handle_target_attribute /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-attribs.cc:5915 0x5d3a07 decl_attributes(tree_node**, tree_node*, int, tree_node*) /home/ubuntu/src/gcc/scaleff/gcc/attribs.cc:900 0x5db403 c_decl_attributes /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:5501 0x5e8965 start_function(c_declspecs*, c_declarator*, tree_node*) /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:10562 0x6318ed c_parser_declaration_or_fndef /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2914 0x63a8ad c_parser_external_declaration /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2048 0x63b219 c_parser_translation_unit /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:1902 0x63b219 c_parse_file() /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:27277 0x68fec5 c_common_parse_file() /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-opts.cc:1311 Please submit a full bug report, with preprocessed source (by using -freport-bug). Please include the complete backtrace with any bug report. See <https://gcc.gnu.org/bugs/> for instructions. gcc/ChangeLog: * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch): Fix allocation size of buffer. (riscv_process_one_target_attr): Likewise. (riscv_process_target_attr): Likewise. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2024-06-15RISC-V: Refine the SAT_ARITH test help header files [NFC]Pan Li18-68/+80
Separate the vector part code to one standalone header file, which is independent with the scalar part. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Leverage the new header file for vector part. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c: Ditto. * gcc.target/riscv/sat_arith.h: Move vector part out. * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-15doc: Remove pointer to old versions of binutilsGerald Pfeifer1-4/+0
The oldest release in the advertised location dates back to August 2002, which is way older than we remotely want to cover here. gcc: PR target/69374 * doc/install.texi (Specific): Remove pointer to old versions of binutils.
2024-06-15Daily bump.GCC Administrator6-1/+475
2024-06-14Dont add varying values to gori_on_edge mass calculations.Andrew MacLeod1-9/+15
gori_on_edge will return an ssa_lazy_cache with all contextual ranges that can be generated by an edge. This patch adjusts it so that a VARYING range is never added. * gimple-range-gori.cc (gori_calc_operands): Do not continue nor add the range when VARYING is produced for an operand.
2024-06-14Add merge facility to ssa_lazy_cache.Andrew MacLeod2-0/+19
The ssa_lazy_cache has a routine to merge a range for an ssa-name with an existing range in the cache. This adds a method which will merge all elements of another ssa_lazy_cache. * gimple-range-cache.cc (ssa_lazy_cache::merge): New. * gimple-range-cache.h (ssa_lazy_cache::merge): New prototype.
2024-06-14Do not assume LHS of call is an ssa-name.Andrew MacLeod1-1/+1
gimple_range_fold makes an assumption that the LHS of a call is an ssa_name, which later in compilation may not be true. * gimple-range-fold.cc (fold_using_range::range_of_call): Ensure LHS is an SSA_NAME before invoking gimple_range_global.
2024-06-14testsuite: Add -Wno-psabi to vshuf-mem.C testJakub Jelinek1-1/+1
The newly added test FAILs on i686-linux. On x86_64-linux make check-g++ RUNTESTFLAGS='--target_board=unix\{-m64,-m32/-msse2,-m32/-mno-sse/-mno-mmx\} dg-torture.exp=vshuf-mem.C' shows that as well. The problem is that without SSE2/MMX the vector is passed differently than normally and so GCC warns about that. -Wno-psabi is the usual way to shut it up. Also wonder about the // { dg-additional-options "-march=z14" { target s390*-*-* } } line, doesn't that mean the test will FAIL on all pre-z14 HW? Shouldn't it use some z14_runtime or similar effective target, or check in main (in that case copied over to g++.target/s390) whether z14 instructions can be actually used at runtime? 2024-06-14 Jakub Jelinek <jakub@redhat.com> * g++.dg/torture/vshuf-mem.C: Add -Wno-psabi to dg-options.
2024-06-14AVR: target/115419 - Tie breaks are rounded-to-even.Georg-Johann Lay1-5/+15
libgcc/config/avr/libf7/ PR target/115419 * libf7.c (f7_get_double): Round tie breaks to even LSB.
2024-06-14libstdc++: Make std::type_info::operator== always_inline for C++23 [PR110572]Jonathan Wakely2-0/+14
Commit r12-6266-g3633cc54284450 implemented P1328 for C++23, making std::type_info::operator== usable in constant expressions. For targets such as mingw-w64 where that function was not previously inline, making it constexpr required making it inline for C++23 and later. For statically linked programs this can result in multiple definition errors, because there's a non-inline definition in libstdc++.a as well. For those targets make it always_inline for C++23, so that there is no symbol generated for the inline definition, and the non-inline definition in libstdc++.a will be the only definition. libstdc++-v3/ChangeLog: PR libstdc++/110572 * libsupc++/typeinfo (type_info::operator==): Add always_inline attribute for targets where the ABI requries equality to be non-inline. * testsuite/18_support/type_info/110572.cc: New test.
2024-06-14libstdc++: Fix declaration of posix_memalign for freestandingJonathan Wakely1-1/+1
Thanks to Jérôme Duval for noticing this. libstdc++-v3/ChangeLog: * libsupc++/new_opa.cc [!_GLIBCXX_HOSTED]: Fix declaration of posix_memalign.
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 10Pan Li9-0/+182
After the middle-end support the form 10 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 10 of unsigned .SAT_SUB. Form 10: #define SAT_SUB_U_10(T) \ T sat_sub_u_10_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return !overflow ? ret : 0; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-37.c: New test. * gcc.target/riscv/sat_u_sub-38.c: New test. * gcc.target/riscv/sat_u_sub-39.c: New test. * gcc.target/riscv/sat_u_sub-40.c: New test. * gcc.target/riscv/sat_u_sub-run-37.c: New test. * gcc.target/riscv/sat_u_sub-run-38.c: New test. * gcc.target/riscv/sat_u_sub-run-39.c: New test. * gcc.target/riscv/sat_u_sub-run-40.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 9Pan Li9-0/+182
After the middle-end support the form 9 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 9 of unsigned .SAT_SUB. Form 9: #define SAT_SUB_U_9(T) \ T sat_sub_u_9_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return overflow ? 0 : ret; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-33.c: New test. * gcc.target/riscv/sat_u_sub-34.c: New test. * gcc.target/riscv/sat_u_sub-35.c: New test. * gcc.target/riscv/sat_u_sub-36.c: New test. * gcc.target/riscv/sat_u_sub-run-33.c: New test. * gcc.target/riscv/sat_u_sub-run-34.c: New test. * gcc.target/riscv/sat_u_sub-run-35.c: New test. * gcc.target/riscv/sat_u_sub-run-36.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 8Pan Li9-0/+182
After the middle-end support the form 8 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 8 of unsigned .SAT_SUB. Form 8: #define SAT_SUB_U_8(T) \ T sat_sub_u_8_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return ret & (T)-(!overflow); \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-29.c: New test. * gcc.target/riscv/sat_u_sub-30.c: New test. * gcc.target/riscv/sat_u_sub-31.c: New test. * gcc.target/riscv/sat_u_sub-32.c: New test. * gcc.target/riscv/sat_u_sub-run-29.c: New test. * gcc.target/riscv/sat_u_sub-run-30.c: New test. * gcc.target/riscv/sat_u_sub-run-31.c: New test. * gcc.target/riscv/sat_u_sub-run-32.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 7Pan Li9-0/+182
After the middle-end support the form 7 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 7 of unsigned .SAT_SUB. Form 7: #define SAT_SUB_U_7(T) \ T sat_sub_u_7_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return ret & (T)(overflow - 1); \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-25.c: New test. * gcc.target/riscv/sat_u_sub-26.c: New test. * gcc.target/riscv/sat_u_sub-27.c: New test. * gcc.target/riscv/sat_u_sub-28.c: New test. * gcc.target/riscv/sat_u_sub-run-25.c: New test. * gcc.target/riscv/sat_u_sub-run-26.c: New test. * gcc.target/riscv/sat_u_sub-run-27.c: New test. * gcc.target/riscv/sat_u_sub-run-28.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 6Pan Li9-0/+180
After the middle-end support the form 6 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 6 of unsigned .SAT_SUB. Form 6: #define SAT_SUB_U_6(T) \ T sat_sub_u_6_##T (T x, T y) \ { \ return x <= y ? 0 : x - y; \ } gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-21.c: New test. * gcc.target/riscv/sat_u_sub-22.c: New test. * gcc.target/riscv/sat_u_sub-23.c: New test. * gcc.target/riscv/sat_u_sub-24.c: New test. * gcc.target/riscv/sat_u_sub-run-21.c: New test. * gcc.target/riscv/sat_u_sub-run-22.c: New test. * gcc.target/riscv/sat_u_sub-run-23.c: New test. * gcc.target/riscv/sat_u_sub-run-24.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 5Pan Li9-0/+180
After the middle-end support the form 5 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 5 of unsigned .SAT_SUB. Form 5: #define SAT_SUB_U_5(T) \ T sat_sub_u_5_##T (T x, T y) \ { \ return x < y ? 0 : x - y; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-17.c: New test. * gcc.target/riscv/sat_u_sub-18.c: New test. * gcc.target/riscv/sat_u_sub-19.c: New test. * gcc.target/riscv/sat_u_sub-20.c: New test. * gcc.target/riscv/sat_u_sub-run-17.c: New test. * gcc.target/riscv/sat_u_sub-run-18.c: New test. * gcc.target/riscv/sat_u_sub-run-19.c: New test. * gcc.target/riscv/sat_u_sub-run-20.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 4Pan Li9-0/+180
After the middle-end support the form 4 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 4 of unsigned .SAT_SUB. Form 4: #define SAT_SUB_U_4(T) \ T sat_sub_u_4_##T (T x, T y) \ { \ return x >= y ? x - y : 0; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-13.c: New test. * gcc.target/riscv/sat_u_sub-14.c: New test. * gcc.target/riscv/sat_u_sub-15.c: New test. * gcc.target/riscv/sat_u_sub-16.c: New test. * gcc.target/riscv/sat_u_sub-run-13.c: New test. * gcc.target/riscv/sat_u_sub-run-14.c: New test. * gcc.target/riscv/sat_u_sub-run-15.c: New test. * gcc.target/riscv/sat_u_sub-run-16.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14RISC-V: Add testcases for scalar unsigned SAT_SUB form 3Pan Li9-0/+180
After the middle-end support the form 3 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 3 of unsigned .SAT_SUB. Form 3: #define SAT_SUB_U_3(T) \ T sat_sub_u_3_##T (T x, T y) \ { \ return x > y ? x - y : 0; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-10.c: New test. * gcc.target/riscv/sat_u_sub-11.c: New test. * gcc.target/riscv/sat_u_sub-12.c: New test. * gcc.target/riscv/sat_u_sub-9.c: New test. * gcc.target/riscv/sat_u_sub-run-10.c: New test. * gcc.target/riscv/sat_u_sub-run-11.c: New test. * gcc.target/riscv/sat_u_sub-run-12.c: New test. * gcc.target/riscv/sat_u_sub-run-9.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-06-14Match: Support more forms for the scalar unsigned .SAT_SUBPan Li2-2/+56
After we support the scalar unsigned form 1 and 2, we would like to introduce more forms include the branch and branchless. There are forms 3-10 list as below: Form 3: #define SAT_SUB_U_3(T) \ T sat_sub_u_3_##T (T x, T y) \ { \ return x > y ? x - y : 0; \ } Form 4: #define SAT_SUB_U_4(T) \ T sat_sub_u_4_##T (T x, T y) \ { \ return x >= y ? x - y : 0; \ } Form 5: #define SAT_SUB_U_5(T) \ T sat_sub_u_5_##T (T x, T y) \ { \ return x < y ? 0 : x - y; \ } Form 6: #define SAT_SUB_U_6(T) \ T sat_sub_u_6_##T (T x, T y) \ { \ return x <= y ? 0 : x - y; \ } Form 7: #define SAT_SUB_U_7(T) \ T sat_sub_u_7_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return ret & (T)(overflow - 1); \ } Form 8: #define SAT_SUB_U_8(T) \ T sat_sub_u_8_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return ret & (T)-(!overflow); \ } Form 9: #define SAT_SUB_U_9(T) \ T sat_sub_u_9_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return overflow ? 0 : ret; \ } Form 10: #define SAT_SUB_U_10(T) \ T sat_sub_u_10_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return !overflow ? ret : 0; \ } Take form 10 as example: SAT_SUB_U_10(uint64_t); Before this patch: uint8_t sat_sub_u_10_uint8_t (uint8_t x, uint8_t y) { unsigned char _1; unsigned char _2; uint8_t _3; __complex__ unsigned char _6; ;; basic block 2, loop depth 0 ;; pred: ENTRY _6 = .SUB_OVERFLOW (x_4(D), y_5(D)); _2 = IMAGPART_EXPR <_6>; if (_2 == 0) goto <bb 3>; [50.00%] else goto <bb 4>; [50.00%] ;; succ: 3 ;; 4 ;; basic block 3, loop depth 0 ;; pred: 2 _1 = REALPART_EXPR <_6>; ;; succ: 4 ;; basic block 4, loop depth 0 ;; pred: 2 ;; 3 # _3 = PHI <0(2), _1(3)> return _3; ;; succ: EXIT } After this patch: uint8_t sat_sub_u_10_uint8_t (uint8_t x, uint8_t y) { uint8_t _3; ;; basic block 2, loop depth 0 ;; pred: ENTRY _3 = .SAT_SUB (x_4(D), y_5(D)); [tail call] return _3; ;; succ: EXIT } The below test suites are passed for this patch: 1. The rv64gcv fully regression test with newlib. 2. The rv64gcv build with glibc. 3. The x86 bootstrap test. 4. The x86 fully regression test. gcc/ChangeLog: * match.pd: Add more match for unsigned sat_sub. * tree-ssa-math-opts.cc (match_unsigned_saturation_sub): Add new func impl to match phi node for .SAT_SUB. (math_opts_dom_walker::after_dom_children): Try match .SAT_SUB for the phi node, MULT_EXPR, BIT_XOR_EXPR and BIT_AND_EXPR. Signed-off-by: Pan Li <pan2.li@intel.com>
generated by cgit v1.1 at 2025-07-28 12:01:02 +0000