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2021-02-03Add -f[no-]header-guard-optdevel/c++-modulesNathan Sidwell13-19/+106
Added so that one can determine the include graph from the -E output.
2021-02-03Merge commit '84110515b93' into devel/c++-modulesNathan Sidwell2152-38772/+101783
2021-02-03Fill up padding in lto_section struct.Martin Liska2-1/+2
gcc/ChangeLog: PR lto/98912 * lto-streamer-out.c (produce_lto_section): Fill up missing padding. * lto-streamer.h (struct lto_section): Add _padding field.
2021-02-03Fix regression with partial rep clause on variant record typeEric Botcazou2-37/+79
It can yield an incorrect layout when there is a partial representation clause on a discriminated record type with a variant part. gcc/ada/ * gcc-interface/decl.c (components_to_record): If the first component with rep clause is the _Parent field with variable size, temporarily set it aside when computing the internal layout of the REP part again. * gcc-interface/utils.c (finish_record_type): Revert to taking the maximum when merging sizes for all record types with rep clause. (merge_sizes): Put SPECIAL parameter last and adjust recursive calls.
2021-02-03Assorted LTO fixes for AdaEric Botcazou2-7/+22
This polishes a few rough edges visible in LTO mode. gcc/ada/ * gcc-interface/decl.c (gnat_to_gnu_entity) <E_Array_Type>: Make the two fields of the fat pointer type addressable, and do not make the template type read-only. <E_Record_Type>: If the type has discriminants mark it as may_alias. * gcc-interface/utils.c (make_dummy_type): Likewise. (build_dummy_unc_pointer_types): Likewise.
2021-02-03Fortran: Fix Array dependency with local coarrays [PR98913]Tobias Burnus2-3/+86
gcc/fortran/ChangeLog: PR fortran/98913 * dependency.c (gfc_dep_resolver): Treat local access to coarrays like any array access in dependency analysis. gcc/testsuite/ChangeLog: PR fortran/98913 * gfortran.dg/coarray/array_temporary.f90: New test.
2021-02-03more memory leak fixesRichard Biener2-2/+7
This fixes more memory leaks as discovered by building 521.wrf_r. 2021-02-03 Richard Biener <rguenther@suse.de> * lto-streamer.c (lto_get_section_name): Free temporary buffer. * tree-loop-distribution.c (loop_distribution::merge_dep_scc_partitions): Free edge data.
2021-02-03ifcvt: Avoid ICEs trying to force_operand random RTL [PR97487]Jakub Jelinek3-6/+92
As the testcase shows, RTL ifcvt can throw random RTL (whatever it found in some insns) at expand_binop or expand_unop and expects it to do something (and then will check if it created valid insns and punts if not). These functions in the end if the operands don't match try to copy_to_mode_reg the operands, which does if (!general_operand (x, VOIDmode)) x = force_operand (x, temp); but, force_operand is far from handling all possible RTLs, it will ICE for all more unusual RTL codes. Basically handles just simple arithmetic and unary RTL operations if they have an optab and expand_simple_binop/expand_simple_unop ICE on others. The following patch fixes it by adding some operand verification (whether there is a hope that copy_to_mode_reg will succeed on those). It is added both to noce_emit_move_insn (not needed for this exact testcase, that function simply tries to recog the insn as is and if it fails, handles some simple binop/unop cases; the patch performs the verification of their operands) and noce_try_sign_mask. 2021-02-03 Jakub Jelinek <jakub@redhat.com> PR middle-end/97487 * ifcvt.c (noce_can_force_operand): New function. (noce_emit_move_insn): Use it. (noce_try_sign_mask): Likewise. Formatting fix. * gcc.dg/pr97487-1.c: New test. * gcc.dg/pr97487-2.c: New test.
2021-02-03lra-constraints: Fix error-recovery for bad inline-asms [PR97971]Jakub Jelinek2-2/+19
The following testcase has ice-on-invalid, it can't be reloaded, but we shouldn't ICE the compiler because the user typed non-sense. In current_insn_transform we have: if (process_alt_operands (reused_alternative_num)) alt_p = true; if (check_only_p) return ! alt_p || best_losers != 0; /* If insn is commutative (it's safe to exchange a certain pair of operands) then we need to try each alternative twice, the second time matching those two operands as if we had exchanged them. To do this, really exchange them in operands. If we have just tried the alternatives the second time, return operands to normal and drop through. */ if (reused_alternative_num < 0 && commutative >= 0) { curr_swapped = !curr_swapped; if (curr_swapped) { swap_operands (commutative); goto try_swapped; } else swap_operands (commutative); } if (! alt_p && ! sec_mem_p) { /* No alternative works with reloads?? */ if (INSN_CODE (curr_insn) >= 0) fatal_insn ("unable to generate reloads for:", curr_insn); error_for_asm (curr_insn, "inconsistent operand constraints in an %<asm%>"); lra_asm_error_p = true; ... and so handle inline asms there differently (and delete/nullify them after this) - fatal_insn is only called for non-inline asm. But in process_alt_operands we do: /* Both the earlyclobber operand and conflicting operand cannot both be user defined hard registers. */ if (HARD_REGISTER_P (operand_reg[i]) && REG_USERVAR_P (operand_reg[i]) && operand_reg[j] != NULL_RTX && HARD_REGISTER_P (operand_reg[j]) && REG_USERVAR_P (operand_reg[j])) fatal_insn ("unable to generate reloads for " "impossible constraints:", curr_insn); and thus ICE even for inline-asms. I think it is inappropriate to delete/nullify the insn in process_alt_operands, as it could be done e.g. in the check_only_p mode, so this patch just returns false in that case, which results in the caller have alt_p false, and as inline asm isn't simple move, sec_mem_p will be also false (and it isn't commutative either), so for check_only_p it will suggests to the callers it isn't ok and otherwise will emit error and delete/nullify the inline asm insn. 2021-02-03 Jakub Jelinek <jakub@redhat.com> PR middle-end/97971 * lra-constraints.c (process_alt_operands): For inline asm, don't call fatal_insn, but instead return false. * gcc.target/i386/pr97971.c: New test.
2021-02-03i386: Remove V1DImode shift expanders [PR98287]Jakub Jelinek2-3/+22
On Tue, Feb 02, 2021 at 02:23:55PM +0100, Richard Biener wrote: > All I say is that the x86 target > should either not advertise V1DF shifts or advertise the basic > ops that reasonable simplification would expect to exist. The backend has several V1?Imode shifts, but optab only for those V1DImode ones: grep '[la]sh[lr]v1[qhsdtox]' tmp-mddump.md (define_insn ("mmx_ashlv1di3") (define_insn ("mmx_lshrv1di3") (define_insn ("avx512bw_ashlv1ti3") (define_insn ("avx512bw_lshrv1ti3") (define_insn ("sse2_ashlv1ti3") (define_insn ("sse2_lshrv1ti3") (define_expand ("ashlv1di3") (define_expand ("lshrv1di3") emit_insn (gen_sse2_lshrv1ti3 (tmp, gen_lowpart (V1TImode, operands[1]), I think it has been introduced with https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89021#c13 Before we didn't have any V1DImode expanders (except mov/movmisalign, but those are needed and are supplied for other V1??mode modes too). This patch just removes the two V1DImode shift expanders with standard names. 2021-02-03 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/98287 * config/i386/mmx.md (<insn><mode>3): For shifts don't enable expander for V1DImode. * gcc.dg/pr98287.c: New test.
2021-02-03slp: Split out patterns away from using SLP_ONLY into their own flagTamar Christina4-2/+66
Previously the SLP pattern matcher was using STMT_VINFO_SLP_VECT_ONLY as a way to dissolve the SLP only patterns during SLP cancellation. However it seems like the semantics for STMT_VINFO_SLP_VECT_ONLY are slightly different than what I expected. Namely that the non-SLP path can still use a statement marked STMT_VINFO_SLP_VECT_ONLY. One such example is masked loads which are used both in the SLP and non-SLP path. To fix this I now introduce a new flag STMT_VINFO_SLP_VECT_ONLY_PATTERN which is used only by the pattern matcher. gcc/ChangeLog: PR tree-optimization/98928 * tree-vect-loop.c (vect_analyze_loop_2): Change STMT_VINFO_SLP_VECT_ONLY to STMT_VINFO_SLP_VECT_ONLY_PATTERN. * tree-vect-slp-patterns.c (complex_pattern::build): Likewise. * tree-vectorizer.h (STMT_VINFO_SLP_VECT_ONLY_PATTERN): New. (class _stmt_vec_info): Add slp_vect_pattern_only_p. gcc/testsuite/ChangeLog: PR tree-optimization/98928 * gcc.target/i386/pr98928.c: New test.
2021-02-03Daily bump.GCC Administrator8-1/+206
2021-02-02gotools: for "make check" run "go test embed/internal/embedtest"Ian Lance Taylor2-9/+45
* Makefile.am (check-embed): New target. (check): Depend on check-embed. Examine embed-testlog. (mostlyclean-local): Add check-embed-dir. (.PHONY): Add check-embed. * Makefile.in: Regenerate.
2021-02-02fix memory leaksRichard Biener4-19/+11
This fixes various vec<> memory leaks as discovered compiling 521.wrf_r. 2021-02-02 Richard Biener <rguenther@suse.de> * gimple-loop-interchange.cc (prepare_data_references): Release vectors. * gimple-loop-jam.c (tree_loop_unroll_and_jam): Likewise. * tree-ssa-loop-im.c (hoist_memory_references): Likewise. * tree-vect-stmts.c (vectorizable_condition): Do not allocate vectors. (vectorizable_comparison): Likewise.
2021-02-02Add test-case.Martin Liska1-0/+18
gcc/testsuite/ChangeLog: PR target/97510 * gcc.target/i386/pr97510.c: New test.
2021-02-02c++: Member fns and deduction guide rewriting [PR98929]Jason Merrill3-1/+23
My patch for 96199 had us re-substitute the parameter types of a constructor in order to rewrite mentions of members into dependent references. We need to do that for member functions, too. gcc/cp/ChangeLog: PR c++/98929 PR c++/96199 * error.c (dump_expr): Ignore dummy object. * pt.c (tsubst_baselink): Handle dependent scope. gcc/testsuite/ChangeLog: PR c++/98929 * g++.dg/cpp1z/class-deduction-decltype1.C: New test.
2021-02-02aarch64: Reimplement vrsqrte* intrinsics with builtinsKyrylo Tkachov3-12/+13
Another very simple move from inline asm to builtins. Only two intrinsics this time. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (ursqrte): Define builtin. * config/aarch64/aarch64-simd.md (aarch64_ursqrte<mode>): New pattern. * config/aarch64/arm_neon.h (vrsqrte_u32): Reimplement using builtin. (vrsqrteq_u32): Likewise.
2021-02-02aarch64: Reimplement vqmovun_high* intrinsics using builtinsKyrylo Tkachov5-19/+48
Another transition from inline asm to builtin. Only 3 intrinsics converted this time but they use the "+w" constraint in their inline asm so are more likely to generate redundant moves so benefit more from reimplementation. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (sqxtun2): Define builtin. * config/aarch64/aarch64-simd.md (aarch64_sqxtun2<mode>_le): Define. (aarch64_sqxtun2<mode>_be): Likewise. (aarch64_sqxtun2<mode>): Likewise. * config/aarch64/arm_neon.h (vqmovun_high_s16): Reimplement using builtin. (vqmovun_high_s32): Likewise. (vqmovun_high_s64): Likewise. * config/aarch64/iterators.md (UNSPEC_SQXTUN2): Define. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_high-intrinsics.c: Adjust sqxtun2 scan.
2021-02-02Fortran: Check remains fixed by patch for PRs 96100/101 [PR91862].Paul Thomas1-0/+26
2021-02-02 Paul Thomas <pault@gcc.gnu.org> gcc/testsuite PR fortran/91862 * gfortran.dg/pr91862.f90: New test.
2021-02-02aarch64: Update flags for bfloat16 builtinsKyrylo Tkachov1-6/+6
This patch updates the flags for the bfloat16 builtins. The bfdot ones aren't affected by the FPCR/FPSR so can be AUTO_FP whereas the bfmlal ones follow the normal floating-point instructions and get FP. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (bfdot_lane, bfdot_laneq): Use AUTO_FP flags. (bfmlalb_lane, bfmlalt_lane, bfmlalb_lane_q, bfmlalt_lane_q): Use FP flags.
2021-02-02aarch64: Relax flags for floating-point builtins to FP where appropriateKyrylo Tkachov1-34/+34
This patch relaxes various floating-point builtins to use the FP flags to signify they made use the FPCR or raise exceptions. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270, fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270, scvtf, ucvtf, fcvtzs, fcvtzu, scvtfsi, scvtfdi, ucvtfsi, ucvtfdi, fcvtzshf, fcvtzuhf, fmlal_lane_low, fmlsl_lane_low, fmlal_laneq_low, fmlsl_laneq_low, fmlalq_lane_low, fmlslq_lane_low, fmlalq_laneq_low, fmlslq_laneq_low, fmlal_lane_high, fmlsl_lane_high, fmlal_laneq_high, fmlsl_laneq_high, fmlalq_lane_high, fmlslq_lane_high, fmlalq_laneq_high, fmlslq_laneq_high): Use FP flags.
2021-02-02aarch64: Add and use FLAG_LOAD in builtinsKyrylo Tkachov2-14/+15
We already have a STORE flag that we use for builtins. This patch introduces a LOAD set that uses AUTO_FP and FLAG_READ_MEMORY. This allows for more aggressive optimisation of the load intrinsics. Turns out we have a great many testcases that do: float16x4x2_t f_vld2_lane_f16 (float16_t * p, float16x4x2_t v) { float16x4x2_t res; /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */ res = vld2_lane_f16 (p, v, 4); /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */ res = vld2_lane_f16 (p, v, -1); return res; } but since the first res is unused it now gets eliminated early on before we get to give an error message. Ideally we'd like to warn for both. This patch takes the conservative approach and doesn't convert the load-lane builtins to LOAD ; that's something we can improve later. gcc/ChangeLog: * config/aarch64/aarch64-builtins.c (FLAG_LOAD): Define. * config/aarch64/aarch64-simd-builtins.def (ld1x2, ld2, ld3, ld4, ld2r, ld3r, ld4r, ld1, ld1x3, ld1x4): Use LOAD flags.
2021-02-02aarch64: Relax some builtins to AUTO_FPKyrylo Tkachov1-9/+9
This patch relaxes the flags for some builtins to AUTO_FP. These builtins do permutes and similar, so they shouldn't get the FP flags when operating on floating-point modes as they don't care about FPCR/FPSR and exceptions. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (combine, zip1, zip2, uzp1, uzp2, trn1, trn2, simd_bsl): Use AUTO_FP flags.
2021-02-02aarch64: Relax builtin flags for integer builtinsKyrylo Tkachov2-56/+58
This patch relaxes the flags for most integer builtins to NONE as they don't read/write memory and don't care about the FPCR/FPSR or exceptions so we should be more aggressive with them. This leads to fallout in a testcase where the result of an intrinsic was unused and it is now DCE'd. The testcase is adjusted. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (clrsb, clz, ctz, popcount, vec_smult_lane_, vec_smlal_lane_, vec_smult_laneq_, vec_smlal_laneq_, vec_umult_lane_, vec_umlal_lane_, vec_umult_laneq_, vec_umlal_laneq_, ashl, sshl, ushl, srshl, urshl, sdot_lane, udot_lane, sdot_laneq, udot_laneq, usdot_lane, usdot_laneq, sudot_lane, sudot_laneq, ashr, ashr_simd, lshr, lshr_simd, srshr_n, urshr_n, ssra_n, usra_n, srsra_n, ursra_n, sshll_n, ushll_n, sshll2_n, ushll2_n, ssri_n, usri_n, ssli_n, ssli_n, usli_n, bswap, rbit, simd_bsl, eor3q, rax1q, xarq, bcaxq): Use NONE builtin flags. gcc/testsuite/ChangeLog: * gcc.target/aarch64/arg-type-diagnostics-1.c: Return result from foo.
2021-02-02libstdc++: Fix markup for status tables in docsJonathan Wakely4-6/+3
libstdc++-v3/ChangeLog: * doc/xml/manual/status_cxx2011.xml: Remove stray table cell. * doc/xml/manual/status_cxx2014.xml: Likewise. * doc/xml/manual/status_cxx2017.xml: Likewise. * doc/html/manual/status.html: Regenerate.
2021-02-02tree-vect-patterns: Don't create over widening patterns for stmts used in ↵Jakub Jelinek3-1/+23
reductions [PR98848] As discussed in the PR, the reduction code isn't able to cope with type promotions/demotions in the reduction computation, so if we recognize an over-widening pattern that has vect_reduction_def type, we most likely make it non-vectorizable. 2021-02-02 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/98848 * tree-vect-patterns.c (vect_recog_over_widening_pattern): Punt if STMT_VINFO_DEF_TYPE (last_stmt_info) is vect_reduction_def. * gcc.dg/vect/pr98848.c: New test. * gcc.dg/vect/pr92205.c: Remove xfail.
2021-02-02testsuite: Add testcase for already fixed PR [PR97960]Jakub Jelinek1-0/+30
This testcase has been fixed by r11-5904-g4cf70c20cb10acd6fb1016611d05540728176b60 so I'm checking it in so that we can close the PR. 2021-02-02 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/97960 * g++.dg/torture/pr97960.C: New test.
2021-02-02PR target/98743: Fix ICE in convert_move for RISC-VKito Cheng2-0/+28
- Check `from` mode is not BLMmode before call store_expr, calling store_expr with BLKmode will cause ICE. - Verified with riscv64, x86_64 and aarch64, no introduce new regression. Note: Those logic was introduced by 3e60ddeb8220ed388819bb3f14e8caa9309fd3c2, so I cc Jakub for reivew. Changes for V2: - Checking mode of `from` rather than mode of `to`. - Verified on riscv64, x86_64 and aarch64 again. gcc/ChangeLog: PR target/98743 * expr.c: Check mode before calling store_expr. gcc/testsuite/ChangeLog: PR target/98743 * g++.dg/opt/pr98743.C: New.
2021-02-02arm: Auto-vectorization for MVE: vornChristophe Lyon4-13/+54
This patch enables MVE vornq instructions for auto-vectorization. MVE vornq insns in mve.md are modified to use ior instead of unspec expression. 2021-02-01 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/iterators.md (supf): Remove VORNQ_S and VORNQ_U. (VORNQ): Remove. * config/arm/mve.md (mve_vornq_s<mode>): New entry for vorn instruction using expression ior. (mve_vornq_u<mode>): New expander. (mve_vornq_f<mode>): Use ior code instead of unspec. * config/arm/unspecs.md (VORNQ_S, VORNQ_U, VORNQ_F): Remove. gcc/testsuite/ * gcc.target/arm/simd/mve-vorn.c: Add vorn tests.
2021-02-02restore current_function_decl after re-gimplifying nested ADDR_EXPRsAlexandre Oliva2-2/+26
Ada makes extensive use of nested functions, which turn all automatic variables of the enclosing function that are used in nested ones into members of an artificial FRAME record type. The address of a local variable is usually passed to asan marking functions without using a temporary. asan_expand_mark_ifn will reject an ADDR_EXPRs if it's split out from the call into an SSA_NAMEs. Taking the address of a member of FRAME within a nested function was not regarded as a gimple val: while introducing FRAME variables, current_function_decl pointed to the outermost function, even while processing a nested function, so decl_address_invariant_p, checking that the context of the variable is current_function_decl, returned false for such ADDR_EXPRs. decl_address_invariant_p, called when determining whether an expression is a legitimate gimple value, compares the context of automatic variables with current_function_decl. Some of the tree-nested function processing doesn't set current_function_decl, but ADDR_EXPR-processing bits temporarily override it. However, they restore it before re-gimplifying, which causes even ADDR_EXPRs referencing automatic variables in the FRAME struct of a nested function to not be regarded as address-invariant. This patch moves the restores of current_function_decl in the ADDR_EXPR-handling bits after the re-gimplification, so that the correct current_function_decl is used when testing for address invariance. for gcc/ChangeLog * tree-nested.c (convert_nonlocal_reference_op): Move current_function_decl restore after re-gimplification. (convert_local_reference_op): Likewise. for gcc/testsuite/ChangeLog * gcc.dg/asan/nested-1.c: New.
2021-02-01analyzer: directly explore within static functions [PR93355,PR96374]David Malcolm9-79/+69
PR analyzer/93355 tracks that -fanalyzer fails to report the FILE * leak in read_alias_file in intl/localealias.c. One reason for the failure is that read_alias_file is marked as "static", and the path leading to the single call of read_alias_file is falsely rejected as infeasible due to PR analyzer/96374. I have been attempting to fix that bug, but don't have a good solution yet. Previously, -fanalyzer only directly explored "static" functions if they were needed for call summaries, instead forcing them to be indirectly explored, but if we have a feasibility bug like above, we will fail to report any issues in a function that's only called by such a falsely infeasible path. It now seems wrong to me to reject directly exploring static functions: even if there is currently no way to call a function, it seems reasonable to warn about bugs within them, since otherwise these latent bugs are a timebomb in the code. Hence this patch reworks toplevel_function_p to directly explore almost all functions, working around these feasiblity issues. It introduces a naming convention that "__analyzer_"-prefixed function names don't get directly explored, since this is useful in the analyzer's DejaGnu-based tests. This workaround gets PR analyzer/93355 closer to working, but unfortunately there is a second instance of PR analyzer/96374 within read_alias_file itself which means even with this patch -fanalyzer falsely rejects the path as infeasible. Still, this ought to help in other cases, and simplifies the implementation. gcc/analyzer/ChangeLog: PR analyzer/93355 PR analyzer/96374 * engine.cc (toplevel_function_p): Simplify so that we only reject functions with a "__analyzer_" prefix. (add_any_callbacks): Delete. (exploded_graph::build_initial_worklist): Update for dropped param of toplevel_function_p. (exploded_graph::build_initial_worklist): Don't bother looking for callbacks that are reachable from global initializers. gcc/testsuite/ChangeLog: PR analyzer/93355 PR analyzer/96374 * gcc.dg/analyzer/conditionals-3.c: Add "__analyzer_" prefix to support subroutines where necessary. * gcc.dg/analyzer/data-model-1.c: Likewise. * gcc.dg/analyzer/feasibility-1.c (called_by_test_6a): New. (test_6a): New. * gcc.dg/analyzer/params.c: Add "__analyzer_" prefix to support subroutines where necessary. * gcc.dg/analyzer/pr96651-2.c: Likewise. * gcc.dg/analyzer/signal-4b.c: Likewise. * gcc.dg/analyzer/single-field.c: Likewise. * gcc.dg/analyzer/torture/conditionals-2.c: Likewise.
2021-02-01analyzer: add more feasibility test cases [PR93355,PR96374]David Malcolm2-0/+95
This patch adds a couple more reduced test cases derived from the integration test for PR analyzer/93355. In both cases, the analyzer falsely rejects the buggy code paths as being infeasible due to PR analyzer/96374, and so the tests are marked as XFAIL for now. gcc/testsuite/ChangeLog: PR analyzer/93355 PR analyzer/96374 * gcc.dg/analyzer/pr93355-localealias-feasibility-2.c: New test. * gcc.dg/analyzer/pr93355-localealias-feasibility-3.c: New test.
2021-02-02d: Fix junk in generated symbol on powerpc64-*-* [PR98921]Iain Buclaw4-10/+53
This adds a special formatter to OutBuffer to handle formatted printing of integers, a common case. The replacement is faster and safer. In dmangle.c, it also gets rid of a number of problematic casts, as seen on powerpc64 targets. Reviewed-on: https://github.com/dlang/dmd/pull/12174 gcc/d/ChangeLog: PR d/98921 * dmd/MERGE: Merge upstream dmd 5e2a81d9c.
2021-02-02Daily bump.GCC Administrator8-1/+262
2021-02-01aarch64: Reimplement vrshrn* intrinsics using builtinsKyrylo Tkachov5-151/+171
This patch moves the vrshrn* intrinsics to builtins away from inline asm. It's a bit of code, but it's very similar to the recent vsrhn* reimplementation except that we use an unspec rather than standard RTL codes for the functionality. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (rshrn, rshrn2): Define builtins. * config/aarch64/aarch64-simd.md (aarch64_rshrn<mode>_insn_le): Define. (aarch64_rshrn<mode>_insn_be): Likewise. (aarch64_rshrn<mode>): Likewise. (aarch64_rshrn2<mode>_insn_le): Likewise. (aarch64_rshrn2<mode>_insn_be): Likewise. (aarch64_rshrn2<mode>): Likewise. * config/aarch64/aarch64.md (unspec): Add UNSPEC_RSHRN. * config/aarch64/arm_neon.h (vrshrn_high_n_s16): Reimplement using builtin. (vrshrn_high_n_s32): Likewise. (vrshrn_high_n_s64): Likewise. (vrshrn_high_n_u16): Likewise. (vrshrn_high_n_u32): Likewise. (vrshrn_high_n_u64): Likewise. (vrshrn_n_s16): Likewise. (vrshrn_n_s32): Likewise. (vrshrn_n_s64): Likewise. (vrshrn_n_u16): Likewise. (vrshrn_n_u32): Likewise. (vrshrn_n_u64): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_high-intrinsics.c: Adjust rshrn2 assembly scan.
2021-02-01analyzer: fix false positives with *UNKNOWN_PTR [PR98918]David Malcolm2-0/+35
PR analyzer/98918 reports various false positives and state explosions on correct code that frees nodes and other pointers in a singly-linked list. The issue is that state-merger in the loop leads to UNKNOWN_VALUEs, and these are then erroneously used to form compound symbolic values and regions, such as; INIT_VAL((*UNKNOWN(struct marker *)).ref) and: (*INIT_VAL((*UNKNOWN(struct marker * *)))) The malloc state machine then treats these symbolic values as identifying specific pointers, and thus e.g. erroneously reports a double-free when INIT_VAL((*UNKNOWN(struct marker *)).ref) is freed twice (on subsequent iterations of the loop). Similarly, the increasingly complex compound symbolic values have sm-state which prevents state merging, and eventually lead to the analysis hitting safety limits and stopping. This patch makes various compound values involving UNKNOWN be themselves UNKNOWN, resolving both the false positives and the state explosions. gcc/analyzer/ChangeLog: PR analyzer/98918 * region-model-manager.cc (region_model_manager::get_or_create_initial_value): Fold the initial value of *UNKNOWN_PTR to an UNKNOWN value. (region_model_manager::get_field_region): Fold the value of UNKNOWN_PTR->FIELD to *UNKNOWN_PTR_OF_&FIELD_TYPE. gcc/testsuite/ChangeLog: PR analyzer/98918 * gcc.dg/analyzer/pr98918.c: New test.
2021-02-01libstdc++: Make deque iterator operator- usable with value-init iteratorsFrançois Dumont3-6/+146
N3644 implies that operator- can be used on value-init iterators. We now return 0 if both iterators are value initialized. If only one is value initialized we keep the UB by returning the result of a normal computation which is a meaningless value. libstdc++-v3/ChangeLog: PR libstdc++/70303 * include/bits/stl_deque.h (std::deque<>::operator-(iterator, iterator)): Return 0 if both iterators are value-initialized. * testsuite/23_containers/deque/70303.cc: New test. * testsuite/23_containers/vector/70303.cc: New test.
2021-02-01tree-optimization/98499 - fix modref analysis on RVO statementsSergei Trofimovich2-4/+45
Before the change RVO gimple statements were treated as local stores by modres analysis. But in practice RVO escapes target. 2021-02-01 Sergei Trofimovich <siarheit@google.com> gcc/ChangeLog: PR tree-optimization/98499 * ipa-modref.c (analyze_ssa_name_flags): treat RVO conservatively and assume all possible side-effects. gcc/testsuite/ChangeLog: PR tree-optimization/98499 * g++.dg/pr98499.C: new test.
2021-02-01aarch64: Reimplement vmovl_high_* intrinsics using builtinsKyrylo Tkachov3-36/+42
The vmovl_high_* intrinsics map down to the SXTL2/UXTL2 instructions that already have appropriately-named patterns and expanders, so it's straightforward to wire them up. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi, vec_unpacku_hi_): Define builtins. * config/aarch64/arm_neon.h (vmovl_high_s8): Reimplement using builtin. (vmovl_high_s16): Likewise. (vmovl_high_s32): Likewise. (vmovl_high_u8): Likewise. (vmovl_high_u16): Likewise. (vmovl_high_u32): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/vmovl_high_1.c: New test.
2021-02-01aarch64: Reimplement vabdl_* intrinsics using builtinsKyrylo Tkachov5-36/+27
Another simple set of intrinsic moved to builtins in the straightforward way. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (sabdl, uabdl): Define builtins. * config/aarch64/aarch64-simd.md (aarch64_<sur>abdl<mode>): New pattern. * config/aarch64/aarch64.md (unspec): Define UNSPEC_SABDL, UNSPEC_UABDL. * config/aarch64/arm_neon.h (vabdl_s8): Reimplemet using builtin. (vabdl_s16): Likewise. (vabdl_s32): Likewise. (vabdl_u8): Likewise. (vabdl_u16): Likewise. (vabdl_u32): Likewise. * config/aarch64/iterators.md (ABDL): New int iterator. (sur): Handle UNSPEC_SABDL, UNSPEC_UABDL.
2021-02-01Document various BLOCK macros.Martin Sebor1-2/+16
gcc/ChangeLog: * tree.h (BLOCK_VARS): Add comment. (BLOCK_SUBBLOCKS): Same. (BLOCK_SUPERCONTEXT): Same. (BLOCK_ABSTRACT_ORIGIN): Same. (inlined_function_outer_scope_p): Same.
2021-02-01Reset front end trees before they make it into the middle end (PR ↵Martin Sebor4-0/+109
middle-end/97172). gcc/ChangeLog: PR middle-end/97172 * attribs.c (attr_access::free_lang_data): Define new function. * attribs.h (attr_access::free_lang_data): Declare new function. gcc/c/ChangeLog: PR middle-end/97172 * c-decl.c (free_attr_access_data): New function. (c_parse_final_cleanups): Call free_attr_access_data. gcc/testsuite/ChangeLog: PR middle-end/97172 * gcc.dg/pr97172.c: New test.
2021-02-01libstdc++: Update C++17 status table for <charconv>Jonathan Wakely4-30/+33
libstdc++-v3/ChangeLog: * doc/xml/manual/status_cxx2011.xml: Update std::call_once status. * doc/xml/manual/status_cxx2014.xml: Likewise. * doc/xml/manual/status_cxx2017.xml: Likewise. Update std::from_chars and std::to_chars status. Fix formatting. * doc/html/manual/status.html: Regenerate.
2021-02-01Avoid -Wstringop-truncation.Martin Sebor1-1/+1
libiberty/ChangeLog: * dyn-string.c (dyn_string_insert_cstr): Use memcpy instead of strncpy to avoid -Wstringop-truncation.
2021-02-01Fix statistic accounting for auto_vec and auto_bitmapRichard Biener2-5/+7
This fixes accounting issues with using auto_vec and auto_bitmap for -fmem-report. 2021-02-01 Richard Biener <rguenther@suse.de> * vec.h (auto_vec::auto_vec): Add memory stat parameters and pass them on. * bitmap.h (auto_bitmap::auto_bitmap): Likewise.
2021-02-01Verify a warning for a class with a ref-qualified assignment (PR c++/98835).Martin Sebor1-0/+18
gcc/testsuite/ChangeLog: PR c++/98835 * g++.dg/Wclass-memaccess-6.C: New test.
2021-02-01c++: Fix ICE from verify_ctor_sanity [PR98295]Patrick Palka2-0/+12
In this testcase we're crashing during constexpr evaluation of the ARRAY_REF b[0] as part of evaluation of the lambda's by-copy capture of b (which is encoded as a VEC_INIT_EXPR<b>). Since A's constexpr default constructor is not yet defined, b's initialization is not actually constant, but because A is an empty type, evaluation of b from cxx_eval_array_ref is successful and yields an empty CONSTRUCTOR. And since this CONSTRUCTOR is empty, we {}-initialize the desired array element, and end up crashing from verify_ctor_sanity during evaluation of this initializer because we updated new_ctx.ctor without updating new_ctx.object: the former now has type A[3] and the latter is still the target of a TARGET_EXPR for b[0][0] created from cxx_eval_vec_init (and so has type A). This patch fixes this by setting new_ctx.object appropriately at the same time that we set new_ctx.ctor from cxx_eval_array_reference. gcc/cp/ChangeLog: PR c++/98295 * constexpr.c (cxx_eval_array_reference): Also set new_ctx.object when setting new_ctx.ctor. gcc/testsuite/ChangeLog: PR c++/98295 * g++.dg/cpp0x/constexpr-98295.C: New test.
2021-02-01c++: Improve sorry for __builtin_has_attribute [PR98355]Marek Polacek2-1/+9
__builtin_has_attribute doesn't work in templates yet (bug 92104), so in r11-471 I added a sorry. But that only caught type-dependent expressions and we also want to sorry on value-dependent expressions. This patch uses uses_template_parms, but guarded with p_t_d, because u_t_p sets p_t_d and then v_d_e_p considers variables with reference types value-dependent, which breaks builtin-has-attribute-6.c. This is a regression and I also plan to apply this to gcc-10. gcc/cp/ChangeLog: PR c++/98355 * parser.c (cp_parser_has_attribute_expression): Use uses_template_parms instead of type_dependent_expression_p. gcc/testsuite/ChangeLog: PR c++/98355 * g++.dg/ext/builtin-has-attribute2.C: New test.
2021-02-01c++: alias in qualified-id in template arg [PR98570]Jason Merrill6-37/+53
template_args_equal has handled dependent alias specializations for a while, but in this testcase the actual template argument is a SCOPE_REF, so we called cp_tree_equal, which doesn't handle aliases specially when we get to them. This patch generalizes this by setting a flag so structural_comptypes will check for template alias equivalence (if we aren't doing partial ordering). The existing flag, comparing_specializations, was too broad; in particular, when we're doing decls_match, we want to treat corresponding parameters as equivalent, so we need to separate that from alias comparison. So I introduce the comparing_dependent_aliases flag. From looking at other uses of comparing_specializations, it seems to me that the new flag is what modules wants, as well. The other use of comparing_specializations in structural_comptypes is a hack to deal with spec_hasher::equal not calling push_to_top_level, which we also don't want to tie to the alias comparison semantics. This patch also changes how we get to structural comparison of aliases from checking TYPE_CANONICAL in comptypes to marking the aliases as getting structural comparison when they are built, which is more consistent with how e.g. typename is handled. As I mention in the comment for comparing_dependent_aliases, I think the default should be to treat different dependent aliases for the same type as distinct, only treating them as equal during deduction (particularly partial ordering). But that's a matter for the C++ committee, to try in stage 1. gcc/cp/ChangeLog: PR c++/98570 * cp-tree.h: Declare it. * pt.c (comparing_dependent_aliases): New flag. (template_args_equal, spec_hasher::equal): Set it. (dependent_alias_template_spec_p): Assert that we don't get non-types other than error_mark_node. (instantiate_alias_template): SET_TYPE_STRUCTURAL_EQUALITY on complex alias specializations. Set TYPE_DEPENDENT_P here. (tsubst_decl): Not here. * module.cc (module_state::read_cluster): Set comparing_dependent_aliases instead of comparing_specializations. * tree.c (cp_tree_equal): Remove comparing_specializations module handling. * typeck.c (structural_comptypes): Adjust. (comptypes): Remove comparing_specializations handling. gcc/testsuite/ChangeLog: PR c++/98570 * g++.dg/cpp0x/alias-decl-targ1.C: New test.
2021-02-01testsuite: aarch64: Add tests for vmlXl_high intrinsicsJonathan Wright12-0/+445
Add tests for vmlal_high_* and vmlsl_high_* Neon intrinsics. Since these intrinsics are only supported for AArch64, these tests are restricted to only run on AArch64 targets. gcc/testsuite/ChangeLog: 2021-01-31 Jonathan Wright <jonathan.wright@arm.com> * gcc.target/aarch64/advsimd-intrinsics/vmlXl_high.inc: New test template. * gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_lane.inc: New test template. * gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_laneq.inc: New test template. * gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_n.inc: New test. * gcc.target/aarch64/advsimd-intrinsics/vmlal_high.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vmlal_high_lane.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vmlal_high_laneq.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vmlal_high_n.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vmlsl_high.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_lane.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_laneq.c: New test. * gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_n.c: New test.
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