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[[rv64]] == RV64I Base Integer Instruction Set, Version 2.1 This chapter describes the RV64I base integer instruction set, which builds upon the RV32I variant described in <<rv32>>. This chapter presents only the differences with RV32I, so should be read in conjunction with the earlier chapter. === Register State RV64I widens the integer registers and supported user address space to 64 bits (XLEN=64 in <<gprs>>). === Integer Computational Instructions Most integer computational instructions operate on XLEN-bit values. Additional instruction variants are provided to manipulate 32-bit values in RV64I, indicated by a 'W' suffix to the opcode. These "*W" instructions ignore the upper 32 bits of their inputs and always produce 32-bit signed values, sign-extending them to 64 bits, i.e. bits XLEN-1 through 31 are equal. [NOTE] ==== The compiler and calling convention maintain an invariant that all 32-bit values are held in a sign-extended format in 64-bit registers. Even 32-bit unsigned integers extend bit 31 into bits 63 through 32. Consequently, conversion between unsigned and signed 32-bit integers is a no-op, as is conversion from a signed 32-bit integer to a signed 64-bit integer. Existing 64-bit wide SLTU and unsigned branch compares still operate correctly on unsigned 32-bit integers under this invariant. Similarly, existing 64-bit wide logical operations on 32-bit sign-extended integers preserve the sign-extension property. A few new instructions (ADD[I]W/SUBW/SxxW) are required for addition and shifts to ensure reasonable performance for 32-bit values. ==== (((RV64I, shifts))) (((RV64I, compares))) ==== Integer Register-Immediate Instructions include::images/wavedrom/rv64i-base-int.adoc[] [[rv64i-base-int]] //.RV64I register-immediate instructions ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register _rs1_ and produces the proper sign-extension of a 32-bit result in _rd_. Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits. Note, ADDIW _rd, rs1, 0_ writes the sign-extension of the lower 32 bits of register _rs1_ into register _rd_ (assembler pseudoinstruction SEXT.W). include::images/wavedrom/rv64i-slli.adoc[] [[rv64i-slli]] //.RV64I register-immediate (descr ADDIW) instructions Shifts by a constant are encoded as a specialization of the I-type format using the same instruction opcode as RV32I. The operand to be shifted is in _rs1_, and the shift amount is encoded in the lower 6 bits of the I-immediate field for RV64I. The right shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits). (((RV64I, SLLI))) (((RV64I, SRKIW))) (((RV64I, SRLIW))) (((RV64I, RV64I-only))) include::images/wavedrom/rv64i-slliw.adoc[] [[rv64i-slliw]] SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit


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