diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-protos.h | 2 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 18 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 3 |
6 files changed, 38 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a511670..6bfb0c6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-01-19 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64.c (aarch64_simd_gen_const_vector_dup): + Change int to HOST_WIDE_INT. + * config/aarch64/aarch64-protos.h + (aarch64_simd_gen_const_vector_dup): Likewise. + * config/aarch64/aarch64-simd.md: Add copysign<mode>3. + 2017-01-19 David Malcolm <dmalcolm@redhat.com> * langhooks-def.h (lhd_type_for_size): New decl. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 8c4380b..7a9a21ea 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -362,7 +362,7 @@ rtx aarch64_eh_return_handler_rtx (void); rtx aarch64_mask_from_zextract_ops (rtx, rtx); const char *aarch64_output_move_struct (rtx *operands); rtx aarch64_return_addr (int, rtx); -rtx aarch64_simd_gen_const_vector_dup (machine_mode, int); +rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT); bool aarch64_simd_mem_operand_p (rtx); rtx aarch64_simd_vect_par_cnst_half (machine_mode, bool); rtx aarch64_tls_get_addr (void); diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index a12e226..b61f79a 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -338,6 +338,24 @@ } ) +(define_expand "copysign<mode>3" + [(match_operand:VHSDF 0 "register_operand") + (match_operand:VHSDF 1 "register_operand") + (match_operand:VHSDF 2 "register_operand")] + "TARGET_FLOAT && TARGET_SIMD" +{ + rtx v_bitmask = gen_reg_rtx (<V_cmp_result>mode); + int bits = GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1; + + emit_move_insn (v_bitmask, + aarch64_simd_gen_const_vector_dup (<V_cmp_result>mode, + HOST_WIDE_INT_M1U << bits)); + emit_insn (gen_aarch64_simd_bsl<mode> (operands[0], v_bitmask, + operands[2], operands[1])); + DONE; +} +) + (define_insn "*aarch64_mul3_elt<mode>" [(set (match_operand:VMUL 0 "register_operand" "=w") (mult:VMUL diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 39a5880..4432cae 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -11237,14 +11237,16 @@ aarch64_mov_operand_p (rtx x, machine_mode mode) /* Return a const_int vector of VAL. */ rtx -aarch64_simd_gen_const_vector_dup (machine_mode mode, int val) +aarch64_simd_gen_const_vector_dup (machine_mode mode, HOST_WIDE_INT val) { int nunits = GET_MODE_NUNITS (mode); rtvec v = rtvec_alloc (nunits); int i; + rtx cache = GEN_INT (val); + for (i=0; i < nunits; i++) - RTVEC_ELT (v, i) = GEN_INT (val); + RTVEC_ELT (v, i) = cache; return gen_rtx_CONST_VECTOR (mode, v); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 662fbc5..1a3a521 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-01-19 Tamar Christina <tamar.christina@arm.com> + + * gcc/testsuite/lib/target-supports.exp + (check_effective_target_vect_call_copysignf): Enable for AArch64. + 2017-01-19 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> PR testsuite/79051 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index b88d13c..12dbf47 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6158,7 +6158,8 @@ proc check_effective_target_vect_call_copysignf { } { } else { set et_vect_call_copysignf_saved($et_index) 0 if { [istarget i?86-*-*] || [istarget x86_64-*-*] - || [istarget powerpc*-*-*] } { + || [istarget powerpc*-*-*] + || [istarget aarch64*-*-*] } { set et_vect_call_copysignf_saved($et_index) 1 } } |