diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/genrvv-type-indexer.cc | 3 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-modes.def | 15 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins-types.def | 25 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-vector-builtins.def | 30 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-vector-switch.def | 32 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.md | 5 | ||||
| -rw-r--r-- | gcc/config/riscv/vector-iterators.md | 37 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/tuple-28.c | 59 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/tuple-29.c | 59 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/tuple-30.c | 58 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/tuple-31.c | 30 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/tuple-32.c | 16 |
12 files changed, 366 insertions, 3 deletions
diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc index 8fc93ce..a332a6a 100644 --- a/gcc/config/riscv/genrvv-type-indexer.cc +++ b/gcc/config/riscv/genrvv-type-indexer.cc @@ -73,9 +73,6 @@ valid_type (unsigned sew, int lmul_log2, unsigned nf, bool float_p) if (nf > 8 || nf < 1) return false; - if (sew == 16 && nf != 1 && float_p) // Disable FP16 tuple in temporarily. - return false; - switch (lmul_log2) { case 1: diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index 19a4f9f..1d15270 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -220,6 +220,7 @@ ADJUST_ALIGNMENT (VNx1QI, 1); #define RVV_TUPLE_MODES(NBYTES, NSUBPARTS, VB, VH, VS, VD) \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, NBYTES, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, NBYTES / 2, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, NBYTES / 2, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, SI, NBYTES / 4, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, SF, NBYTES / 4, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, DI, NBYTES / 8, 1); \ @@ -236,6 +237,9 @@ ADJUST_ALIGNMENT (VNx1QI, 1); ADJUST_NUNITS (VNx##NSUBPARTS##x##VD##DI, \ riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VD##DI##mode, \ VD * NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x##VH##HF, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VH##HF##mode, \ + VH * NSUBPARTS)); \ ADJUST_NUNITS (VNx##NSUBPARTS##x##VS##SF, \ riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VS##SF##mode, \ VS * NSUBPARTS)); \ @@ -247,6 +251,7 @@ ADJUST_ALIGNMENT (VNx1QI, 1); ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VH##HI, 2); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VS##SI, 4); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VD##DI, 8); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VH##HF, 2); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VS##SF, 4); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VD##DF, 8); @@ -275,10 +280,12 @@ RVV_TUPLE_MODES (64, 2, 64, 32, 16, 8) #define RVV_TUPLE_PARTIAL_MODES(NSUBPARTS) \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 1, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, 1, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, 1, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, SI, 1, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, SF, 1, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 2, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, 2, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, 2, 1); \ VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 4, 1); \ \ ADJUST_NUNITS (VNx##NSUBPARTS##x1QI, \ @@ -287,6 +294,9 @@ RVV_TUPLE_MODES (64, 2, 64, 32, 16, 8) ADJUST_NUNITS (VNx##NSUBPARTS##x1HI, \ riscv_v_adjust_nunits (VNx##NSUBPARTS##x1HI##mode, \ NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x1HF, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x1HF##mode, \ + NSUBPARTS)); \ ADJUST_NUNITS (VNx##NSUBPARTS##x1SI, \ riscv_v_adjust_nunits (VNx##NSUBPARTS##x1SI##mode, \ NSUBPARTS)); \ @@ -299,15 +309,20 @@ RVV_TUPLE_MODES (64, 2, 64, 32, 16, 8) ADJUST_NUNITS (VNx##NSUBPARTS##x2HI, \ riscv_v_adjust_nunits (VNx##NSUBPARTS##x2HI##mode, \ 2 * NSUBPARTS)); \ +ADJUST_NUNITS (VNx##NSUBPARTS##x2HF, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x2HF##mode, \ + 2 * NSUBPARTS)); \ ADJUST_NUNITS (VNx##NSUBPARTS##x4QI, \ riscv_v_adjust_nunits (VNx##NSUBPARTS##x4QI##mode, \ 4 * NSUBPARTS)); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1QI, 1); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1HI, 2); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1HF, 2); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1SI, 4); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1SF, 4); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2QI, 1); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2HI, 2); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2HF, 2); \ ADJUST_ALIGNMENT (VNx##NSUBPARTS##x4QI, 1); RVV_TUPLE_PARTIAL_MODES (2) diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def index 4926bd8..1c3cc0e 100644 --- a/gcc/config/riscv/riscv-vector-builtins-types.def +++ b/gcc/config/riscv/riscv-vector-builtins-types.def @@ -1291,6 +1291,31 @@ DEF_RVV_TUPLE_OPS (vint64m2x4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_TUPLE_OPS (vuint64m2x4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_TUPLE_OPS (vint64m4x2_t, RVV_REQUIRE_ELEN_64) DEF_RVV_TUPLE_OPS (vuint64m4x2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_TUPLE_OPS (vfloat16mf4x2_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vfloat16mf4x3_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vfloat16mf4x4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vfloat16mf4x5_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vfloat16mf4x6_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vfloat16mf4x7_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vfloat16mf4x8_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vfloat16mf2x2_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16mf2x3_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16mf2x4_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16mf2x5_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16mf2x6_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16mf2x7_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16mf2x8_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m1x2_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m1x3_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m1x4_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m1x5_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m1x6_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m1x7_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m1x8_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m2x2_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m2x3_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m2x4_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_TUPLE_OPS (vfloat16m4x2_t, RVV_REQUIRE_ELEN_FP_16) DEF_RVV_TUPLE_OPS (vfloat32mf2x2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_TUPLE_OPS (vfloat32mf2x3_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_TUPLE_OPS (vfloat32mf2x4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64) diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 310edea..1e94579 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -494,18 +494,48 @@ DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, VNx16DI, VNx8DI, VOID, /* LMUL = 1/4. */ DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, VNx2HF, VNx1HF, VOID, _f16mf4, _f16, _e16mf4) +/* Define tuple types for SEW = 16, LMUL = MF4. */ +DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t, float, 2, _f16mf4x2) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t, float, 3, _f16mf4x3) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t, float, 4, _f16mf4x4) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t, float, 5, _f16mf4x5) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t, float, 6, _f16mf4x6) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t, float, 7, _f16mf4x7) +DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t, float, 8, _f16mf4x8) /* LMUL = 1/2. */ DEF_RVV_TYPE (vfloat16mf2_t, 18, __rvv_float16mf2_t, float16, VNx4HF, VNx2HF, VNx1HF, _f16mf2, _f16, _e16mf2) +/* Define tuple types for SEW = 16, LMUL = MF2. */ +DEF_RVV_TUPLE_TYPE (vfloat16mf2x2_t, 20, __rvv_float16mf2x2_t, vfloat16mf2_t, float, 2, _f16mf2x2) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x3_t, 20, __rvv_float16mf2x3_t, vfloat16mf2_t, float, 3, _f16mf2x3) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x4_t, 20, __rvv_float16mf2x4_t, vfloat16mf2_t, float, 4, _f16mf2x4) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x5_t, 20, __rvv_float16mf2x5_t, vfloat16mf2_t, float, 5, _f16mf2x5) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x6_t, 20, __rvv_float16mf2x6_t, vfloat16mf2_t, float, 6, _f16mf2x6) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x7_t, 20, __rvv_float16mf2x7_t, vfloat16mf2_t, float, 7, _f16mf2x7) +DEF_RVV_TUPLE_TYPE (vfloat16mf2x8_t, 20, __rvv_float16mf2x8_t, vfloat16mf2_t, float, 8, _f16mf2x8) /* LMUL = 1. */ DEF_RVV_TYPE (vfloat16m1_t, 17, __rvv_float16m1_t, float16, VNx8HF, VNx4HF, VNx2HF, _f16m1, _f16, _e16m1) +/* Define tuple types for SEW = 16, LMUL = M1. */ +DEF_RVV_TUPLE_TYPE (vfloat16m1x2_t, 19, __rvv_float16m1x2_t, vfloat16m1_t, float, 2, _f16m1x2) +DEF_RVV_TUPLE_TYPE (vfloat16m1x3_t, 19, __rvv_float16m1x3_t, vfloat16m1_t, float, 3, _f16m1x3) +DEF_RVV_TUPLE_TYPE (vfloat16m1x4_t, 19, __rvv_float16m1x4_t, vfloat16m1_t, float, 4, _f16m1x4) +DEF_RVV_TUPLE_TYPE (vfloat16m1x5_t, 19, __rvv_float16m1x5_t, vfloat16m1_t, float, 5, _f16m1x5) +DEF_RVV_TUPLE_TYPE (vfloat16m1x6_t, 19, __rvv_float16m1x6_t, vfloat16m1_t, float, 6, _f16m1x6) +DEF_RVV_TUPLE_TYPE (vfloat16m1x7_t, 19, __rvv_float16m1x7_t, vfloat16m1_t, float, 7, _f16m1x7) +DEF_RVV_TUPLE_TYPE (vfloat16m1x8_t, 19, __rvv_float16m1x8_t, vfloat16m1_t, float, 8, _f16m1x8) /* LMUL = 2. */ DEF_RVV_TYPE (vfloat16m2_t, 17, __rvv_float16m2_t, float16, VNx16HF, VNx8HF, VNx4HF, _f16m2, _f16, _e16m2) +/* Define tuple types for SEW = 16, LMUL = M2. */ +DEF_RVV_TUPLE_TYPE (vfloat16m2x2_t, 19, __rvv_float16m2x2_t, vfloat16m2_t, float, 2, _f16m2x2) +DEF_RVV_TUPLE_TYPE (vfloat16m2x3_t, 19, __rvv_float16m2x3_t, vfloat16m2_t, float, 3, _f16m2x3) +DEF_RVV_TUPLE_TYPE (vfloat16m2x4_t, 19, __rvv_float16m2x4_t, vfloat16m2_t, float, 4, _f16m2x4) /* LMUL = 4. */ DEF_RVV_TYPE (vfloat16m4_t, 17, __rvv_float16m4_t, float16, VNx32HF, VNx16HF, VNx8HF, _f16m4, _f16, _e16m4) +/* Define tuple types for SEW = 16, LMUL = M4. */ +DEF_RVV_TUPLE_TYPE (vfloat16m4x2_t, 19, __rvv_float16m4x2_t, vfloat16m4_t, float, 2, _f16m4x2) /* LMUL = 8. */ DEF_RVV_TYPE (vfloat16m8_t, 16, __rvv_float16m8_t, float16, VNx64HF, VNx32HF, VNx16HF, _f16m8, _f16, _e16m8) diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index 52f07709..7f14891 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -248,6 +248,38 @@ TUPLE_ENTRY (VNx5x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 5, LMUL_F2, 32, LMUL_F4, 6 TUPLE_ENTRY (VNx6x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 6, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) TUPLE_ENTRY (VNx7x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 7, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) TUPLE_ENTRY (VNx8x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 8, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx2x32HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx32HF, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 4) +TUPLE_ENTRY (VNx2x16HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx16HF, 2, LMUL_RESERVED, 0, LMUL_4, 4, LMUL_2, 8) +TUPLE_ENTRY (VNx3x16HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx16HF, 3, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 8) +TUPLE_ENTRY (VNx4x16HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx16HF, 4, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 8) +TUPLE_ENTRY (VNx2x8HF, TARGET_VECTOR_ELEN_FP_16, VNx8HF, 2, LMUL_4, 4, LMUL_2, 8, LMUL_1, 16) +TUPLE_ENTRY (VNx3x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx8HF, 3, LMUL_RESERVED, 0, LMUL_2, 8, LMUL_1, 16) +TUPLE_ENTRY (VNx4x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx8HF, 4, LMUL_RESERVED, 0, LMUL_2, 8, LMUL_1, 16) +TUPLE_ENTRY (VNx5x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx8HF, 5, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16) +TUPLE_ENTRY (VNx6x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx8HF, 6, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16) +TUPLE_ENTRY (VNx7x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx8HF, 7, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16) +TUPLE_ENTRY (VNx8x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx8HF, 8, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16) +TUPLE_ENTRY (VNx2x4HF, TARGET_VECTOR_ELEN_FP_16, VNx4HF, 2, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx3x4HF, TARGET_VECTOR_ELEN_FP_16, VNx4HF, 3, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx4x4HF, TARGET_VECTOR_ELEN_FP_16, VNx4HF, 4, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx5x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx4HF, 5, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx6x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx4HF, 6, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx7x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx4HF, 7, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx8x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx4HF, 8, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx2x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 2, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx3x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 3, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx4x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 4, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx5x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 5, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx6x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 6, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx7x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 7, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx8x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 8, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx2x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 2, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx3x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 3, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx4x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 4, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx5x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 5, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx6x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 6, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx7x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 7, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx8x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 8, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) /* Tuple modes for EEW = 32. */ TUPLE_ENTRY (VNx2x16SI, TARGET_MIN_VLEN >= 128, VNx16SI, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 8) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d8e935c..c2fe4c6 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -189,6 +189,11 @@ VNx2x4HI,VNx3x4HI,VNx4x4HI,VNx5x4HI,VNx6x4HI,VNx7x4HI,VNx8x4HI, VNx2x2HI,VNx3x2HI,VNx4x2HI,VNx5x2HI,VNx6x2HI,VNx7x2HI,VNx8x2HI, VNx2x1HI,VNx3x1HI,VNx4x1HI,VNx5x1HI,VNx6x1HI,VNx7x1HI,VNx8x1HI, + VNx2x32HF,VNx2x16HF,VNx3x16HF,VNx4x16HF, + VNx2x8HF,VNx3x8HF,VNx4x8HF,VNx5x8HF,VNx6x8HF,VNx7x8HF,VNx8x8HF, + VNx2x4HF,VNx3x4HF,VNx4x4HF,VNx5x4HF,VNx6x4HF,VNx7x4HF,VNx8x4HF, + VNx2x2HF,VNx3x2HF,VNx4x2HF,VNx5x2HF,VNx6x2HF,VNx7x2HF,VNx8x2HF, + VNx2x1HF,VNx3x1HF,VNx4x1HF,VNx5x1HF,VNx6x1HF,VNx7x1HF,VNx8x1HF, VNx2x16SI,VNx2x8SI,VNx3x8SI,VNx4x8SI, VNx2x4SI,VNx3x4SI,VNx4x4SI,VNx5x4SI,VNx6x4SI,VNx7x4SI,VNx8x4SI, VNx2x2SI,VNx3x2SI,VNx4x2SI,VNx5x2SI,VNx6x2SI,VNx7x2SI,VNx8x2SI, diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index e2c8ade..a5a660e 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -660,6 +660,38 @@ (VNx6x1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx7x1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx8x1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") + (VNx2x32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx2x16HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (VNx3x16HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx4x16HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx2x8HF "TARGET_VECTOR_ELEN_FP_16") + (VNx3x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (VNx4x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (VNx5x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx6x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx7x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx8x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128") + (VNx2x4HF "TARGET_VECTOR_ELEN_FP_16") + (VNx3x4HF "TARGET_VECTOR_ELEN_FP_16") + (VNx4x4HF "TARGET_VECTOR_ELEN_FP_16") + (VNx5x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (VNx6x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (VNx7x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (VNx8x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64") + (VNx2x2HF "TARGET_VECTOR_ELEN_FP_16") + (VNx3x2HF "TARGET_VECTOR_ELEN_FP_16") + (VNx4x2HF "TARGET_VECTOR_ELEN_FP_16") + (VNx5x2HF "TARGET_VECTOR_ELEN_FP_16") + (VNx6x2HF "TARGET_VECTOR_ELEN_FP_16") + (VNx7x2HF "TARGET_VECTOR_ELEN_FP_16") + (VNx8x2HF "TARGET_VECTOR_ELEN_FP_16") + (VNx2x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx3x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx4x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx5x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx6x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx7x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx8x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") (VNx2x16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") (VNx2x8SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") (VNx3x8SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@ -1086,6 +1118,11 @@ (VNx2x8DI "VNx8BI") (VNx2x4DI "VNx4BI") (VNx3x4DI "VNx4BI") (VNx4x4DI "VNx4BI") (VNx2x2DI "VNx2BI") (VNx3x2DI "VNx2BI") (VNx4x2DI "VNx2BI") (VNx5x2DI "VNx2BI") (VNx6x2DI "VNx2BI") (VNx7x2DI "VNx2BI") (VNx8x2DI "VNx2BI") (VNx2x1DI "VNx1BI") (VNx3x1DI "VNx1BI") (VNx4x1DI "VNx1BI") (VNx5x1DI "VNx1BI") (VNx6x1DI "VNx1BI") (VNx7x1DI "VNx1BI") (VNx8x1DI "VNx1BI") + (VNx2x32HF "VNx32BI") (VNx2x16HF "VNx16BI") (VNx3x16HF "VNx16BI") (VNx4x16HF "VNx16BI") + (VNx2x8HF "VNx8BI") (VNx3x8HF "VNx8BI") (VNx4x8HF "VNx8BI") (VNx5x8HF "VNx8BI") (VNx6x8HF "VNx8BI") (VNx7x8HF "VNx8BI") (VNx8x8HF "VNx8BI") + (VNx2x4HF "VNx4BI") (VNx3x4HF "VNx4BI") (VNx4x4HF "VNx4BI") (VNx5x4HF "VNx4BI") (VNx6x4HF "VNx4BI") (VNx7x4HF "VNx4BI") (VNx8x4HF "VNx4BI") + (VNx2x2HF "VNx2BI") (VNx3x2HF "VNx2BI") (VNx4x2HF "VNx2BI") (VNx5x2HF "VNx2BI") (VNx6x2HF "VNx2BI") (VNx7x2HF "VNx2BI") (VNx8x2HF "VNx2BI") + (VNx2x1HF "VNx1BI") (VNx3x1HF "VNx1BI") (VNx4x1HF "VNx1BI") (VNx5x1HF "VNx1BI") (VNx6x1HF "VNx1BI") (VNx7x1HF "VNx1BI") (VNx8x1HF "VNx1BI") (VNx2x16SF "VNx16BI") (VNx2x8SF "VNx8BI") (VNx3x8SF "VNx8BI") (VNx4x8SF "VNx8BI") (VNx2x4SF "VNx4BI") (VNx3x4SF "VNx4BI") (VNx4x4SF "VNx4BI") (VNx5x4SF "VNx4BI") (VNx6x4SF "VNx4BI") (VNx7x4SF "VNx4BI") (VNx8x4SF "VNx4BI") (VNx2x2SF "VNx2BI") (VNx3x2SF "VNx2BI") (VNx4x2SF "VNx2BI") (VNx5x2SF "VNx2BI") (VNx6x2SF "VNx2BI") (VNx7x2SF "VNx2BI") (VNx8x2SF "VNx2BI") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-28.c new file mode 100644 index 0000000..f36129e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-28.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void +f_vfloat16mf4x2_t (void *base, void *out) +{ + vfloat16mf4x2_t v = *(vfloat16mf4x2_t*)base; + *(vfloat16mf4x2_t*)out = v; +} + +void +f_vfloat16mf4x3_t (void *base, void *out) +{ + vfloat16mf4x3_t v = *(vfloat16mf4x3_t*)base; + *(vfloat16mf4x3_t*)out = v; +} + +void +f_vfloat16mf4x4_t (void *base, void *out) +{ + vfloat16mf4x4_t v = *(vfloat16mf4x4_t*)base; + *(vfloat16mf4x4_t*)out = v; +} + +void +f_vfloat16mf4x5_t (void *base, void *out) +{ + vfloat16mf4x5_t v = *(vfloat16mf4x5_t*)base; + *(vfloat16mf4x5_t*)out = v; +} + +void +f_vfloat16mf4x6_t (void *base, void *out) +{ + vfloat16mf4x6_t v = *(vfloat16mf4x6_t*)base; + *(vfloat16mf4x6_t*)out = v; +} + +void +f_vfloat16mf4x7_t (void *base, void *out) +{ + vfloat16mf4x7_t v = *(vfloat16mf4x7_t*)base; + *(vfloat16mf4x7_t*)out = v; +} + +void +f_vfloat16mf4x8_t (void *base, void *out) +{ + vfloat16mf4x8_t v = *(vfloat16mf4x8_t*)base; + *(vfloat16mf4x8_t*)out = v; +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 7 } } */ +/* { dg-final { scan-assembler {srai} } } */ +/* { dg-final { scan-assembler-not {slli} } } */ +/* { dg-final { scan-assembler-times {vle16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */ +/* { dg-final { scan-assembler-times {vse16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-29.c new file mode 100644 index 0000000..c6807c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-29.c @@ -0,0 +1,59 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void +f_vfloat16mf2x2_t (void *base, void *out) +{ + vfloat16mf2x2_t v = *(vfloat16mf2x2_t*)base; + *(vfloat16mf2x2_t*)out = v; +} + +void +f_vfloat16mf2x3_t (void *base, void *out) +{ + vfloat16mf2x3_t v = *(vfloat16mf2x3_t*)base; + *(vfloat16mf2x3_t*)out = v; +} + +void +f_vfloat16mf2x4_t (void *base, void *out) +{ + vfloat16mf2x4_t v = *(vfloat16mf2x4_t*)base; + *(vfloat16mf2x4_t*)out = v; +} + +void +f_vfloat16mf2x5_t (void *base, void *out) +{ + vfloat16mf2x5_t v = *(vfloat16mf2x5_t*)base; + *(vfloat16mf2x5_t*)out = v; +} + +void +f_vfloat16mf2x6_t (void *base, void *out) +{ + vfloat16mf2x6_t v = *(vfloat16mf2x6_t*)base; + *(vfloat16mf2x6_t*)out = v; +} + +void +f_vfloat16mf2x7_t (void *base, void *out) +{ + vfloat16mf2x7_t v = *(vfloat16mf2x7_t*)base; + *(vfloat16mf2x7_t*)out = v; +} + +void +f_vfloat16mf2x8_t (void *base, void *out) +{ + vfloat16mf2x8_t v = *(vfloat16mf2x8_t*)base; + *(vfloat16mf2x8_t*)out = v; +} + +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 7 } } */ +/* { dg-final { scan-assembler {srai} } } */ +/* { dg-final { scan-assembler-not {slli} } } */ +/* { dg-final { scan-assembler-times {vle16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */ +/* { dg-final { scan-assembler-times {vse16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-30.c new file mode 100644 index 0000000..dd4de3c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-30.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void +f_vfloat16m1x2_t (void *base, void *out) +{ + vfloat16m1x2_t v = *(vfloat16m1x2_t*)base; + *(vfloat16m1x2_t*)out = v; +} + +void +f_vfloat16m1x3_t (void *base, void *out) +{ + vfloat16m1x3_t v = *(vfloat16m1x3_t*)base; + *(vfloat16m1x3_t*)out = v; +} + +void +f_vfloat16m1x4_t (void *base, void *out) +{ + vfloat16m1x4_t v = *(vfloat16m1x4_t*)base; + *(vfloat16m1x4_t*)out = v; +} + +void +f_vfloat16m1x5_t (void *base, void *out) +{ + vfloat16m1x5_t v = *(vfloat16m1x5_t*)base; + *(vfloat16m1x5_t*)out = v; +} + +void +f_vfloat16m1x6_t (void *base, void *out) +{ + vfloat16m1x6_t v = *(vfloat16m1x6_t*)base; + *(vfloat16m1x6_t*)out = v; +} + +void +f_vfloat16m1x7_t (void *base, void *out) +{ + vfloat16m1x7_t v = *(vfloat16m1x7_t*)base; + *(vfloat16m1x7_t*)out = v; +} + +void +f_vfloat16m1x8_t (void *base, void *out) +{ + vfloat16m1x8_t v = *(vfloat16m1x8_t*)base; + *(vfloat16m1x8_t*)out = v; +} + +/* { dg-final { scan-assembler-not {srai} } } */ +/* { dg-final { scan-assembler-not {slli} } } */ +/* { dg-final { scan-assembler-times {vl1re16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */ +/* { dg-final { scan-assembler-times {vs1r\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-31.c new file mode 100644 index 0000000..48b084e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-31.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void +f_vfloat16m2x2_t (void *base, void *out) +{ + vfloat16m2x2_t v = *(vfloat16m2x2_t*)base; + *(vfloat16m2x2_t*)out = v; +} + +void +f_vfloat16m2x3_t (void *base, void *out) +{ + vfloat16m2x3_t v = *(vfloat16m2x3_t*)base; + *(vfloat16m2x3_t*)out = v; +} + +void +f_vfloat16m2x4_t (void *base, void *out) +{ + vfloat16m2x4_t v = *(vfloat16m2x4_t*)base; + *(vfloat16m2x4_t*)out = v; +} + +/* { dg-final { scan-assembler-not {srai} } } */ +/* { dg-final { scan-assembler {slli} } } */ +/* { dg-final { scan-assembler-times {vl2re16\.v\tv[0-9]+,0\([a-x0-9]+\)} 9 } } */ +/* { dg-final { scan-assembler-times {vs2r\.v\tv[0-9]+,0\([a-x0-9]+\)} 9 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-32.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-32.c new file mode 100644 index 0000000..90693d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-32.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void +f_vfloat16m4x2_t (void *base, void *out) +{ + vfloat16m4x2_t v = *(vfloat16m4x2_t*)base; + *(vfloat16m4x2_t*)out = v; +} + +/* { dg-final { scan-assembler-not {srai} } } */ +/* { dg-final { scan-assembler {slli} } } */ +/* { dg-final { scan-assembler-times {vl4re16\.v\tv[0-9]+,0\([a-x0-9]+\)} 2 } } */ +/* { dg-final { scan-assembler-times {vs4r\.v\tv[0-9]+,0\([a-x0-9]+\)} 2 } } */
\ No newline at end of file |