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-rw-r--r--gcc/ChangeLog17
-rw-r--r--gcc/config/mips/mips.c10
-rw-r--r--gcc/config/mips/mips.h3
-rw-r--r--gcc/config/mips/mips.md38
-rw-r--r--gcc/testsuite/ChangeLog10
-rw-r--r--gcc/testsuite/gcc.target/mips/octeon-seq-1.c19
-rw-r--r--gcc/testsuite/gcc.target/mips/octeon-seq-2.c15
-rw-r--r--gcc/testsuite/gcc.target/mips/octeon-seq-3.c13
-rw-r--r--gcc/testsuite/gcc.target/mips/octeon-seq-4.c13
-rw-r--r--gcc/testsuite/gcc.target/mips/scc-2.c2
-rw-r--r--gcc/testsuite/gcc.target/mips/scc-3.c2
-rw-r--r--gcc/testsuite/gcc.target/mips/seq-1.c10
12 files changed, 142 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d035a4b..531589d0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,22 @@
2008-09-04 Adam Nemet <anemet@caviumnetworks.com>
+ * config/mips/mips.h (ISA_HAS_SEQ_SNE): New macro.
+ * config/mips/mips.c (mips_expand_scc): Also expand seq and sne if
+ second operand is a reg_imm10_operand.
+ * config/mips/mips.md (*seq_<GPR:mode><GPR2:mode>_seq,
+ *sne_<GPR:mode><GPR2:mode>_sne): New patterns.
+ (*seq_<GPR:mode><GPR2:mode>): Rename to
+ *seq_zero_<GPR:mode><GPR2:mode>. Don't match if
+ ISA_HAS_SEQ_SNE.
+ (*seq_<GPR:mode><GPR2:mode>_mips16): Rename to
+ *seq_zero_<GPR:mode><GPR2:mode>_mip16. Don't match if
+ ISA_HAS_SEQ_SNE.
+ (*sne_<GPR:mode><GPR2:mode>): Rename to
+ *sne_zero_<GPR:mode><GPR2:mode>. Don't match if
+ ISA_HAS_SEQ_SNE.
+
+2008-09-04 Adam Nemet <anemet@caviumnetworks.com>
+
* config/mips/mips.h (ISA_HAS_EXTS): New macro.
* config/mips/mips.md (*ashr_trunc<mode>): Name the pattern
combining an arithmetic right shift by more than 31 and a
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 911f93c..fd0101b 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -4222,8 +4222,14 @@ mips_expand_scc (enum rtx_code code, rtx target)
if (code == EQ || code == NE)
{
- rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
- mips_emit_binary (code, target, zie, const0_rtx);
+ if (ISA_HAS_SEQ_SNE
+ && reg_imm10_operand (cmp_operands[1], GET_MODE (cmp_operands[1])))
+ mips_emit_binary (code, target, cmp_operands[0], cmp_operands[1]);
+ else
+ {
+ rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
+ mips_emit_binary (code, target, zie, const0_rtx);
+ }
}
else
mips_emit_int_order_test (code, 0, target,
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 4677546..1a9b542 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1015,6 +1015,9 @@ enum mips_code_readable_setting {
/* ISA includes the exts instruction. */
#define ISA_HAS_EXTS TARGET_OCTEON
+/* ISA includes the seq and sne instructions. */
+#define ISA_HAS_SEQ_SNE TARGET_OCTEON
+
/* ISA includes the pop instruction. */
#define ISA_HAS_POP TARGET_OCTEON
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 0f478cf..0512a70 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -5200,24 +5200,37 @@
""
{ if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
-(define_insn "*seq_<GPR:mode><GPR2:mode>"
+(define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
[(set (match_operand:GPR2 0 "register_operand" "=d")
(eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
(const_int 0)))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
"sltu\t%0,%1,1"
[(set_attr "type" "slt")
(set_attr "mode" "<GPR:MODE>")])
-(define_insn "*seq_<GPR:mode><GPR2:mode>_mips16"
+(define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
[(set (match_operand:GPR2 0 "register_operand" "=t")
(eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
(const_int 0)))]
- "TARGET_MIPS16"
+ "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
"sltu\t%1,1"
[(set_attr "type" "slt")
(set_attr "mode" "<GPR:MODE>")])
+;; Generate sltiu unless using seq results in better code.
+(define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
+ [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
+ (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
+ (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
+ "ISA_HAS_SEQ_SNE"
+ "@
+ seq\t%0,%1,%2
+ sltiu\t%0,%1,1
+ seqi\t%0,%1,%2"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
+
;; "sne" uses sltu instructions in which the first operand is $0.
;; This isn't possible in mips16 code.
@@ -5228,15 +5241,28 @@
"!TARGET_MIPS16"
{ if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
-(define_insn "*sne_<GPR:mode><GPR2:mode>"
+(define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
[(set (match_operand:GPR2 0 "register_operand" "=d")
(ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
(const_int 0)))]
- "!TARGET_MIPS16"
+ "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
"sltu\t%0,%.,%1"
[(set_attr "type" "slt")
(set_attr "mode" "<GPR:MODE>")])
+;; Generate sltu unless using sne results in better code.
+(define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
+ [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
+ (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
+ (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
+ "ISA_HAS_SEQ_SNE"
+ "@
+ sne\t%0,%1,%2
+ sltu\t%0,%.,%1
+ snei\t%0,%1,%2"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
+
(define_expand "sgt<u>"
[(set (match_operand:SI 0 "register_operand")
(any_gt:SI (match_dup 1)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9eeb9cc..e2e111f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,15 @@
2008-09-04 Adam Nemet <anemet@caviumnetworks.com>
+ * gcc.target/mips/seq-1.c: New test.
+ * gcc.target/mips/octeon-seq-1.c: New test.
+ * gcc.target/mips/octeon-seq-2.c: New test.
+ * gcc.target/mips/octeon-seq-3.c: New test.
+ * gcc.target/mips/octeon-seq-4.c: New test.
+ * gcc.target/mips/scc-2.c: Also pass on sltiu.
+ * gcc.target/mips/scc-3.c: Likewise.
+
+2008-09-04 Adam Nemet <anemet@caviumnetworks.com>
+
* gcc.target/mips/truncate-2.c: New test.
* gcc.target/mips/octeon-exts-1.c: New test.
* gcc.target/mips/octeon-exts-2.c: New test.
diff --git a/gcc/testsuite/gcc.target/mips/octeon-seq-1.c b/gcc/testsuite/gcc.target/mips/octeon-seq-1.c
new file mode 100644
index 0000000..3199cd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/octeon-seq-1.c
@@ -0,0 +1,19 @@
+/* Check if we expand seq and sne. */
+
+/* { dg-do compile } */
+/* { dg-mips-options "-march=octeon" } */
+/* { dg-final { scan-assembler-times "\tseq\t|\tseqi\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tsne\t|\tsnei\t" 4 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+ NOMIPS16 int f##N (int a, int b) { return LHS REL RHS; }
+
+TEST (0, a, ==, b);
+TEST (1, a, ==, 23);
+TEST (2, a, ==, 511);
+TEST (3, a, ==, -200);
+
+TEST (10, a, !=, b);
+TEST (11, a, !=, 1);
+TEST (12, a, !=, 350);
+TEST (13, a, !=, -512);
diff --git a/gcc/testsuite/gcc.target/mips/octeon-seq-2.c b/gcc/testsuite/gcc.target/mips/octeon-seq-2.c
new file mode 100644
index 0000000..994e51b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/octeon-seq-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-march=octeon -mgp64" } */
+/* { dg-final { scan-assembler-times "\tseq\t|\tseqi\t" 3 } } */
+/* { dg-final { scan-assembler-times "\tsne\t|\tsnei\t" 3 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+ NOMIPS16 long long f##N (long long a, long long b) { return LHS REL RHS; }
+
+TEST (0, a, ==, b);
+TEST (1, a, ==, 23);
+TEST (2, a, ==, 511);
+
+TEST (3, a, !=, b);
+TEST (4, a, !=, 1);
+TEST (5, a, !=, 350);
diff --git a/gcc/testsuite/gcc.target/mips/octeon-seq-3.c b/gcc/testsuite/gcc.target/mips/octeon-seq-3.c
new file mode 100644
index 0000000..522d0ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/octeon-seq-3.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-O -march=octeon -mgp64" } */
+
+/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */
+/* { dg-final { scan-assembler-times "\tseqi\t\|\tsnei\t" 4 } } */
+
+
+#define TEST(N, LHS, REL, RHS) \
+ NOMIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \
+ NOMIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \
+
+TEST (eq, a, ==, 10);
+TEST (ne, a, !=, 32);
diff --git a/gcc/testsuite/gcc.target/mips/octeon-seq-4.c b/gcc/testsuite/gcc.target/mips/octeon-seq-4.c
new file mode 100644
index 0000000..88a7100
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/octeon-seq-4.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-O2 -march=octeon" } */
+/* { dg-final { scan-assembler-not "xor" } } */
+
+unsigned
+m (unsigned e);
+
+NOMIPS16 void
+f (unsigned i)
+{
+ unsigned j = m (i);
+ h (j, i != j);
+}
diff --git a/gcc/testsuite/gcc.target/mips/scc-2.c b/gcc/testsuite/gcc.target/mips/scc-2.c
index 7964227..c6c79d8 100644
--- a/gcc/testsuite/gcc.target/mips/scc-2.c
+++ b/gcc/testsuite/gcc.target/mips/scc-2.c
@@ -2,7 +2,7 @@
/* { dg-mips-options "-O -mgp64" } */
/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */
-/* { dg-final { scan-assembler-times "slt\t\|sltu\t" 12 } } */
+/* { dg-final { scan-assembler-times "slt\t\|slti?u\t" 12 } } */
#define TEST(N, LHS, REL, RHS) \
diff --git a/gcc/testsuite/gcc.target/mips/scc-3.c b/gcc/testsuite/gcc.target/mips/scc-3.c
index eb9d575..445a324 100644
--- a/gcc/testsuite/gcc.target/mips/scc-3.c
+++ b/gcc/testsuite/gcc.target/mips/scc-3.c
@@ -3,7 +3,7 @@
/* { dg-add-options mips16_attribute } */
/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */
-/* { dg-final { scan-assembler-times "slt\t\|sltu\t" 8 } } */
+/* { dg-final { scan-assembler-times "slt\t\|slti?u\t" 8 } } */
#define TEST(N, LHS, REL, RHS) \
diff --git a/gcc/testsuite/gcc.target/mips/seq-1.c b/gcc/testsuite/gcc.target/mips/seq-1.c
new file mode 100644
index 0000000..ae23608
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/seq-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler-times "\tsltu\t|\tsltiu\t" 4 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+ NOMIPS16 int f##N (int a, int b) { return LHS REL RHS; }
+
+TEST (0, a, ==, 0);
+TEST (1, a, ==, 600);
+TEST (10, a, !=, 0);
+TEST (11, a, !=, -800);
generated by cgit v1.1 at 2025-03-01 17:34:47 +0000