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-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/doc/tm.texi3
-rw-r--r--gcc/doc/tm.texi.in3
3 files changed, 5 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b5cf3b2..3b56192 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2014-05-12 David Wohlferd <dw@LimeGreenSocks.com>
+
+ * doc/tm.texi: Remove reference to deleted macro.
+ * doc/tm.texi.in: Likewise.
+
2014-05-12 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR target/60991
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index fd4e4fd..92312f5 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -10067,9 +10067,6 @@ Another note: according to the MIPS spec, coprocessor 1 (if present) is
the FPU@. One accesses COP1 registers through standard mips
floating-point support; they are not included in this mechanism.
-There is one macro used in defining the MIPS coprocessor interface which
-you may want to override in subtargets; it is described below.
-
@node PCH Target
@section Parameters for Precompiled Header Validity Checking
@cindex parameters, precompiled headers
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 9c030df..7a91da0 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -7565,9 +7565,6 @@ Another note: according to the MIPS spec, coprocessor 1 (if present) is
the FPU@. One accesses COP1 registers through standard mips
floating-point support; they are not included in this mechanism.
-There is one macro used in defining the MIPS coprocessor interface which
-you may want to override in subtargets; it is described below.
-
@node PCH Target
@section Parameters for Precompiled Header Validity Checking
@cindex parameters, precompiled headers