diff options
Diffstat (limited to 'gcc')
47 files changed, 5733 insertions, 2367 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f7ffd4d..d597002 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,282 @@ +2025-05-13 Andrew MacLeod <amacleod@redhat.com> + + * tree-ssanames.cc (set_bitmask): Use int_range_max for temps. + * value-range.cc (irange::set_range_from_bitmask): Handle all + trailing zero values. + +2025-05-12 Pan Li <pan2.li@intel.com> + + * match.pd: Add form 7 matching pattern for unsigned integer + SAT_ADD. + +2025-05-12 Andrew Pinski <quic_apinski@quicinc.com> + + * config/aarch64/aarch64.md (cmov<mode>6): Remove. + +2025-05-12 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/120230 + * optabs.cc (can_compare_p): Remove support for ccp_cmov. + * optabs.def (cmov_optab): Remove. + * optabs.h (can_compare_purpose): Remove ccp_cmov. + +2025-05-12 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/120231 + * range-op-float.cc (operator_cast::fold_range): New variants. + (operator_cast::op1_range): Likewise. + * range-op-mixed.h (operator_cast::fold_range): Likewise. + (operator_cast::op1_range): Likewise + * range-op.cc (range_op_handler::fold_range): Add RO_FIF dispatch. + (range_op_handler::op1_range): Add RO_IFF and RO_FII patterns. + (range_operator::fold_range): Provide new variant default. + (range_operator::op1_range): Likewise. + * range-op.h (range_operator): Add new variant methods. + +2025-05-12 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/120188 + * doc/gm2.texi (Semantic checking): Add -fm2-plugin command line option. + +2025-05-12 Thomas Schwinge <tschwinge@baylibre.com> + + * config/nvptx/nvptx-sm.def: Add '61'. + * config/nvptx/nvptx-gen.h: Regenerate. + * config/nvptx/nvptx-gen.opt: Likewise. + * config/nvptx/nvptx.cc (first_ptx_version_supporting_sm): Adjust. + * config/nvptx/nvptx.opt (-march-map=sm_61, -march-map=sm_62): + Likewise. + * config.gcc: Likewise. + * doc/invoke.texi (Nvidia PTX Options): Document '-march=sm_61'. + * config/nvptx/gen-multilib-matches-tests: Extend. + +2025-05-12 Thomas Schwinge <tschwinge@baylibre.com> + + * config/nvptx/nvptx-opts.h (enum ptx_version): Add + 'PTX_VERSION_5_0'. + * config/nvptx/nvptx.cc (ptx_version_to_string) + (ptx_version_to_number): Adjust. + * config/nvptx/nvptx.h (TARGET_PTX_5_0): New. + * config/nvptx/nvptx.opt (Enum(ptx_version)): Add 'EnumValue' + '5.0' for 'PTX_VERSION_5_0'. + * doc/invoke.texi (Nvidia PTX Options): Document '-mptx=5.0'. + +2025-05-12 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::check_conflict_ext): New extension. + * config/riscv/riscv.opt: Ditto. + +2025-05-12 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::check_conflict_ext): New extension. + * config/riscv/riscv.opt: Ditto. + +2025-05-12 Richard Biener <rguenther@suse.de> + + * lto-streamer-out.cc (hash_tree): Hash TYPE_MODE_RAW. + When offloading hash modes as VOIDmode for aggregates + and vectors. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * doc/extend.texi: Remove the iwmmxt intrinsics. + * doc/md.texi: Remove the iwmmxt-related constraints. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/aout.h (REGISTER_NAMES): Remove iwmmxt registers. + * config/arm/arm.h (FIRST_IWMMXT_REGNUM): Delete. + (LAST_IWMMXT_REGNUM): Delete. + (FIRST_IWMMXT_GR_REGNUM): Delete. + (LAST_IWMMXT_GR_REGNUM): Delete. + (IS_IWMMXT_REGNUM): Delete. + (IS_IWMMXT_GR_REGNUM): Delete. + (FRAME_POINTER_REGNUM): Define relative to CC_REGNUM. + (ARG_POINTER_REGNUM): Define relative to FRAME_POINTER_REGNUM. + (FIRST_PSEUDO_REGISTER): Adjust. + (WREG): Delete. + (WGREG): Delete. + (REG_ALLOC_ORDER): Remove iWMMX registers. + (enum reg_class): Remove iWMMX register classes. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Remove iWMMX registers. + * config/arm/arm.md (CC_REGNUM): Adjust value. + (VFPCC_RENGUM): Likewise. + (APSRQ_REGNUM): Likewise. + (APSRGE_REGNUM): Likewise. + (VPR_REGNUM): Likewise. + (RA_AUTH_CODE): Likewise. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-cpus.in (feature iwmmxt, feature iwmmxt2): Delete. + * config/arm/arm-protos.h (arm_output_iwmmxt_shift_immediate): Delete. + (arm_output_iwmmxt_tinsr): Delete. + (arm_arch_iwmmxt): Delete. + (arm_arch_iwmmxt2): Delete. + * config/arm/arm.h (TARGET_IWMMXT): Delete. + (TARGET_IWMMXT2): Delete. + (TARGET_REALLY_IWMMXT): Delete. + (TARGET_REALLY_IWMMXT2): Delete. + (VALID_IWMMXT_REG_MODE): Delete. + (ARM_HAVE_V8QI_ARITH): Remove iWMMXT. + (ARM_HAVE_V4HI_ARITH): Likewise. + (ARM_HAVE_V2SI_ARITH): Likewise. + (ARM_HAVE_V8QI_LDST): Likewise. + (ARM_HAVE_V4HI_LDST): Likewise. + (ARM_HAVE_V2SI_LDST): Likewise. + (SECONDARY_OUTPUT_RELOAD_CLASS): Remove iWMMXT cases. + (SECONDARY_INPUT_RELOAD_CLASS): Likewise. + * config/arm/arm.cc (arm_arch_iwmmxt): Delete. + (arm_arch_iwmmxt2): Delete. + (arm_option_reconfigure_globals): Don't initialize them. + (arm_register_move_cost): Remove costs for iwmmxt. + (struct minipool_node): Update comment. + (output_move_double): Likewise + (output_return_instruction): Likewise. + (arm_print_operand, cases 'U' and 'w'): Report an error if + used. + (arm_regno_class): Remove iWMMXT cases. + (arm_debugger_regno): Remove iWMMXT cases. + (arm_output_iwmmxt_shift_immediate): Delete. + (arm_output_iwmmxt_tinsr): Delete. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-c.cc (arm_cpu_builtins): Remove predefines + for __IWWMXT__, __IWMMXT2__ and __ARM_WMMX. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/iterators.md (VMMX, VMMX2): Remove mode iterators. + (MMX_char): Remove mode iterator attribute. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.md (core_cycles): Remove iwmmxt attributes. + * config/arm/types.md (autodetect_type): Likewise. + * config/arm/marvell-f-iwmmxt.md: Removed. + * config/arm/t-arm: Remove marvell-f-iwmmxt.md + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.cc (arm_option_check_internal): Remove + IWMMXT check. + (arm_options_perform_arch_sanity_checks): Likewise. + (use_return_insn): Likewise. + (arm_init_cumulative_args): Likewise. + (arm_legitimate_index_p): Likewise. + (thumb2_legitimate_index_p): Likewise. + (arm_compute_save_core_reg_mask): Likewise. + (output_return_instruction): Likewise. + (arm_compute_frame_layout): Likewise. + (arm_save_coproc_regs): Likewise. + (arm_hard_regno_mode_ok): Likewise. + (arm_expand_epilogue_apcs_frame): Likewise. + (arm_expand_epilogue): Likewise. + (arm_vector_mode_supported_p): Likewise. + (arm_preferred_simd_mode): Likewise. + (arm_conditional_register_usage): Likewise. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config.gcc (arm, --with-abi): Remove iwmmxt abi option. + * config/arm/arm.opt (enum ARM_ABI_IWMMXT): Remove. + * config/arm/arm.h (TARGET_IWMMXT_ABI): Delete. + (enum arm_pcs): Remove ARM_PCS_AAPCS_IWMMXT. + (FUNCTION_ARG_REGNO_P): Remove IWMMXT ABI support. + (CUMULATIVE_ARGS): Remove iwmmxt_nregs. + * config/arm/arm.cc (arm_options_perform_arch_sanity_checks): + Remove IWMMXT ABI checks. + (arm_libcall_value_1): Likewise. + (arm_function_value_regno_p): Likewise. + (arm_apply_result_size): Remove adjustment for IWMMXT ABI. + (arm_function_arg): Remove IWMMXT ABI support. + (arm_arg_partial_bytes): Likewise. + (arm_function_arg_advance): Likewise. + (arm_init_cumulative_args): Don't initialize iwmmxt_nregs. + * doc/invoke.texi (arm -mabi): Remove mention of the iwmmxt + ABI option. + * config/arm/arm-opts.h (enum arm_abi_type): Remove ARM_ABI_IWMMXT. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.md(attr arch): Remove iwmmxt and iwmmxt2. + Remove checks based on TARGET_REALLY_IWMMXT2 from all split + patterns. + (arm_movdi): Likewise. + (*arm_movt): Likewise. + (arch_enabled): Remove test for iwmmxt2. + * config/arm/constraints.md (y, z): Remove register constraints. + (Uy): Remove memory constraint. + * config/arm/thumb2.md (thumb2_pop_single): Remove check for + IWMMXT. + * config/arm/vec-common.md (mov<mode>): Remove check for IWMMXT. + (mul<mode>3): Likewise. + (xor<mode>3): Likewise. + (<absneg_str><mode>2): Likewise. + (@movmisalign<mode>): Likewise. + (@mve_<mve_insn>q_<supf><mode>): Likewise. + (vashl<mode>3): Likewise. + (vashr<mode>3): Likewise. + (vlshr<mode>3): Likewise. + (uavg<mode>3_ceil): Likewise. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.md: Don't include iwmmxt.md. + * config/arm/t-arm (MD_INCLUDES): Remove iwmmxt*.md. + * config/arm/iwmmxt.md: Removed. + * config/arm/iwmmxt2.md: Removed. + * config/arm/unspecs.md: Remove comment referring to + iwmmxt2.md. + (enum unspec): Remove iWMMXt unspec values. + (enum unspecv): Likewise. + * config/arm/predicates.md (imm_or_reg_operand): Delete. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-builtins.cc (enum arm_builtins): Delete iWMMX + builtin values. + (bdesc_2arg): Likewise. + (bdesc_1arg): Likewise. + (arm_init_iwmmxt_builtins): Delete. + (arm_init_builtins): Don't call arm_init_iwmmxt_builtins. + (safe_vector_operand): Use __builtin_unreachable instead of emitting + an iwmmxt builtin. + (arm_general_expand_builtin): Remove iWMMX builtins support. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-cpus.in (arch iwmmxt): treat in the same + way as we would treat XScale. + (arch iwmmxt2): Likewise. + (cpu xscale): Add aliases for iwmmxt and iwmmxt2. + (cpu iwmmxt): Delete. + (cpu iwmmxt2): Delete. + * config/arm/arm-generic.md (load_ldsched_xscale): Remove references + to iwmmxt. + (load_ldsched): Likewise. + * config/arm/arm-tables.opt: Regenerated. + * config/arm/arm-tune.md: Regenerated. + * doc/sourcebuild.texi (arm_iwmmxt_ok): Delete. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.h (SECONDARY_OUTPUT_RELOAD_CLASS): Add parentheis + and re-indent. + (SECONDARY_INPUT_RELOAD_CLASS): Likewise. + +2025-05-12 H.J. Lu <hjl.tools@gmail.com> + + PR target/120228 + * config/i386/i386-features.cc (ix86_place_single_vector_set): + Remove df_insn_rescan after emit_insn_*. + (remove_partial_avx_dependency): Likewise. + (replace_vector_const): Likewise. + 2025-05-11 Jan Hubicka <hubicka@ucw.cz> * config/i386/i386.cc (ix86_widen_mult_cost): Use sse_op to cost diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 823f45b..83f5cb2 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250512 +20250513 diff --git a/gcc/Makefile.in b/gcc/Makefile.in index e3af923..72d1322 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -3703,7 +3703,7 @@ TEXI_GCC_FILES = gcc.texi gcc-common.texi gcc-vers.texi frontends.texi \ contribute.texi compat.texi funding.texi gnu.texi gpl_v3.texi \ fdl.texi contrib.texi cppenv.texi cppopts.texi avr-mmcu.texi \ implement-c.texi implement-cxx.texi gcov-tool.texi gcov-dump.texi \ - lto-dump.texi + lto-dump.texi riscv-ext.texi # we explicitly use $(srcdir)/doc/tm.texi here to avoid confusion with # the generated tm.texi; the latter might have a more recent timestamp, diff --git a/gcc/ada/Make-generated.in b/gcc/ada/Make-generated.in index 95c2a1d..5cb1b32 100644 --- a/gcc/ada/Make-generated.in +++ b/gcc/ada/Make-generated.in @@ -18,7 +18,7 @@ GEN_IL_FLAGS = -gnata -gnat2012 -gnatw.g -gnatyg -gnatU $(GEN_IL_INCLUDES) ada/seinfo_tables.ads ada/seinfo_tables.adb ada/sinfo.h ada/einfo.h ada/nmake.ads ada/nmake.adb ada/seinfo.ads ada/sinfo-nodes.ads ada/sinfo-nodes.adb ada/einfo-entities.ads ada/einfo-entities.adb: ada/stamp-gen_il ; @true ada/stamp-gen_il: $(fsrcdir)/ada/gen_il* $(MKDIR) ada/gen_il - cd ada/gen_il; gnatmake -q -g $(GEN_IL_FLAGS) gen_il-main + cd ada/gen_il; gnatmake -g $(GEN_IL_FLAGS) gen_il-main # Ignore errors to work around finalization issues in older compilers - cd ada/gen_il; ./gen_il-main $(fsrcdir)/../move-if-change ada/gen_il/seinfo_tables.ads ada/seinfo_tables.ads @@ -46,7 +46,7 @@ ada/stamp-snames : ada/snames.ads-tmpl ada/snames.adb-tmpl ada/snames.h-tmpl ada -$(MKDIR) ada/bldtools/snamest $(RM) $(addprefix ada/bldtools/snamest/,$(notdir $^)) $(CP) $^ ada/bldtools/snamest - cd ada/bldtools/snamest && gnatmake -q xsnamest && ./xsnamest + cd ada/bldtools/snamest && gnatmake xsnamest && ./xsnamest $(fsrcdir)/../move-if-change ada/bldtools/snamest/snames.ns ada/snames.ads $(fsrcdir)/../move-if-change ada/bldtools/snamest/snames.nb ada/snames.adb $(fsrcdir)/../move-if-change ada/bldtools/snamest/snames.nh ada/snames.h diff --git a/gcc/ada/gcc-interface/Makefile.in b/gcc/ada/gcc-interface/Makefile.in index 4ffdc1e..2c42cb1 100644 --- a/gcc/ada/gcc-interface/Makefile.in +++ b/gcc/ada/gcc-interface/Makefile.in @@ -634,7 +634,7 @@ OSCONS_EXTRACT=$(GCC_FOR_ADA_RTS) $(GNATLIBCFLAGS_FOR_C) -S s-oscons-tmplt.i -$(MKDIR) ./bldtools/oscons $(RM) $(addprefix ./bldtools/oscons/,$(notdir $^)) $(CP) $^ ./bldtools/oscons - (cd ./bldtools/oscons ; gnatmake -q xoscons) + (cd ./bldtools/oscons ; gnatmake xoscons) $(RTSDIR)/s-oscons.ads: ../stamp-gnatlib1-$(RTSDIR) s-oscons-tmplt.c gsocket.h ./bldtools/oscons/xoscons $(RM) $(RTSDIR)/s-oscons-tmplt.i $(RTSDIR)/s-oscons-tmplt.s diff --git a/gcc/cfgexpand.cc b/gcc/cfgexpand.cc index 2b27076..277ef65 100644 --- a/gcc/cfgexpand.cc +++ b/gcc/cfgexpand.cc @@ -766,7 +766,12 @@ vars_ssa_cache::operator() (tree name) /* If the cache exists for the use, don't try to recreate it. */ if (exists (use)) - continue; + { + /* Update the cache here, this can reduce the number of + times through the update loop below. */ + update (old_name, use); + continue; + } /* Create the cache bitmap for the use and also so we don't go into an infinite loop for some phi nodes with loops. */ @@ -804,9 +809,11 @@ vars_ssa_cache::operator() (tree name) bool changed; do { changed = false; - for (auto &e : update_cache_list) + unsigned int i; + std::pair<tree,tree> *e; + FOR_EACH_VEC_ELT_REVERSE (update_cache_list, i, e) { - if (update (e.second, e.first)) + if (update (e->second, e->first)) changed = true; } } while (changed); diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index d3240f7..3d3ca11 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -19,6 +19,7 @@ along with GCC; see the file COPYING3. If not see #include <sstream> #include <vector> +#include <unordered_map> #include <queue> #define INCLUDE_STRING @@ -41,236 +42,216 @@ along with GCC; see the file COPYING3. If not see #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN) #endif +/* Type for pointer to member of gcc_options and cl_target_option. */ +typedef int (gcc_options::*opt_var_ref_t); +typedef int (cl_target_option::*cl_opt_var_ref_t); + +/* Types for recording extension to internal flag. */ +struct riscv_extra_ext_flag_table_t +{ + const char *ext; + opt_var_ref_t var_ref; + cl_opt_var_ref_t cl_var_ref; + int mask; +}; + +/* Types for recording extension to internal flag. */ +struct riscv_ext_flag_table_t +{ + opt_var_ref_t var_ref; + cl_opt_var_ref_t cl_var_ref; + int mask; + + void clean (gcc_options *opts) const { opts->*var_ref &= ~mask; } + + void set (gcc_options *opts) const { opts->*var_ref |= mask; } + + bool check (cl_target_option *opts) const + { + return (opts->*cl_var_ref & mask); + } +}; + +/* Type for hold RISC-V extension version. */ +struct riscv_version_t +{ + riscv_version_t (int major_version, int minor_version, + enum riscv_isa_spec_class isa_spec_class + = ISA_SPEC_CLASS_NONE) + : major_version (major_version), minor_version (minor_version), + isa_spec_class (isa_spec_class) + {} + int major_version; + int minor_version; + enum riscv_isa_spec_class isa_spec_class; +}; + typedef bool (*riscv_implied_predicator_t) (const riscv_subset_list *); /* Type for implied ISA info. */ struct riscv_implied_info_t { - constexpr riscv_implied_info_t (const char *ext, const char *implied_ext, + constexpr riscv_implied_info_t (const char *implied_ext, riscv_implied_predicator_t predicator = nullptr) - : ext (ext), implied_ext (implied_ext), predicator (predicator){}; + : implied_ext (implied_ext), predicator (predicator) + {} - bool match (const riscv_subset_list *subset_list, const char *ext_name) const + bool match (const riscv_subset_list *subset_list) const { - if (strcmp (ext_name, ext) != 0) - return false; - if (predicator && !predicator (subset_list)) return false; return true; } - bool match (const riscv_subset_list *subset_list, - const riscv_subset_t *subset) const - { - return match (subset_list, subset->name.c_str()); - } - - const char *ext; const char *implied_ext; riscv_implied_predicator_t predicator; }; -/* Implied ISA info, must end with NULL sentinel. */ -static const riscv_implied_info_t riscv_implied_info[] = -{ - {"m", "zmmul"}, - - {"d", "f"}, - {"f", "zicsr"}, - {"d", "zicsr"}, - - {"a", "zaamo"}, - {"a", "zalrsc"}, - - {"c", "zca"}, - {"c", "zcf", - [] (const riscv_subset_list *subset_list) -> bool - { - return subset_list->xlen () == 32 && subset_list->lookup ("f"); - }}, - {"c", "zcd", - [] (const riscv_subset_list *subset_list) -> bool - { - return subset_list->lookup ("d"); - }}, - - {"zabha", "zaamo"}, - {"zacas", "zaamo"}, - {"zawrs", "zalrsc"}, - - {"zcmop", "zca"}, - - {"b", "zba"}, - {"b", "zbb"}, - {"b", "zbs"}, - - {"zdinx", "zfinx"}, - {"zfinx", "zicsr"}, - {"zdinx", "zicsr"}, - - {"zicfiss", "zicsr"}, - {"zicfiss", "zimop"}, - {"zicfilp", "zicsr"}, - - {"zclsd", "zilsd"}, - {"zclsd", "zca"}, - - {"zk", "zkn"}, - {"zk", "zkr"}, - {"zk", "zkt"}, - {"zkn", "zbkb"}, - {"zkn", "zbkc"}, - {"zkn", "zbkx"}, - {"zkn", "zkne"}, - {"zkn", "zknd"}, - {"zkn", "zknh"}, - {"zks", "zbkb"}, - {"zks", "zbkc"}, - {"zks", "zbkx"}, - {"zks", "zksed"}, - {"zks", "zksh"}, - - {"v", "zvl128b"}, - {"v", "zve64d"}, - - {"zve32f", "f"}, - {"zve64f", "f"}, - {"zve64d", "d"}, - - {"zve32x", "zicsr"}, - {"zve32x", "zvl32b"}, - {"zve32f", "zve32x"}, - {"zve32f", "zvl32b"}, - - {"zve64x", "zve32x"}, - {"zve64x", "zvl64b"}, - {"zve64f", "zve32f"}, - {"zve64f", "zve64x"}, - {"zve64f", "zvl64b"}, - {"zve64d", "zve64f"}, - {"zve64d", "zvl64b"}, - - {"zvl64b", "zvl32b"}, - {"zvl128b", "zvl64b"}, - {"zvl256b", "zvl128b"}, - {"zvl512b", "zvl256b"}, - {"zvl1024b", "zvl512b"}, - {"zvl2048b", "zvl1024b"}, - {"zvl4096b", "zvl2048b"}, - {"zvl8192b", "zvl4096b"}, - {"zvl16384b", "zvl8192b"}, - {"zvl32768b", "zvl16384b"}, - {"zvl65536b", "zvl32768b"}, - - {"zvkn", "zvkned"}, - {"zvkn", "zvknhb"}, - {"zvkn", "zvkb"}, - {"zvkn", "zvkt"}, - {"zvknc", "zvkn"}, - {"zvknc", "zvbc"}, - {"zvkng", "zvkn"}, - {"zvkng", "zvkg"}, - {"zvks", "zvksed"}, - {"zvks", "zvksh"}, - {"zvks", "zvkb"}, - {"zvks", "zvkt"}, - {"zvksc", "zvks"}, - {"zvksc", "zvbc"}, - {"zvksg", "zvks"}, - {"zvksg", "zvkg"}, - {"zvbb", "zvkb"}, - {"zvbc", "zve64x"}, - {"zvkb", "zve32x"}, - {"zvkg", "zve32x"}, - {"zvkned", "zve32x"}, - {"zvknha", "zve32x"}, - {"zvknhb", "zve64x"}, - {"zvksed", "zve32x"}, - {"zvksh", "zve32x"}, - - {"zfbfmin", "zfhmin"}, - {"zfh", "zfhmin"}, - {"zfhmin", "f"}, - - {"zfa", "f"}, - - {"zvfbfmin", "zve32f"}, - {"zvfbfwma", "zvfbfmin"}, - {"zvfbfwma", "zfbfmin"}, - {"zvfhmin", "zve32f"}, - {"zvfh", "zve32f"}, - {"zvfh", "zfhmin"}, - - {"zhinx", "zhinxmin"}, - {"zhinxmin", "zfinx"}, - - {"zce", "zca"}, - {"zce", "zcb"}, - {"zce", "zcmp"}, - {"zce", "zcmt"}, - {"zcf", "zca"}, - {"zcd", "zca"}, - {"zcb", "zca"}, - {"zcmp", "zca"}, - {"zcmt", "zca"}, - {"zcmt", "zicsr"}, - {"zce", "zcf", - [] (const riscv_subset_list *subset_list) -> bool - { - return subset_list->xlen () == 32 && subset_list->lookup ("f"); - }}, - {"zca", "c", - [] (const riscv_subset_list *subset_list) -> bool - { - /* For RV32 Zca implies C for one of these combinations of - extensions: Zca, F_Zca_Zcf and FD_Zca_Zcf_Zcd. */ - if (subset_list->xlen () == 32) - { - if (subset_list->lookup ("d")) - return subset_list->lookup ("zcf") && subset_list->lookup ("zcd"); - - if (subset_list->lookup ("f")) - return subset_list->lookup ("zcf"); - - return true; - } - - /* For RV64 Zca implies C for one of these combinations of - extensions: Zca and FD_Zca_Zcd (Zcf is not available - for RV64). */ - if (subset_list->xlen () == 64) - { - if (subset_list->lookup ("d")) - return subset_list->lookup ("zcd"); - - return true; - } - - /* Do nothing for future RV128 specification. Behaviour - for this case is not yet well defined. */ - return false; - }}, - - {"smaia", "ssaia"}, - {"smstateen", "ssstateen"}, - {"smepmp", "zicsr"}, - {"ssaia", "zicsr"}, - {"sscofpmf", "zicsr"}, - {"ssstateen", "zicsr"}, - {"sstc", "zicsr"}, - - {"ssnpm", "zicsr"}, - {"smnpm", "zicsr"}, - {"smmpm", "zicsr"}, - - {"xsfvcp", "zve32x"}, +static void +apply_extra_extension_flags (const char *ext, + std::vector<riscv_ext_flag_table_t> &flag_table); + +/* Class for hold the extension info. */ +class riscv_ext_info_t +{ +public: + riscv_ext_info_t (const char *ext, + const std::vector<riscv_implied_info_t> &implied_exts, + const std::vector<riscv_version_t> &supported_versions, + const std::vector<riscv_ext_flag_table_t> &flag_table, + int bitmask_group_id, int bitmask_group_bit_pos, + unsigned extra_extension_flags) + : m_ext (ext), m_implied_exts (implied_exts), + m_supported_versions (supported_versions), m_flag_table (flag_table), + m_bitmask_group_id (bitmask_group_id), + m_bitmask_group_bit_pos (bitmask_group_bit_pos), + m_extra_extension_flags (extra_extension_flags) + { + apply_extra_extension_flags (ext, m_flag_table); + } - {NULL, NULL} + /* Return true if any change. */ + bool apply_implied_ext (riscv_subset_list *subset_list) const; + + const std::vector<riscv_implied_info_t> implied_exts () const + { + return m_implied_exts; + } + + bool need_combine_p () const + { + return m_extra_extension_flags & EXT_FLAG_MACRO; + } + + riscv_version_t default_version () const + { + if (m_supported_versions.size () == 1) + { + return *m_supported_versions.begin (); + } + + for (const riscv_version_t &ver : m_supported_versions) + { + if (ver.isa_spec_class == riscv_isa_spec + || ver.isa_spec_class == ISA_SPEC_CLASS_NONE) + return ver; + } + gcc_unreachable (); + } + + void clean_opts (gcc_options *opts) const + { + for (auto &flag : m_flag_table) + flag.clean (opts); + } + + void set_opts (gcc_options *opts) const + { + for (auto &flag : m_flag_table) + flag.set (opts); + } + + bool check_opts (cl_target_option *opts) const + { + bool result = true; + for (auto &flag : m_flag_table) + result = result && flag.check (opts); + return result; + } + + const std::vector<riscv_version_t> &supported_versions () const + { + return m_supported_versions; + } + +private: + const char *m_ext; + std::vector<riscv_implied_info_t> m_implied_exts; + std::vector<riscv_version_t> m_supported_versions; + std::vector<riscv_ext_flag_table_t> m_flag_table; + int m_bitmask_group_id; + int m_bitmask_group_bit_pos; + unsigned m_extra_extension_flags; +}; + +static const std::unordered_map<std::string, riscv_ext_info_t> riscv_ext_infos + = { +#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ + SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ + BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ + {std::string (#NAME), \ + riscv_ext_info_t (#NAME, std::vector<riscv_implied_info_t> DEP_EXTS, \ + std::vector<riscv_version_t> SUPPORTED_VERSIONS, \ + std::vector<riscv_ext_flag_table_t> ( \ + {{&gcc_options::x_riscv_##FLAG_GROUP##_subext, \ + &cl_target_option::x_riscv_##FLAG_GROUP##_subext, \ + MASK_##UPPERCAE_NAME}}), \ + BITMASK_GROUP_ID, BITMASK_BIT_POSITION, \ + EXTRA_EXTENSION_FLAGS)}, +#include "../../../config/riscv/riscv-ext.def" +#undef DEFINE_RISCV_EXT }; +static const riscv_ext_info_t & +get_riscv_ext_info (const std::string &ext) +{ + auto itr = riscv_ext_infos.find (ext); + if (itr == riscv_ext_infos.end ()) + { + gcc_unreachable (); + } + return itr->second; +} + +/* Return true if any change. */ +bool +riscv_ext_info_t::apply_implied_ext (riscv_subset_list *subset_list) const +{ + bool any_change = false; + for (const riscv_implied_info_t &implied_info : m_implied_exts) + { + /* Skip if implied extension already present. */ + if (subset_list->lookup (implied_info.implied_ext)) + continue; + + any_change = true; + if (!implied_info.match (subset_list)) + continue; + + /* Version of implied extension will get from current ISA spec + version. */ + subset_list->add (implied_info.implied_ext, true); + + /* Recursively add implied extension by implied_info->implied_ext. */ + const riscv_ext_info_t &implied_ext_info + = get_riscv_ext_info (implied_info.implied_ext); + implied_ext_info.apply_implied_ext (subset_list); + } + return any_change; +} + /* This structure holds version information for specific ISA version. */ struct riscv_ext_version @@ -287,243 +268,6 @@ struct riscv_profiles const char *profile_string; }; -/* All standard extensions defined in all supported ISA spec. */ -static const struct riscv_ext_version riscv_ext_version_table[] = -{ - /* name, ISA spec, major version, minor_version. */ - {"e", ISA_SPEC_CLASS_20191213, 2, 0}, - {"e", ISA_SPEC_CLASS_20190608, 2, 0}, - {"e", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"i", ISA_SPEC_CLASS_20191213, 2, 1}, - {"i", ISA_SPEC_CLASS_20190608, 2, 1}, - {"i", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"m", ISA_SPEC_CLASS_20191213, 2, 0}, - {"m", ISA_SPEC_CLASS_20190608, 2, 0}, - {"m", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"a", ISA_SPEC_CLASS_20191213, 2, 1}, - {"a", ISA_SPEC_CLASS_20190608, 2, 0}, - {"a", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"f", ISA_SPEC_CLASS_20191213, 2, 2}, - {"f", ISA_SPEC_CLASS_20190608, 2, 2}, - {"f", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"d", ISA_SPEC_CLASS_20191213, 2, 2}, - {"d", ISA_SPEC_CLASS_20190608, 2, 2}, - {"d", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"c", ISA_SPEC_CLASS_20191213, 2, 0}, - {"c", ISA_SPEC_CLASS_20190608, 2, 0}, - {"c", ISA_SPEC_CLASS_2P2, 2, 0}, - - {"b", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"h", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"v", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0}, - {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0}, - - {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, - {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, - - {"zicond", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"za64rs", ISA_SPEC_CLASS_NONE, 1, 0}, - {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zabha", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zacas", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zama16b", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zhinx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zhinxmin", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zbkb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbkc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zbkx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkne", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zknd", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zknh", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkr", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zksed", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0}, - - {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, - {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, - {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, - {"zic64b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ziccif", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zicfiss", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zicfilp", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zimop", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0}, - {"zihpm", ISA_SPEC_CLASS_NONE, 2, 0}, - - {"zilsd", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zclsd", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"ztso", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zve32x", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zve32f", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zve64x", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zve64f", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zve64d", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zvbb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvbc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkg", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkned", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvknha", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvknhb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksed", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksh", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkn", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvknc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkng", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvks", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksg", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkt", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zvl32b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl64b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl128b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl256b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl512b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl1024b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl2048b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl4096b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl8192b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl16384b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvfbfwma", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvfh", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zfa", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"zca", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zce", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcf", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcd", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"sdtrig", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"smaia", ISA_SPEC_CLASS_NONE, 1, 0}, - {"smepmp", ISA_SPEC_CLASS_NONE, 1, 0}, - {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"ssaia", ISA_SPEC_CLASS_NONE, 1, 0}, - {"sscofpmf", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, - {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"ssstrict", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"ssnpm", ISA_SPEC_CLASS_NONE, 1, 0}, - {"smnpm", ISA_SPEC_CLASS_NONE, 1, 0}, - {"smmpm", ISA_SPEC_CLASS_NONE, 1, 0}, - {"sspm", ISA_SPEC_CLASS_NONE, 1, 0}, - {"supm", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"svade", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svadu", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0}, - {"svvptc", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xcvsimd", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadbs", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadfmv", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadint", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, - - {"xsfvcp", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xsfvqmaccqoq", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xsfvqmaccdod", ISA_SPEC_CLASS_NONE, 1, 0}, - {"xsfvfnrclipxfqf", ISA_SPEC_CLASS_NONE, 1, 0}, - - /* Terminate the list. */ - {NULL, ISA_SPEC_CLASS_NONE, 0, 0} -}; - -/* Combine extensions defined in this table */ -static const struct riscv_ext_version riscv_combine_info[] = -{ - {"a", ISA_SPEC_CLASS_20191213, 2, 1}, - {"b", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkn", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvknc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvkng", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvks", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksc", ISA_SPEC_CLASS_NONE, 1, 0}, - {"zvksg", ISA_SPEC_CLASS_NONE, 1, 0}, - /* Terminate the list. */ - {NULL, ISA_SPEC_CLASS_NONE, 0, 0} -}; - /* This table records the mapping form RISC-V Profiles into march string. */ static const riscv_profiles riscv_profiles_table[] = { @@ -798,11 +542,8 @@ subset_cmp (const std::string &a, const std::string &b) static bool standard_extensions_p (const char *ext) { - const riscv_ext_version *ext_ver; - for (ext_ver = &riscv_ext_version_table[0]; ext_ver->name != NULL; ++ext_ver) - if (strcmp (ext, ext_ver->name) == 0) - return true; - return false; + auto itr = riscv_ext_infos.find (ext); + return itr != riscv_ext_infos.end (); } /* Add new subset to list. */ @@ -932,24 +673,19 @@ get_default_version (const char *ext, unsigned int *major_version, unsigned int *minor_version) { - const riscv_ext_version *ext_ver; - for (ext_ver = &riscv_ext_version_table[0]; - ext_ver->name != NULL; - ++ext_ver) - if (strcmp (ext, ext_ver->name) == 0) - { - if ((ext_ver->isa_spec_class == riscv_isa_spec) || - (ext_ver->isa_spec_class == ISA_SPEC_CLASS_NONE)) - { - *major_version = ext_ver->major_version; - *minor_version = ext_ver->minor_version; - return; - } - } + auto itr = riscv_ext_infos.find (ext); + if (itr == riscv_ext_infos.end ()) + { + /* Not found version info. */ + *major_version = 0; + *minor_version = 0; + return; + } - /* Not found version info. */ - *major_version = 0; - *minor_version = 0; + riscv_version_t ver = itr->second.default_version (); + /* Get the version info from riscv_ext_infos. */ + *major_version = ver.major_version; + *minor_version = ver.minor_version; } /* Add new subset to list, but using default version from ISA spec version. */ @@ -1353,25 +1089,8 @@ riscv_subset_list::parse_single_std_ext (const char *p, bool exact_single_p) void riscv_subset_list::handle_implied_ext (const char *ext) { - const riscv_implied_info_t *implied_info; - for (implied_info = &riscv_implied_info[0]; - implied_info->ext; - ++implied_info) - { - if (!implied_info->match (this, ext)) - continue; - - /* Skip if implied extension already present. */ - if (lookup (implied_info->implied_ext)) - continue; - - /* Version of implied extension will get from current ISA spec - version. */ - add (implied_info->implied_ext, true); - - /* Recursively add implied extension by implied_info->implied_ext. */ - handle_implied_ext (implied_info->implied_ext); - } + const riscv_ext_info_t &ext_info = get_riscv_ext_info (ext); + ext_info.apply_implied_ext (this); /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifence is included in the base ISA. */ @@ -1392,14 +1111,13 @@ riscv_subset_list::check_implied_ext () riscv_subset_t *itr; for (itr = m_head; itr != NULL; itr = itr->next) { - const riscv_implied_info_t *implied_info; - for (implied_info = &riscv_implied_info[0]; implied_info->ext; - ++implied_info) + auto &ext = *itr; + auto &ext_info = get_riscv_ext_info (ext.name); + for (auto &implied_ext : ext_info.implied_exts ()) { - if (!implied_info->match (this, itr)) + if (!implied_ext.match (this)) continue; - - if (!lookup (implied_info->implied_ext)) + if (lookup (implied_ext.implied_ext) == NULL) return false; } } @@ -1410,27 +1128,23 @@ riscv_subset_list::check_implied_ext () void riscv_subset_list::handle_combine_ext () { - const riscv_ext_version *combine_info; - const riscv_implied_info_t *implied_info; - bool is_combined = false; - - for (combine_info = &riscv_combine_info[0]; combine_info->name; - ++combine_info) + for (const auto &[ext_name, ext_info] : riscv_ext_infos) { - /* Skip if combine extensions are present */ - if (lookup (combine_info->name)) + bool is_combined = true; + /* Skip if this extension don't need to combine. */ + if (!ext_info.need_combine_p ()) + continue; + /* Skip if combine extensions are present. */ + if (lookup (ext_name.c_str ())) continue; - /* Find all extensions of the combine extension */ - for (implied_info = &riscv_implied_info[0]; implied_info->ext; - ++implied_info) + /* Check all implied extensions is present. */ + for (const auto &implied_ext : ext_info.implied_exts ()) { - if (!implied_info->match (this, combine_info->name)) + if (!implied_ext.match (this)) continue; - if (lookup (implied_info->implied_ext)) - is_combined = true; - else + if (!lookup (implied_ext.implied_ext)) { is_combined = false; break; @@ -1440,11 +1154,9 @@ riscv_subset_list::handle_combine_ext () /* Add combine extensions */ if (is_combined) { - if (lookup (combine_info->name) == NULL) - { - add (combine_info->name, combine_info->major_version, - combine_info->minor_version, false, true); - } + riscv_version_t ver = ext_info.default_version(); + add (ext_name.c_str (), ver.major_version, + ver.minor_version, false, true); } } } @@ -1759,91 +1471,15 @@ riscv_arch_str (bool version_p) return std::string(); } -/* Type for pointer to member of gcc_options and cl_target_option. */ -typedef int (gcc_options::*opt_var_ref_t); -typedef int (cl_target_option::*cl_opt_var_ref_t); - -/* Types for recording extension to internal flag. */ -struct riscv_ext_flag_table_t { - const char *ext; - opt_var_ref_t var_ref; - cl_opt_var_ref_t cl_var_ref; - int mask; -}; - #define RISCV_EXT_FLAG_ENTRY(NAME, VAR, MASK) \ {NAME, &gcc_options::VAR, &cl_target_option::VAR, MASK} -/* Mapping table between extension to internal flag. */ -static const riscv_ext_flag_table_t riscv_ext_flag_table[] = -{ - RISCV_EXT_FLAG_ENTRY ("e", x_target_flags, MASK_RVE), - RISCV_EXT_FLAG_ENTRY ("m", x_target_flags, MASK_MUL), - RISCV_EXT_FLAG_ENTRY ("a", x_target_flags, MASK_ATOMIC), - RISCV_EXT_FLAG_ENTRY ("f", x_target_flags, MASK_HARD_FLOAT), - RISCV_EXT_FLAG_ENTRY ("d", x_target_flags, MASK_DOUBLE_FLOAT), - RISCV_EXT_FLAG_ENTRY ("c", x_target_flags, MASK_RVC), - RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_FULL_V), - RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_VECTOR), - - RISCV_EXT_FLAG_ENTRY ("zicsr", x_riscv_zi_subext, MASK_ZICSR), - RISCV_EXT_FLAG_ENTRY ("zifencei", x_riscv_zi_subext, MASK_ZIFENCEI), - RISCV_EXT_FLAG_ENTRY ("zicond", x_riscv_zi_subext, MASK_ZICOND), - - RISCV_EXT_FLAG_ENTRY ("za64rs", x_riscv_za_subext, MASK_ZA64RS), - RISCV_EXT_FLAG_ENTRY ("za128rs", x_riscv_za_subext, MASK_ZA128RS), - RISCV_EXT_FLAG_ENTRY ("zawrs", x_riscv_za_subext, MASK_ZAWRS), - RISCV_EXT_FLAG_ENTRY ("zaamo", x_riscv_za_subext, MASK_ZAAMO), - RISCV_EXT_FLAG_ENTRY ("zalrsc", x_riscv_za_subext, MASK_ZALRSC), - RISCV_EXT_FLAG_ENTRY ("zabha", x_riscv_za_subext, MASK_ZABHA), - RISCV_EXT_FLAG_ENTRY ("zacas", x_riscv_za_subext, MASK_ZACAS), - RISCV_EXT_FLAG_ENTRY ("zama16b", x_riscv_za_subext, MASK_ZAMA16B), - - RISCV_EXT_FLAG_ENTRY ("zba", x_riscv_zb_subext, MASK_ZBA), - RISCV_EXT_FLAG_ENTRY ("zbb", x_riscv_zb_subext, MASK_ZBB), - RISCV_EXT_FLAG_ENTRY ("zbc", x_riscv_zb_subext, MASK_ZBC), - RISCV_EXT_FLAG_ENTRY ("zbs", x_riscv_zb_subext, MASK_ZBS), - - RISCV_EXT_FLAG_ENTRY ("zfinx", x_riscv_zinx_subext, MASK_ZFINX), - RISCV_EXT_FLAG_ENTRY ("zdinx", x_riscv_zinx_subext, MASK_ZDINX), - RISCV_EXT_FLAG_ENTRY ("zhinx", x_riscv_zinx_subext, MASK_ZHINX), - RISCV_EXT_FLAG_ENTRY ("zhinxmin", x_riscv_zinx_subext, MASK_ZHINXMIN), - - RISCV_EXT_FLAG_ENTRY ("zbkb", x_riscv_zk_subext, MASK_ZBKB), - RISCV_EXT_FLAG_ENTRY ("zbkc", x_riscv_zk_subext, MASK_ZBKC), - RISCV_EXT_FLAG_ENTRY ("zbkx", x_riscv_zk_subext, MASK_ZBKX), - RISCV_EXT_FLAG_ENTRY ("zknd", x_riscv_zk_subext, MASK_ZKND), - RISCV_EXT_FLAG_ENTRY ("zkne", x_riscv_zk_subext, MASK_ZKNE), - RISCV_EXT_FLAG_ENTRY ("zknh", x_riscv_zk_subext, MASK_ZKNH), - RISCV_EXT_FLAG_ENTRY ("zkr", x_riscv_zk_subext, MASK_ZKR), - RISCV_EXT_FLAG_ENTRY ("zksed", x_riscv_zk_subext, MASK_ZKSED), - RISCV_EXT_FLAG_ENTRY ("zksh", x_riscv_zk_subext, MASK_ZKSH), - RISCV_EXT_FLAG_ENTRY ("zkt", x_riscv_zk_subext, MASK_ZKT), - - RISCV_EXT_FLAG_ENTRY ("zihintntl", x_riscv_zi_subext, MASK_ZIHINTNTL), - RISCV_EXT_FLAG_ENTRY ("zihintpause", x_riscv_zi_subext, MASK_ZIHINTPAUSE), - RISCV_EXT_FLAG_ENTRY ("ziccamoa", x_riscv_zi_subext, MASK_ZICCAMOA), - RISCV_EXT_FLAG_ENTRY ("ziccif", x_riscv_zi_subext, MASK_ZICCIF), - RISCV_EXT_FLAG_ENTRY ("zicclsm", x_riscv_zi_subext, MASK_ZICCLSM), - RISCV_EXT_FLAG_ENTRY ("ziccrse", x_riscv_zi_subext, MASK_ZICCRSE), - RISCV_EXT_FLAG_ENTRY ("zilsd", x_riscv_zi_subext, MASK_ZILSD), - - RISCV_EXT_FLAG_ENTRY ("zicboz", x_riscv_zicmo_subext, MASK_ZICBOZ), - RISCV_EXT_FLAG_ENTRY ("zicbom", x_riscv_zicmo_subext, MASK_ZICBOM), - RISCV_EXT_FLAG_ENTRY ("zicbop", x_riscv_zicmo_subext, MASK_ZICBOP), - RISCV_EXT_FLAG_ENTRY ("zic64b", x_riscv_zicmo_subext, MASK_ZIC64B), - - RISCV_EXT_FLAG_ENTRY ("zicfiss", x_riscv_zi_subext, MASK_ZICFISS), - RISCV_EXT_FLAG_ENTRY ("zicfilp", x_riscv_zi_subext, MASK_ZICFILP), - - RISCV_EXT_FLAG_ENTRY ("zimop", x_riscv_mop_subext, MASK_ZIMOP), - RISCV_EXT_FLAG_ENTRY ("zcmop", x_riscv_mop_subext, MASK_ZCMOP), - - RISCV_EXT_FLAG_ENTRY ("zve32x", x_target_flags, MASK_VECTOR), - RISCV_EXT_FLAG_ENTRY ("zve32f", x_target_flags, MASK_VECTOR), - RISCV_EXT_FLAG_ENTRY ("zve64x", x_target_flags, MASK_VECTOR), - RISCV_EXT_FLAG_ENTRY ("zve64f", x_target_flags, MASK_VECTOR), - RISCV_EXT_FLAG_ENTRY ("zve64d", x_target_flags, MASK_VECTOR), +/* Mapping table between extension to internal flag, + this table is not needed to add manually unless there is speical rule. */ +static const riscv_extra_ext_flag_table_t riscv_extra_ext_flag_table[] = +{ + RISCV_EXT_FLAG_ENTRY ("zve32x", x_riscv_isa_flags, MASK_VECTOR), + RISCV_EXT_FLAG_ENTRY ("v", x_riscv_isa_flags, MASK_FULL_V), /* We don't need to put complete ELEN/ELEN_FP info here, due to the implication relation of vector extension. @@ -1860,115 +1496,40 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), - RISCV_EXT_FLAG_ENTRY ("zvbb", x_riscv_zvb_subext, MASK_ZVBB), - RISCV_EXT_FLAG_ENTRY ("zvbc", x_riscv_zvb_subext, MASK_ZVBC), - RISCV_EXT_FLAG_ENTRY ("zvkb", x_riscv_zvb_subext, MASK_ZVKB), - RISCV_EXT_FLAG_ENTRY ("zvkg", x_riscv_zvk_subext, MASK_ZVKG), - RISCV_EXT_FLAG_ENTRY ("zvkned", x_riscv_zvk_subext, MASK_ZVKNED), - RISCV_EXT_FLAG_ENTRY ("zvknha", x_riscv_zvk_subext, MASK_ZVKNHA), - RISCV_EXT_FLAG_ENTRY ("zvknhb", x_riscv_zvk_subext, MASK_ZVKNHB), - RISCV_EXT_FLAG_ENTRY ("zvksed", x_riscv_zvk_subext, MASK_ZVKSED), - RISCV_EXT_FLAG_ENTRY ("zvksh", x_riscv_zvk_subext, MASK_ZVKSH), - RISCV_EXT_FLAG_ENTRY ("zvkn", x_riscv_zvk_subext, MASK_ZVKN), - RISCV_EXT_FLAG_ENTRY ("zvknc", x_riscv_zvk_subext, MASK_ZVKNC), - RISCV_EXT_FLAG_ENTRY ("zvkng", x_riscv_zvk_subext, MASK_ZVKNG), - RISCV_EXT_FLAG_ENTRY ("zvks", x_riscv_zvk_subext, MASK_ZVKS), - RISCV_EXT_FLAG_ENTRY ("zvksc", x_riscv_zvk_subext, MASK_ZVKSC), - RISCV_EXT_FLAG_ENTRY ("zvksg", x_riscv_zvk_subext, MASK_ZVKSG), - RISCV_EXT_FLAG_ENTRY ("zvkt", x_riscv_zvk_subext, MASK_ZVKT), - - RISCV_EXT_FLAG_ENTRY ("zvl32b", x_riscv_zvl_flags, MASK_ZVL32B), - RISCV_EXT_FLAG_ENTRY ("zvl64b", x_riscv_zvl_flags, MASK_ZVL64B), - RISCV_EXT_FLAG_ENTRY ("zvl128b", x_riscv_zvl_flags, MASK_ZVL128B), - RISCV_EXT_FLAG_ENTRY ("zvl256b", x_riscv_zvl_flags, MASK_ZVL256B), - RISCV_EXT_FLAG_ENTRY ("zvl512b", x_riscv_zvl_flags, MASK_ZVL512B), - RISCV_EXT_FLAG_ENTRY ("zvl1024b", x_riscv_zvl_flags, MASK_ZVL1024B), - RISCV_EXT_FLAG_ENTRY ("zvl2048b", x_riscv_zvl_flags, MASK_ZVL2048B), - RISCV_EXT_FLAG_ENTRY ("zvl4096b", x_riscv_zvl_flags, MASK_ZVL4096B), - RISCV_EXT_FLAG_ENTRY ("zvl8192b", x_riscv_zvl_flags, MASK_ZVL8192B), - RISCV_EXT_FLAG_ENTRY ("zvl16384b", x_riscv_zvl_flags, MASK_ZVL16384B), - RISCV_EXT_FLAG_ENTRY ("zvl32768b", x_riscv_zvl_flags, MASK_ZVL32768B), - RISCV_EXT_FLAG_ENTRY ("zvl65536b", x_riscv_zvl_flags, MASK_ZVL65536B), - - RISCV_EXT_FLAG_ENTRY ("zfbfmin", x_riscv_zf_subext, MASK_ZFBFMIN), - RISCV_EXT_FLAG_ENTRY ("zfhmin", x_riscv_zf_subext, MASK_ZFHMIN), - RISCV_EXT_FLAG_ENTRY ("zfh", x_riscv_zf_subext, MASK_ZFH), - RISCV_EXT_FLAG_ENTRY ("zvfbfmin", x_riscv_zf_subext, MASK_ZVFBFMIN), - RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_zf_subext, MASK_ZVFBFWMA), - RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_zf_subext, MASK_ZVFHMIN), - RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_zf_subext, MASK_ZVFH), - - RISCV_EXT_FLAG_ENTRY ("zfa", x_riscv_zfa_subext, MASK_ZFA), - - RISCV_EXT_FLAG_ENTRY ("zmmul", x_riscv_zm_subext, MASK_ZMMUL), - - /* Code-size reduction extensions. */ - RISCV_EXT_FLAG_ENTRY ("zca", x_riscv_zc_subext, MASK_ZCA), - RISCV_EXT_FLAG_ENTRY ("zcb", x_riscv_zc_subext, MASK_ZCB), - RISCV_EXT_FLAG_ENTRY ("zce", x_riscv_zc_subext, MASK_ZCE), - RISCV_EXT_FLAG_ENTRY ("zcf", x_riscv_zc_subext, MASK_ZCF), - RISCV_EXT_FLAG_ENTRY ("zcd", x_riscv_zc_subext, MASK_ZCD), - RISCV_EXT_FLAG_ENTRY ("zcmp", x_riscv_zc_subext, MASK_ZCMP), - RISCV_EXT_FLAG_ENTRY ("zcmt", x_riscv_zc_subext, MASK_ZCMT), - RISCV_EXT_FLAG_ENTRY ("zclsd", x_riscv_zc_subext, MASK_ZCLSD), - - RISCV_EXT_FLAG_ENTRY ("svade", x_riscv_sv_subext, MASK_SVADE), - RISCV_EXT_FLAG_ENTRY ("svadu", x_riscv_sv_subext, MASK_SVADU), - RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL), - RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT), - RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC), - - RISCV_EXT_FLAG_ENTRY ("ssnpm", x_riscv_ss_subext, MASK_SSNPM), - RISCV_EXT_FLAG_ENTRY ("smnpm", x_riscv_sm_subext, MASK_SMNPM), - RISCV_EXT_FLAG_ENTRY ("smmpm", x_riscv_sm_subext, MASK_SMMPM), - RISCV_EXT_FLAG_ENTRY ("sspm", x_riscv_ss_subext, MASK_SSPM), - RISCV_EXT_FLAG_ENTRY ("supm", x_riscv_su_subext, MASK_SUPM), - - RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO), - - RISCV_EXT_FLAG_ENTRY ("xcvmac", x_riscv_xcv_subext, MASK_XCVMAC), - RISCV_EXT_FLAG_ENTRY ("xcvalu", x_riscv_xcv_subext, MASK_XCVALU), - RISCV_EXT_FLAG_ENTRY ("xcvelw", x_riscv_xcv_subext, MASK_XCVELW), - RISCV_EXT_FLAG_ENTRY ("xcvsimd", x_riscv_xcv_subext, MASK_XCVSIMD), - RISCV_EXT_FLAG_ENTRY ("xcvbi", x_riscv_xcv_subext, MASK_XCVBI), - - RISCV_EXT_FLAG_ENTRY ("xtheadba", x_riscv_xthead_subext, MASK_XTHEADBA), - RISCV_EXT_FLAG_ENTRY ("xtheadbb", x_riscv_xthead_subext, MASK_XTHEADBB), - RISCV_EXT_FLAG_ENTRY ("xtheadbs", x_riscv_xthead_subext, MASK_XTHEADBS), - RISCV_EXT_FLAG_ENTRY ("xtheadcmo", x_riscv_xthead_subext, MASK_XTHEADCMO), - RISCV_EXT_FLAG_ENTRY ("xtheadcondmov", x_riscv_xthead_subext, MASK_XTHEADCONDMOV), - RISCV_EXT_FLAG_ENTRY ("xtheadfmemidx", x_riscv_xthead_subext, MASK_XTHEADFMEMIDX), - RISCV_EXT_FLAG_ENTRY ("xtheadfmv", x_riscv_xthead_subext, MASK_XTHEADFMV), - RISCV_EXT_FLAG_ENTRY ("xtheadint", x_riscv_xthead_subext, MASK_XTHEADINT), - RISCV_EXT_FLAG_ENTRY ("xtheadmac", x_riscv_xthead_subext, MASK_XTHEADMAC), - RISCV_EXT_FLAG_ENTRY ("xtheadmemidx", x_riscv_xthead_subext, MASK_XTHEADMEMIDX), - RISCV_EXT_FLAG_ENTRY ("xtheadmempair", x_riscv_xthead_subext, MASK_XTHEADMEMPAIR), - RISCV_EXT_FLAG_ENTRY ("xtheadsync", x_riscv_xthead_subext, MASK_XTHEADSYNC), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_xthead_subext, MASK_XTHEADVECTOR), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64), RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL32B), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL64B), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL128B), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zf_subext, MASK_ZVFHMIN), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zf_subext, MASK_ZVFH), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_target_flags, MASK_FULL_V), - RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_target_flags, MASK_VECTOR), - - RISCV_EXT_FLAG_ENTRY ("xventanacondops", x_riscv_xventana_subext, MASK_XVENTANACONDOPS), - - RISCV_EXT_FLAG_ENTRY ("xsfvcp", x_riscv_sifive_subext, MASK_XSFVCP), - RISCV_EXT_FLAG_ENTRY ("xsfcease", x_riscv_sifive_subext, MASK_XSFCEASE), - RISCV_EXT_FLAG_ENTRY ("xsfvqmaccqoq", x_riscv_sifive_subext, MASK_XSFVQMACCQOQ), - RISCV_EXT_FLAG_ENTRY ("xsfvqmaccdod", x_riscv_sifive_subext, MASK_XSFVQMACCDOD), - RISCV_EXT_FLAG_ENTRY ("xsfvfnrclipxfqf", x_riscv_sifive_subext, MASK_XSFVFNRCLIPXFQF), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_subext, MASK_ZVL32B), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_subext, MASK_ZVL64B), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_subext, MASK_ZVL128B), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvf_subext, MASK_ZVFHMIN), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvf_subext, MASK_ZVFH), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_FULL_V), + RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_VECTOR), {NULL, NULL, NULL, 0} }; +/* Add extra extension flags into FLAG_TABLE for EXT. */ +static void +apply_extra_extension_flags (const char *ext, + std::vector<riscv_ext_flag_table_t> &flag_table) +{ + const riscv_extra_ext_flag_table_t *arch_ext_flag_tab; + for (arch_ext_flag_tab = &riscv_extra_ext_flag_table[0]; + arch_ext_flag_tab->ext; ++arch_ext_flag_tab) + { + if (strcmp (arch_ext_flag_tab->ext, ext) == 0) + { + flag_table.push_back ({arch_ext_flag_tab->var_ref, + arch_ext_flag_tab->cl_var_ref, + arch_ext_flag_tab->mask}); + } + } +} + /* Types for recording extension to RISC-V C-API bitmask. */ struct riscv_ext_bitmask_table_t { const char *ext; @@ -1995,24 +1556,21 @@ riscv_set_arch_by_subset_list (riscv_subset_list *subset_list, { if (opts) { - const riscv_ext_flag_table_t *arch_ext_flag_tab; /* Clean up target flags before we set. */ - for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; arch_ext_flag_tab->ext; - ++arch_ext_flag_tab) - opts->*arch_ext_flag_tab->var_ref &= ~arch_ext_flag_tab->mask; + for (const auto &[ext_name, ext_info] : riscv_ext_infos) + ext_info.clean_opts (opts); if (subset_list->xlen () == 32) - opts->x_target_flags &= ~MASK_64BIT; + opts->x_riscv_isa_flags &= ~MASK_64BIT; else if (subset_list->xlen () == 64) - opts->x_target_flags |= MASK_64BIT; + opts->x_riscv_isa_flags |= MASK_64BIT; - for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; - arch_ext_flag_tab->ext; - ++arch_ext_flag_tab) - { - if (subset_list->lookup (arch_ext_flag_tab->ext)) - opts->*arch_ext_flag_tab->var_ref |= arch_ext_flag_tab->mask; - } + for (const auto &[ext_name, ext_info] : riscv_ext_infos) + if (subset_list->lookup (ext_name.c_str ())) + { + /* Set the extension flag. */ + ext_info.set_opts (opts); + } } } @@ -2022,37 +1580,14 @@ bool riscv_ext_is_subset (struct cl_target_option *opts, struct cl_target_option *subset) { - const riscv_ext_flag_table_t *arch_ext_flag_tab; - for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; - arch_ext_flag_tab->ext; - ++arch_ext_flag_tab) + for (const auto &[ext_name, ext_info] : riscv_ext_infos) { - if (subset->*arch_ext_flag_tab->cl_var_ref & arch_ext_flag_tab->mask) - { - if (!(opts->*arch_ext_flag_tab->cl_var_ref & arch_ext_flag_tab->mask)) - return false; - } + if (ext_info.check_opts (opts) && !ext_info.check_opts (subset)) + return false; } return true; } -/* Return the mask of ISA extension in x_target_flags of gcc_options. */ - -int -riscv_x_target_flags_isa_mask (void) -{ - int mask = 0; - const riscv_ext_flag_table_t *arch_ext_flag_tab; - for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; - arch_ext_flag_tab->ext; - ++arch_ext_flag_tab) - { - if (arch_ext_flag_tab->var_ref == &gcc_options::x_target_flags) - mask |= arch_ext_flag_tab->mask; - } - return mask; -} - /* Get the minimal feature bits in Linux hwprobe of the given ISA string. Used for generating Function Multi-Versioning (FMV) dispatcher for RISC-V. @@ -2107,20 +1642,18 @@ riscv_minimal_hwprobe_feature_bits (const char *isa, search_q.pop (); /* Iterate through the implied extension table. */ - const riscv_implied_info_t *implied_info; - for (implied_info = &riscv_implied_info[0]; - implied_info->ext; - ++implied_info) + auto &ext_info = get_riscv_ext_info (search_ext); + for (const auto &implied_ext : ext_info.implied_exts ()) { /* When the search extension matches the implied extension and the implied extension has not been visited, mark the implied extension in the implied_exts set and push it into the queue. */ - if (implied_info->match (subset_list, search_ext) - && implied_exts.count (implied_info->implied_ext) == 0) + if (implied_ext.match (subset_list) + && implied_exts.count (implied_ext.implied_ext) == 0) { - implied_exts.insert (implied_info->implied_ext); - search_q.push (implied_info->implied_ext); + implied_exts.insert (implied_ext.implied_ext); + search_q.push (implied_ext.implied_ext); } } } @@ -2674,16 +2207,15 @@ riscv_arch_help (int, const char **) } }; std::map<std::string, std::set<unsigned>, extension_comparator> all_exts; - for (const riscv_ext_version &ext : riscv_ext_version_table) + for (const auto &[ext_name, ext_info] : riscv_ext_infos) { - if (!ext.name) - break; - if (ext.name[0] == 'g') - continue; - unsigned version_value = (ext.major_version * RISCV_MAJOR_VERSION_BASE) - + (ext.minor_version - * RISCV_MINOR_VERSION_BASE); - all_exts[ext.name].insert(version_value); + for (auto &supported_version : ext_info.supported_versions ()) + { + unsigned version_value + = (supported_version.major_version * RISCV_MAJOR_VERSION_BASE) + + (supported_version.minor_version * RISCV_MINOR_VERSION_BASE); + all_exts[ext_name].insert (version_value); + } } printf("All available -march extensions for RISC-V:\n"); diff --git a/gcc/config.gcc b/gcc/config.gcc index 2454ec7..e552f469 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -558,6 +558,7 @@ riscv*) extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h sifive_vector.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h" + extra_options="${extra_options} riscv/riscv-ext.opt" ;; rs6000*-*-*) extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt" diff --git a/gcc/config/riscv/gen-riscv-ext-opt.cc b/gcc/config/riscv/gen-riscv-ext-opt.cc new file mode 100644 index 0000000..17b8f5b --- /dev/null +++ b/gcc/config/riscv/gen-riscv-ext-opt.cc @@ -0,0 +1,105 @@ +#include <vector> +#include <string> +#include <set> +#include <stdio.h> +#include "riscv-opts.h" + +struct version_t +{ + int major; + int minor; + version_t (int major, int minor, + enum riscv_isa_spec_class spec = ISA_SPEC_CLASS_NONE) + : major (major), minor (minor) + {} + bool operator<(const version_t &other) const + { + if (major != other.major) + return major < other.major; + return minor < other.minor; + } + + bool operator== (const version_t &other) const + { + return major == other.major && minor == other.minor; + } +}; + +static void +print_ext_doc_entry (const std::string &ext_name, const std::string &full_name, + const std::string &desc, + const std::vector<version_t> &supported_versions) +{ + // Implementation of the function to print the documentation entry + // for the extension. + std::set<version_t> unique_versions; + for (const auto &version : supported_versions) + unique_versions.insert (version); + printf ("@item %s\n", ext_name.c_str ()); + printf ("@tab"); + for (const auto &version : unique_versions) + { + printf (" %d.%d", version.major, version.minor); + } + printf ("\n"); + printf ("@tab %s", full_name.c_str ()); + if (desc.size ()) + printf (", %s", desc.c_str ()); + printf ("\n\n"); +} + +int +main () +{ + puts ("; Target options for the RISC-V port of the compiler"); + puts (";"); + puts ("; Copyright (C) 2025 Free Software Foundation, Inc."); + puts (";"); + puts ("; This file is part of GCC."); + puts (";"); + puts ( + "; GCC is free software; you can redistribute it and/or modify it under"); + puts ( + "; the terms of the GNU General Public License as published by the Free"); + puts ( + "; Software Foundation; either version 3, or (at your option) any later"); + puts ("; version."); + puts (";"); + puts ("; GCC is distributed in the hope that it will be useful, but WITHOUT"); + puts ("; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY"); + puts ("; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public"); + puts ("; License for more details."); + puts (";"); + puts ("; You should have received a copy of the GNU General Public License"); + puts ("; along with GCC; see the file COPYING3. If not see "); + puts ("; <http://www.gnu.org/licenses/>."); + + puts ("; This file is generated automatically using"); + puts ("; gcc/config/riscv/gen-riscv-ext-opt.cc from:"); + puts ("; gcc/config/riscv/riscv-ext.def"); + puts (""); + puts ("; Please *DO NOT* edit manually."); + + std::set<std::string> all_vars; +#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ + SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ + BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ + all_vars.insert ("riscv_" #FLAG_GROUP "_subext"); +#include "riscv-ext.def" +#undef DEFINE_RISCV_EXT + + for (auto var : all_vars) + { + puts ("TargetVariable"); + printf ("int %s\n\n", var.c_str ()); + } + +#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ + SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ + BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ + puts ("Mask(" #UPPERCAE_NAME ") Var(riscv_" #FLAG_GROUP "_subext)\n"); +#include "riscv-ext.def" +#undef DEFINE_RISCV_EXT + + return 0; +} diff --git a/gcc/config/riscv/gen-riscv-ext-texi.cc b/gcc/config/riscv/gen-riscv-ext-texi.cc new file mode 100644 index 0000000..e15fdbf --- /dev/null +++ b/gcc/config/riscv/gen-riscv-ext-texi.cc @@ -0,0 +1,88 @@ +#include <vector> +#include <string> +#include <set> +#include <stdio.h> +#include "riscv-opts.h" + +struct version_t +{ + int major; + int minor; + version_t (int major, int minor, + enum riscv_isa_spec_class spec = ISA_SPEC_CLASS_NONE) + : major (major), minor (minor) + {} + bool operator<(const version_t &other) const + { + if (major != other.major) + return major < other.major; + return minor < other.minor; + } + + bool operator== (const version_t &other) const + { + return major == other.major && minor == other.minor; + } +}; + +static void +print_ext_doc_entry (const std::string &ext_name, const std::string &full_name, + const std::string &desc, + const std::vector<version_t> &supported_versions) +{ + // Implementation of the function to print the documentation entry + // for the extension. + std::set<version_t> unique_versions; + for (const auto &version : supported_versions) + unique_versions.insert (version); + printf ("@item %s\n", ext_name.c_str ()); + printf ("@tab"); + for (const auto &version : unique_versions) + { + printf (" %d.%d", version.major, version.minor); + } + printf ("\n"); + printf ("@tab %s", full_name.c_str ()); + if (desc.size ()) + printf (", %s", desc.c_str ()); + printf ("\n\n"); +} + +int +main () +{ + puts ("@c Copyright (C) 2025 Free Software Foundation, Inc."); + puts ("@c This is part of the GCC manual."); + puts ("@c For copying conditions, see the file gcc/doc/include/fdl.texi."); + puts (""); + puts ("@c This file is generated automatically using"); + puts ("@c gcc/config/riscv/gen-riscv-ext-texi.cc from:"); + puts ("@c gcc/config/riscv/riscv-ext.def"); + puts ("@c gcc/config/riscv/riscv-opts.h"); + puts (""); + puts ("@c Please *DO NOT* edit manually."); + puts (""); + puts ("@multitable @columnfractions .10 .10 .80"); + puts ("@headitem Extension Name @tab Supported Version @tab Description"); + puts (""); + + /* g extension is a very speical extension that no clear version... */ + puts ("@item g"); + puts ("@tab -"); + puts ( + "@tab General-purpose computing base extension, @samp{g} will expand to"); + puts ("@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and"); + puts ("@samp{zifencei}."); + puts (""); + +#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ + SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ + BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ + print_ext_doc_entry (#NAME, FULL_NAME, DESC, \ + std::vector<version_t> SUPPORTED_VERSIONS); +#include "riscv-ext.def" +#undef DEFINE_RISCV_EXT + + puts ("@end multitable"); + return 0; +} diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index ab6dc83..1ff1968 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -36,10 +36,10 @@ along with GCC; see the file COPYING3. If not see struct pragma_intrinsic_flags { - int intrinsic_target_flags; + int intrinsic_riscv_isa_flags; int intrinsic_riscv_vector_elen_flags; - int intrinsic_riscv_zvl_flags; + int intrinsic_riscv_zvl_subext; int intrinsic_riscv_zvb_subext; int intrinsic_riscv_zvk_subext; }; @@ -47,16 +47,16 @@ struct pragma_intrinsic_flags static void riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) { - flags->intrinsic_target_flags = target_flags; + flags->intrinsic_riscv_isa_flags = riscv_isa_flags; flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags; - flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags; + flags->intrinsic_riscv_zvl_subext = riscv_zvl_subext; flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext; flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext; - target_flags = target_flags + riscv_isa_flags = riscv_isa_flags | MASK_VECTOR; - riscv_zvl_flags = riscv_zvl_flags + riscv_zvl_subext = riscv_zvl_subext | MASK_ZVL32B | MASK_ZVL64B | MASK_ZVL128B @@ -97,10 +97,10 @@ riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags) static void riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *flags) { - target_flags = flags->intrinsic_target_flags; + riscv_isa_flags = flags->intrinsic_riscv_isa_flags; riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags; - riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags; + riscv_zvl_subext = flags->intrinsic_riscv_zvl_subext; riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext; riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext; } diff --git a/gcc/config/riscv/riscv-ext-corev.def b/gcc/config/riscv/riscv-ext-corev.def new file mode 100644 index 0000000..eb97399 --- /dev/null +++ b/gcc/config/riscv/riscv-ext-corev.def @@ -0,0 +1,87 @@ +/* CORE-V extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ + +DEFINE_RISCV_EXT( + /* NAME */ xcvalu, + /* UPPERCAE_NAME */ XCVALU, + /* FULL_NAME */ "Core-V miscellaneous ALU extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xcvbi, + /* UPPERCAE_NAME */ XCVBI, + /* FULL_NAME */ "xcvbi extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xcvelw, + /* UPPERCAE_NAME */ XCVELW, + /* FULL_NAME */ "Core-V event load word extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xcvmac, + /* UPPERCAE_NAME */ XCVMAC, + /* FULL_NAME */ "Core-V multiply-accumulate extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xcvsimd, + /* UPPERCAE_NAME */ XCVSIMD, + /* FULL_NAME */ "xcvsimd extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xcv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext-sifive.def b/gcc/config/riscv/riscv-ext-sifive.def new file mode 100644 index 0000000..c8d79da --- /dev/null +++ b/gcc/config/riscv/riscv-ext-sifive.def @@ -0,0 +1,87 @@ +/* SiFive extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ + +DEFINE_RISCV_EXT( + /* NAME */ xsfcease, + /* UPPERCAE_NAME */ XSFCEASE, + /* FULL_NAME */ "xsfcease extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xsfvcp, + /* UPPERCAE_NAME */ XSFVCP, + /* FULL_NAME */ "xsfvcp extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xsfvfnrclipxfqf, + /* UPPERCAE_NAME */ XSFVFNRCLIPXFQF, + /* FULL_NAME */ "xsfvfnrclipxfqf extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xsfvqmaccdod, + /* UPPERCAE_NAME */ XSFVQMACCDOD, + /* FULL_NAME */ "xsfvqmaccdod extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xsfvqmaccqoq, + /* UPPERCAE_NAME */ XSFVQMACCQOQ, + /* FULL_NAME */ "xsfvqmaccqoq extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xsf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext-thead.def b/gcc/config/riscv/riscv-ext-thead.def new file mode 100644 index 0000000..327d2ae --- /dev/null +++ b/gcc/config/riscv/riscv-ext-thead.def @@ -0,0 +1,191 @@ +/* T-head extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ + +DEFINE_RISCV_EXT( + /* NAME */ xtheadba, + /* UPPERCAE_NAME */ XTHEADBA, + /* FULL_NAME */ "T-head address calculation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadbb, + /* UPPERCAE_NAME */ XTHEADBB, + /* FULL_NAME */ "T-head basic bit-manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadbs, + /* UPPERCAE_NAME */ XTHEADBS, + /* FULL_NAME */ "T-head single-bit instructions extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadcmo, + /* UPPERCAE_NAME */ XTHEADCMO, + /* FULL_NAME */ "T-head cache management operations extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadcondmov, + /* UPPERCAE_NAME */ XTHEADCONDMOV, + /* FULL_NAME */ "T-head conditional move extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadfmemidx, + /* UPPERCAE_NAME */ XTHEADFMEMIDX, + /* FULL_NAME */ "T-head indexed memory operations for floating-point registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadfmv, + /* UPPERCAE_NAME */ XTHEADFMV, + /* FULL_NAME */ "T-head double floating-point high-bit data transmission extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadint, + /* UPPERCAE_NAME */ XTHEADINT, + /* FULL_NAME */ "T-head acceleration interruption extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadmac, + /* UPPERCAE_NAME */ XTHEADMAC, + /* FULL_NAME */ "T-head multiply-accumulate extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadmemidx, + /* UPPERCAE_NAME */ XTHEADMEMIDX, + /* FULL_NAME */ "T-head indexed memory operation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadmempair, + /* UPPERCAE_NAME */ XTHEADMEMPAIR, + /* FULL_NAME */ "T-head two-GPR memory operation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadsync, + /* UPPERCAE_NAME */ XTHEADSYNC, + /* FULL_NAME */ "T-head multi-core synchronization extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ xtheadvector, + /* UPPERCAE_NAME */ XTHEADVECTOR, + /* FULL_NAME */ "xtheadvector extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xthead, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext-ventana.def b/gcc/config/riscv/riscv-ext-ventana.def new file mode 100644 index 0000000..deed47f --- /dev/null +++ b/gcc/config/riscv/riscv-ext-ventana.def @@ -0,0 +1,35 @@ +/* Ventana extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ + +DEFINE_RISCV_EXT( + /* NAME */ xventanacondops, + /* UPPERCAE_NAME */ XVENTANACONDOPS, + /* FULL_NAME */ "Ventana integer conditional operations extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ xventana, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def new file mode 100644 index 0000000..34742d9 --- /dev/null +++ b/gcc/config/riscv/riscv-ext.def @@ -0,0 +1,1824 @@ +/* RISC-V extension definition file for RISC-V. + Copyright (C) 2025 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. + +Please run `make riscv-regen` in build folder to make sure updated anything. + +Format of DEFINE_RISCV_EXT: + NAME: + The name of the extension, e.g. "i". + UPPERCASE_NAME: + The name of the extension in uppercase, e.g. "ZBA", this used + for generate TARGET_<ext-name> marco and MASK_<ext-name> macro. + For those extension only named with single letter, it should also come with + 'RV', e.g. 'v' should use 'RVV' here. + Some of old extension like 'i' and 'm' are not follow the rule. + FULL_NAME: + The full name of the extension, e.g. "Base integer extension". + DESC: + A short description of the extension, this will used during generating + documentation, GNU Texinfo format can be used this field. + URL: + A URL for the extension. + DEP_EXTS: + A list of dependent extensions, this is a list of strings or + a list of tuples. The first element of the tuple is the name + of the extension and the second element is a function that + takes a subset_list and returns true if the extension should be added as + a dependent extension, `c` and `zca` are examples of this. + SUPPORTED_VERSIONS: + A list of tuples, each tuple contains the major version number, minor + version number and the class of the specification. The version number is a + list of integers, e.g. {2, 0} for version 2.0. The class is + a string, e.g. "ISA_SPEC_CLASS_20191213", the class of the + specification is not required for any new extension. + FLAG_GROUP: + The group of the extension, this is used to group extensions + together. The group is a string, e.g. "base", "zi", "zm", "za", "zf", + "zc", "zb", "zk" and "zi". + This should be auto generated in theory in some day... + BITMASK_GROUP_ID: + The group id of the extension for the __riscv_feature_bits. + this field should sync with riscv-c-api-doc, and keep BITMASK_NOT_YET_ALLOCATED + if not got allocated. + https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions + BITMASK_BIT_POSITION: + The bit position of the extension for the __riscv_feature_bits. + this field should sync with riscv-c-api-doc, and keep BITMASK_NOT_YET_ALLOCATED + if not got allocated. + https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions + EXTRA_EXTENSION_FLAGS: + Extra flags for the extension, this is a bitmask of the + extra flags. The extra flags are: + - EXT_FLAG_MACRO: Set this flag if this extension is just a macro of set of + extensions, and not define any new instrcutions, new CSRs or new + behaviors, the example is `b` extension is just a macro of `zba`, `zbb` + and `zbs`. +*/ + +DEFINE_RISCV_EXT( + /* NAME */ e, + /* UPPERCAE_NAME */ RVE, + /* FULL_NAME */ "Reduced base integer extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ i, + /* UPPERCAE_NAME */ RVI, + /* FULL_NAME */ "Base integer extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 1, ISA_SPEC_CLASS_20191213}, + {2, 1, ISA_SPEC_CLASS_20190608}, + {2, 0, ISA_SPEC_CLASS_2P2}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 8, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ m, + /* UPPERCAE_NAME */ MUL, + /* FULL_NAME */ "Integer multiplication and division extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zmmul"}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 12, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ a, + /* UPPERCAE_NAME */ ATOMIC, + /* FULL_NAME */ "Atomic extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zaamo", "zalrsc"}), + /* SUPPORTED_VERSIONS */ ({{2, 1, ISA_SPEC_CLASS_20191213}, + {2, 0, ISA_SPEC_CLASS_20190608}, + {2, 0, ISA_SPEC_CLASS_2P2}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 0, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ f, + /* UPPERCAE_NAME */ HARD_FLOAT, + /* FULL_NAME */ "Single-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{2, 2, ISA_SPEC_CLASS_20191213}, + {2, 2, ISA_SPEC_CLASS_20190608}, + {2, 0, ISA_SPEC_CLASS_2P2}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 5, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ d, + /* UPPERCAE_NAME */ DOUBLE_FLOAT, + /* FULL_NAME */ "Double-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f", "zicsr"}), + /* SUPPORTED_VERSIONS */ ({{2, 2, ISA_SPEC_CLASS_20191213}, + {2, 2, ISA_SPEC_CLASS_20190608}, + {2, 0, ISA_SPEC_CLASS_2P2}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 3, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ c, + /* UPPERCAE_NAME */ RVC, + /* FULL_NAME */ "Compressed extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca", + {"zcf", + [] (const riscv_subset_list *subset_list) -> bool + { + return subset_list->xlen () == 32 + && subset_list->lookup ("f"); + }}, + {"zcd", + [] (const riscv_subset_list *subset_list) -> bool + { + return subset_list->lookup ("d"); + }}}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 2, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ b, + /* UPPERCAE_NAME */ RVB, + /* FULL_NAME */ "b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zba", "zbb", "zbs"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ v, + /* UPPERCAE_NAME */ RVV, + /* FULL_NAME */ "Vector extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl128b", "zve64d"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 21, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ h, + /* UPPERCAE_NAME */ RVH, + /* FULL_NAME */ "Hypervisor extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ base, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zic64b, + /* UPPERCAE_NAME */ ZIC64B, + /* FULL_NAME */ "Cache block size isf 64 bytes", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicbom, + /* UPPERCAE_NAME */ ZICBOM, + /* FULL_NAME */ "Cache-block management extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicbop, + /* UPPERCAE_NAME */ ZICBOP, + /* FULL_NAME */ "Cache-block prefetch extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicboz, + /* UPPERCAE_NAME */ ZICBOZ, + /* FULL_NAME */ "Cache-block zero extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 37, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ziccamoa, + /* UPPERCAE_NAME */ ZICCAMOA, + /* FULL_NAME */ "Main memory supports all atomics in A", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ziccif, + /* UPPERCAE_NAME */ ZICCIF, + /* FULL_NAME */ "Main memory supports instruction fetch with atomicity requirement", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicclsm, + /* UPPERCAE_NAME */ ZICCLSM, + /* FULL_NAME */ "Main memory supports misaligned loads/stores", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ziccrse, + /* UPPERCAE_NAME */ ZICCRSE, + /* FULL_NAME */ "Main memory supports forward progress on LR/SC sequences", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicfilp, + /* UPPERCAE_NAME */ ZICFILP, + /* FULL_NAME */ "zicfilp extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicfiss, + /* UPPERCAE_NAME */ ZICFISS, + /* FULL_NAME */ "zicfiss extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr", "zimop"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicntr, + /* UPPERCAE_NAME */ ZICNTR, + /* FULL_NAME */ "Standard extension for base counters and timers", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicond, + /* UPPERCAE_NAME */ ZICOND, + /* FULL_NAME */ "Integer conditional operations extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 38, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zicsr, + /* UPPERCAE_NAME */ ZICSR, + /* FULL_NAME */ "Control and status register access extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zifencei, + /* UPPERCAE_NAME */ ZIFENCEI, + /* FULL_NAME */ "Instruction-fetch fence extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zihintntl, + /* UPPERCAE_NAME */ ZIHINTNTL, + /* FULL_NAME */ "Non-temporal locality hints extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 39, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zihintpause, + /* UPPERCAE_NAME */ ZIHINTPAUSE, + /* FULL_NAME */ "Pause hint extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 40, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zihpm, + /* UPPERCAE_NAME */ ZIHPM, + /* FULL_NAME */ "Standard extension for hardware performance counters", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{2, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zimop, + /* UPPERCAE_NAME */ ZIMOP, + /* FULL_NAME */ "zimop extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 1, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zilsd, + /* UPPERCAE_NAME */ ZILSD, + /* FULL_NAME */ "Load/Store pair instructions extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zi, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 1, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zmmul, + /* UPPERCAE_NAME */ ZMMUL, + /* FULL_NAME */ "Integer multiplication extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ za128rs, + /* UPPERCAE_NAME */ ZA128RS, + /* FULL_NAME */ "Reservation set size of 128 bytes", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ za64rs, + /* UPPERCAE_NAME */ ZA64RS, + /* FULL_NAME */ "Reservation set size of 64 bytes", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zaamo, + /* UPPERCAE_NAME */ ZAAMO, + /* FULL_NAME */ "zaamo extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zabha, + /* UPPERCAE_NAME */ ZABHA, + /* FULL_NAME */ "zabha extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zaamo"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zacas, + /* UPPERCAE_NAME */ ZACAS, + /* FULL_NAME */ "zacas extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zaamo"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 26, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zalrsc, + /* UPPERCAE_NAME */ ZALRSC, + /* FULL_NAME */ "zalrsc extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zawrs, + /* UPPERCAE_NAME */ ZAWRS, + /* FULL_NAME */ "Wait-on-reservation-set extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zalrsc"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 7, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zama16b, + /* UPPERCAE_NAME */ ZAMA16B, + /* FULL_NAME */ "Zama16b extension", + /* DESC */ "Misaligned loads, stores, and AMOs to main memory regions that do" + " not cross a naturally aligned 16-byte boundary are atomic.", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ za, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfa, + /* UPPERCAE_NAME */ ZFA, + /* FULL_NAME */ "Additional floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 34, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfbfmin, + /* UPPERCAE_NAME */ ZFBFMIN, + /* FULL_NAME */ "zfbfmin extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zfhmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfh, + /* UPPERCAE_NAME */ ZFH, + /* FULL_NAME */ "Half-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zfhmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 35, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfhmin, + /* UPPERCAE_NAME */ ZFHMIN, + /* FULL_NAME */ "Minimal half-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 36, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zfinx, + /* UPPERCAE_NAME */ ZFINX, + /* FULL_NAME */ "Single-precision floating-point in integer registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zinx, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zdinx, + /* UPPERCAE_NAME */ ZDINX, + /* FULL_NAME */ "Double-precision floating-point in integer registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zfinx", "zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zinx, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zca, + /* UPPERCAE_NAME */ ZCA, + /* FULL_NAME */ "Integer compressed instruction extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({{"c", +[] (const riscv_subset_list *subset_list) -> bool +{ + /* For RV32 Zca implies C for one of these combinations of + extensions: Zca, F_Zca_Zcf and FD_Zca_Zcf_Zcd. */ + if (subset_list->xlen () == 32) + { + if (subset_list->lookup ("d")) + return subset_list->lookup ("zcf") && subset_list->lookup ("zcd"); + + if (subset_list->lookup ("f")) + return subset_list->lookup ("zcf"); + + return true; + } + + /* For RV64 Zca implies C for one of these combinations of + extensions: Zca and FD_Zca_Zcd (Zcf is not available + for RV64). */ + if (subset_list->xlen () == 64) + { + if (subset_list->lookup ("d")) + return subset_list->lookup ("zcd"); + + return true; + } + + /* Do nothing for future RV128 specification. Behaviour + for this case is not yet well defined. */ + return false; + +}}}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 2, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcb, + /* UPPERCAE_NAME */ ZCB, + /* FULL_NAME */ "Simple compressed instruction extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 3, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcd, + /* UPPERCAE_NAME */ ZCD, + /* FULL_NAME */ "Compressed double-precision floating point loads and stores extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 4, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zce, + /* UPPERCAE_NAME */ ZCE, + /* FULL_NAME */ "Compressed instruction extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca", "zcb", "zcmp", "zcmt", + {"zcf", + [] (const riscv_subset_list *subset_list) -> bool + { + return subset_list->xlen () == 32 + && subset_list->lookup ("f"); + }}}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcf, + /* UPPERCAE_NAME */ ZCF, + /* FULL_NAME */ "Compressed single-precision floating point loads and stores extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 5, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcmop, + /* UPPERCAE_NAME */ ZCMOP, + /* FULL_NAME */ "zcmop extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 6, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcmp, + /* UPPERCAE_NAME */ ZCMP, + /* FULL_NAME */ "Compressed push pop extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zcmt, + /* UPPERCAE_NAME */ ZCMT, + /* FULL_NAME */ "Table jump instruction extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca", "zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zclsd, + /* UPPERCAE_NAME */ ZCLSD, + /* FULL_NAME */ "Compressed load/store pair instructions extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zca", "zilsd"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zc, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zba, + /* UPPERCAE_NAME */ ZBA, + /* FULL_NAME */ "Address calculation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 27, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbb, + /* UPPERCAE_NAME */ ZBB, + /* FULL_NAME */ "Basic bit manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 28, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbc, + /* UPPERCAE_NAME */ ZBC, + /* FULL_NAME */ "Carry-less multiplication extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 29, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbkb, + /* UPPERCAE_NAME */ ZBKB, + /* FULL_NAME */ "Cryptography bit-manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 30, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbkc, + /* UPPERCAE_NAME */ ZBKC, + /* FULL_NAME */ "Cryptography carry-less multiply extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 31, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbkx, + /* UPPERCAE_NAME */ ZBKX, + /* FULL_NAME */ "Cryptography crossbar permutation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 32, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zbs, + /* UPPERCAE_NAME */ ZBS, + /* FULL_NAME */ "Single-bit operation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 33, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zk, + /* UPPERCAE_NAME */ ZK, + /* FULL_NAME */ "Standard scalar cryptography extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zkn", "zkr", "zkt"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zkn, + /* UPPERCAE_NAME */ ZKN, + /* FULL_NAME */ "NIST algorithm suite extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zknd, + /* UPPERCAE_NAME */ ZKND, + /* FULL_NAME */ "AES Decryption extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 41, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zkne, + /* UPPERCAE_NAME */ ZKNE, + /* FULL_NAME */ "AES Encryption extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 42, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zknh, + /* UPPERCAE_NAME */ ZKNH, + /* FULL_NAME */ "Hash function extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 43, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zkr, + /* UPPERCAE_NAME */ ZKR, + /* FULL_NAME */ "Entropy source extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zks, + /* UPPERCAE_NAME */ ZKS, + /* FULL_NAME */ "ShangMi algorithm suite extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zbkb", "zbkc", "zbkx", "zksed", "zksh"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zksed, + /* UPPERCAE_NAME */ ZKSED, + /* FULL_NAME */ "SM4 block cipher extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 44, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zksh, + /* UPPERCAE_NAME */ ZKSH, + /* FULL_NAME */ "SM3 hash function extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 45, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zkt, + /* UPPERCAE_NAME */ ZKT, + /* FULL_NAME */ "Data independent execution latency extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 46, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ztso, + /* UPPERCAE_NAME */ ZTSO, + /* FULL_NAME */ "Total store ordering extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zt, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 47, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvbb, + /* UPPERCAE_NAME */ ZVBB, + /* FULL_NAME */ "Vector basic bit-manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvkb"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 48, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvbc, + /* UPPERCAE_NAME */ ZVBC, + /* FULL_NAME */ "Vector carryless multiplication extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve64x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvb, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 49, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve32f, + /* UPPERCAE_NAME */ ZVE32F, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f", "zve32x", "zvl32b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 61, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve32x, + /* UPPERCAE_NAME */ ZVE32X, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr", "zvl32b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 60, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve64d, + /* UPPERCAE_NAME */ ZVE64D, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"d", "zve64f", "zvl64b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 1, + /* BITMASK_BIT_POSITION*/ 0, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve64f, + /* UPPERCAE_NAME */ ZVE64F, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"f", "zve32f", "zve64x", "zvl64b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 63, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zve64x, + /* UPPERCAE_NAME */ ZVE64X, + /* FULL_NAME */ "Vector extensions for embedded processors", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x", "zvl64b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zve, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 62, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfbfmin, + /* UPPERCAE_NAME */ ZVFBFMIN, + /* FULL_NAME */ "Vector BF16 converts extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfbfwma, + /* UPPERCAE_NAME */ ZVFBFWMA, + /* FULL_NAME */ "zvfbfwma extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvfbfmin", "zfbfmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfh, + /* UPPERCAE_NAME */ ZVFH, + /* FULL_NAME */ "Vector half-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f", "zfhmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 50, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfhmin, + /* UPPERCAE_NAME */ ZVFHMIN, + /* FULL_NAME */ "Vector minimal half-precision floating-point extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 51, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkb, + /* UPPERCAE_NAME */ ZVKB, + /* FULL_NAME */ "Vector cryptography bit-manipulation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 52, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkg, + /* UPPERCAE_NAME */ ZVKG, + /* FULL_NAME */ "Vector GCM/GMAC extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 53, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkn, + /* UPPERCAE_NAME */ ZVKN, + /* FULL_NAME */ "Vector NIST Algorithm Suite extension", + /* DESC */ "@samp{zvkn} will expand to", + /* URL */ , + /* DEP_EXTS */ ({"zvkned", "zvknhb", "zvkb", "zvkt"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvknc, + /* UPPERCAE_NAME */ ZVKNC, + /* FULL_NAME */ "Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc}", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvkn", "zvbc"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvkned, + /* UPPERCAE_NAME */ ZVKNED, + /* FULL_NAME */ "Vector AES block cipher extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 54, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkng, + /* UPPERCAE_NAME */ ZVKNG, + /* FULL_NAME */ "Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvkn", "zvkg"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvknha, + /* UPPERCAE_NAME */ ZVKNHA, + /* FULL_NAME */ "Vector SHA-2 secure hash extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 55, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvknhb, + /* UPPERCAE_NAME */ ZVKNHB, + /* FULL_NAME */ "Vector SHA-2 secure hash extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve64x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 56, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvks, + /* UPPERCAE_NAME */ ZVKS, + /* FULL_NAME */ "Vector ShangMi algorithm suite extension, @samp{zvks} will expand", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvksed", "zvksh", "zvkb", "zvkt"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvksc, + /* UPPERCAE_NAME */ ZVKSC, + /* FULL_NAME */ "Vector ShangMi algorithm suite with carryless multiplication extension,", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvks", "zvbc"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvksed, + /* UPPERCAE_NAME */ ZVKSED, + /* FULL_NAME */ "Vector SM4 Block Cipher extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 57, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvksg, + /* UPPERCAE_NAME */ ZVKSG, + /* FULL_NAME */ "Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvks", "zvkg"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ EXT_FLAG_MACRO) + +DEFINE_RISCV_EXT( + /* NAME */ zvksh, + /* UPPERCAE_NAME */ ZVKSH, + /* FULL_NAME */ "Vector SM3 Secure Hash extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 58, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvkt, + /* UPPERCAE_NAME */ ZVKT, + /* FULL_NAME */ "Vector data independent execution latency extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvk, + /* BITMASK_GROUP_ID */ 0, + /* BITMASK_BIT_POSITION*/ 59, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl1024b, + /* UPPERCAE_NAME */ ZVL1024B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl512b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl128b, + /* UPPERCAE_NAME */ ZVL128B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl64b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl16384b, + /* UPPERCAE_NAME */ ZVL16384B, + /* FULL_NAME */ "zvl16384b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl8192b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl2048b, + /* UPPERCAE_NAME */ ZVL2048B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl1024b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl256b, + /* UPPERCAE_NAME */ ZVL256B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl128b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl32768b, + /* UPPERCAE_NAME */ ZVL32768B, + /* FULL_NAME */ "zvl32768b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl16384b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl32b, + /* UPPERCAE_NAME */ ZVL32B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl4096b, + /* UPPERCAE_NAME */ ZVL4096B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl2048b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl512b, + /* UPPERCAE_NAME */ ZVL512B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl256b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl64b, + /* UPPERCAE_NAME */ ZVL64B, + /* FULL_NAME */ "Minimum vector length standard extensions", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl32b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl65536b, + /* UPPERCAE_NAME */ ZVL65536B, + /* FULL_NAME */ "zvl65536b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl32768b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvl8192b, + /* UPPERCAE_NAME */ ZVL8192B, + /* FULL_NAME */ "zvl8192b extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zvl4096b"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvl, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zhinx, + /* UPPERCAE_NAME */ ZHINX, + /* FULL_NAME */ "Half-precision floating-point in integer registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zhinxmin"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zinx, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zhinxmin, + /* UPPERCAE_NAME */ ZHINXMIN, + /* FULL_NAME */ "Minimal half-precision floating-point in integer registers extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zfinx"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zinx, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ sdtrig, + /* UPPERCAE_NAME */ SDTRIG, + /* FULL_NAME */ "sdtrig extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sd, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smaia, + /* UPPERCAE_NAME */ SMAIA, + /* FULL_NAME */ "Advanced interrupt architecture extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"ssaia"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smepmp, + /* UPPERCAE_NAME */ SMEPMP, + /* FULL_NAME */ "PMP Enhancements for memory access and execution prevention on Machine mode", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smmpm, + /* UPPERCAE_NAME */ SMMPM, + /* FULL_NAME */ "smmpm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smnpm, + /* UPPERCAE_NAME */ SMNPM, + /* FULL_NAME */ "smnpm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ smstateen, + /* UPPERCAE_NAME */ SMSTATEEN, + /* FULL_NAME */ "State enable extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"ssstateen"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ssaia, + /* UPPERCAE_NAME */ SSAIA, + /* FULL_NAME */ "Advanced interrupt architecture extension for supervisor-mode", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ sscofpmf, + /* UPPERCAE_NAME */ SSCOFPMF, + /* FULL_NAME */ "Count overflow & filtering extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ssnpm, + /* UPPERCAE_NAME */ SSNPM, + /* FULL_NAME */ "ssnpm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ sspm, + /* UPPERCAE_NAME */ SSPM, + /* FULL_NAME */ "sspm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ssstateen, + /* UPPERCAE_NAME */ SSSTATEEN, + /* FULL_NAME */ "State-enable extension for supervisor-mode", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ sstc, + /* UPPERCAE_NAME */ SSTC, + /* FULL_NAME */ "Supervisor-mode timer interrupts extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ ssstrict, + /* UPPERCAE_NAME */ SSSTRICT, + /* FULL_NAME */ "ssstrict extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ ss, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ supm, + /* UPPERCAE_NAME */ SUPM, + /* FULL_NAME */ "supm extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ su, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svinval, + /* UPPERCAE_NAME */ SVINVAL, + /* FULL_NAME */ "Fine-grained address-translation cache invalidation extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svnapot, + /* UPPERCAE_NAME */ SVNAPOT, + /* FULL_NAME */ "NAPOT translation contiguity extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svpbmt, + /* UPPERCAE_NAME */ SVPBMT, + /* FULL_NAME */ "Page-based memory types extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svvptc, + /* UPPERCAE_NAME */ SVVPTC, + /* FULL_NAME */ "svvptc extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svadu, + /* UPPERCAE_NAME */ SVADU, + /* FULL_NAME */ "Hardware Updating of A/D Bits extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ svade, + /* UPPERCAE_NAME */ SVADE, + /* FULL_NAME */ "Cause exception when hardware updating of A/D bits is disabled", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sv, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +#include "riscv-ext-corev.def" +#include "riscv-ext-sifive.def" +#include "riscv-ext-thead.def" +#include "riscv-ext-ventana.def" diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt new file mode 100644 index 0000000..0c56dc9 --- /dev/null +++ b/gcc/config/riscv/riscv-ext.opt @@ -0,0 +1,404 @@ +; Target options for the RISC-V port of the compiler +; +; Copyright (C) 2025 Free Software Foundation, Inc. +; +; This file is part of GCC. +; +; GCC is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License as published by the Free +; Software Foundation; either version 3, or (at your option) any later +; version. +; +; GCC is distributed in the hope that it will be useful, but WITHOUT +; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +; License for more details. +; +; You should have received a copy of the GNU General Public License +; along with GCC; see the file COPYING3. If not see +; <http://www.gnu.org/licenses/>. +; This file is generated automatically using +; gcc/config/riscv/gen-riscv-ext-opt.cc from: +; gcc/config/riscv/riscv-ext.def + +; Please *DO NOT* edit manually. +TargetVariable +int riscv_base_subext + +TargetVariable +int riscv_sd_subext + +TargetVariable +int riscv_sm_subext + +TargetVariable +int riscv_ss_subext + +TargetVariable +int riscv_su_subext + +TargetVariable +int riscv_sv_subext + +TargetVariable +int riscv_xcv_subext + +TargetVariable +int riscv_xsf_subext + +TargetVariable +int riscv_xthead_subext + +TargetVariable +int riscv_xventana_subext + +TargetVariable +int riscv_za_subext + +TargetVariable +int riscv_zb_subext + +TargetVariable +int riscv_zc_subext + +TargetVariable +int riscv_zf_subext + +TargetVariable +int riscv_zi_subext + +TargetVariable +int riscv_zinx_subext + +TargetVariable +int riscv_zk_subext + +TargetVariable +int riscv_zm_subext + +TargetVariable +int riscv_zt_subext + +TargetVariable +int riscv_zvb_subext + +TargetVariable +int riscv_zve_subext + +TargetVariable +int riscv_zvf_subext + +TargetVariable +int riscv_zvk_subext + +TargetVariable +int riscv_zvl_subext + +Mask(RVE) Var(riscv_base_subext) + +Mask(RVI) Var(riscv_base_subext) + +Mask(MUL) Var(riscv_base_subext) + +Mask(ATOMIC) Var(riscv_base_subext) + +Mask(HARD_FLOAT) Var(riscv_base_subext) + +Mask(DOUBLE_FLOAT) Var(riscv_base_subext) + +Mask(RVC) Var(riscv_base_subext) + +Mask(RVB) Var(riscv_base_subext) + +Mask(RVV) Var(riscv_base_subext) + +Mask(RVH) Var(riscv_base_subext) + +Mask(ZIC64B) Var(riscv_zi_subext) + +Mask(ZICBOM) Var(riscv_zi_subext) + +Mask(ZICBOP) Var(riscv_zi_subext) + +Mask(ZICBOZ) Var(riscv_zi_subext) + +Mask(ZICCAMOA) Var(riscv_zi_subext) + +Mask(ZICCIF) Var(riscv_zi_subext) + +Mask(ZICCLSM) Var(riscv_zi_subext) + +Mask(ZICCRSE) Var(riscv_zi_subext) + +Mask(ZICFILP) Var(riscv_zi_subext) + +Mask(ZICFISS) Var(riscv_zi_subext) + +Mask(ZICNTR) Var(riscv_zi_subext) + +Mask(ZICOND) Var(riscv_zi_subext) + +Mask(ZICSR) Var(riscv_zi_subext) + +Mask(ZIFENCEI) Var(riscv_zi_subext) + +Mask(ZIHINTNTL) Var(riscv_zi_subext) + +Mask(ZIHINTPAUSE) Var(riscv_zi_subext) + +Mask(ZIHPM) Var(riscv_zi_subext) + +Mask(ZIMOP) Var(riscv_zi_subext) + +Mask(ZILSD) Var(riscv_zi_subext) + +Mask(ZMMUL) Var(riscv_zm_subext) + +Mask(ZA128RS) Var(riscv_za_subext) + +Mask(ZA64RS) Var(riscv_za_subext) + +Mask(ZAAMO) Var(riscv_za_subext) + +Mask(ZABHA) Var(riscv_za_subext) + +Mask(ZACAS) Var(riscv_za_subext) + +Mask(ZALRSC) Var(riscv_za_subext) + +Mask(ZAWRS) Var(riscv_za_subext) + +Mask(ZAMA16B) Var(riscv_za_subext) + +Mask(ZFA) Var(riscv_zf_subext) + +Mask(ZFBFMIN) Var(riscv_zf_subext) + +Mask(ZFH) Var(riscv_zf_subext) + +Mask(ZFHMIN) Var(riscv_zf_subext) + +Mask(ZFINX) Var(riscv_zinx_subext) + +Mask(ZDINX) Var(riscv_zinx_subext) + +Mask(ZCA) Var(riscv_zc_subext) + +Mask(ZCB) Var(riscv_zc_subext) + +Mask(ZCD) Var(riscv_zc_subext) + +Mask(ZCE) Var(riscv_zc_subext) + +Mask(ZCF) Var(riscv_zc_subext) + +Mask(ZCMOP) Var(riscv_zc_subext) + +Mask(ZCMP) Var(riscv_zc_subext) + +Mask(ZCMT) Var(riscv_zc_subext) + +Mask(ZCLSD) Var(riscv_zc_subext) + +Mask(ZBA) Var(riscv_zb_subext) + +Mask(ZBB) Var(riscv_zb_subext) + +Mask(ZBC) Var(riscv_zb_subext) + +Mask(ZBKB) Var(riscv_zb_subext) + +Mask(ZBKC) Var(riscv_zb_subext) + +Mask(ZBKX) Var(riscv_zb_subext) + +Mask(ZBS) Var(riscv_zb_subext) + +Mask(ZK) Var(riscv_zk_subext) + +Mask(ZKN) Var(riscv_zk_subext) + +Mask(ZKND) Var(riscv_zk_subext) + +Mask(ZKNE) Var(riscv_zk_subext) + +Mask(ZKNH) Var(riscv_zk_subext) + +Mask(ZKR) Var(riscv_zk_subext) + +Mask(ZKS) Var(riscv_zk_subext) + +Mask(ZKSED) Var(riscv_zk_subext) + +Mask(ZKSH) Var(riscv_zk_subext) + +Mask(ZKT) Var(riscv_zk_subext) + +Mask(ZTSO) Var(riscv_zt_subext) + +Mask(ZVBB) Var(riscv_zvb_subext) + +Mask(ZVBC) Var(riscv_zvb_subext) + +Mask(ZVE32F) Var(riscv_zve_subext) + +Mask(ZVE32X) Var(riscv_zve_subext) + +Mask(ZVE64D) Var(riscv_zve_subext) + +Mask(ZVE64F) Var(riscv_zve_subext) + +Mask(ZVE64X) Var(riscv_zve_subext) + +Mask(ZVFBFMIN) Var(riscv_zvf_subext) + +Mask(ZVFBFWMA) Var(riscv_zvf_subext) + +Mask(ZVFH) Var(riscv_zvf_subext) + +Mask(ZVFHMIN) Var(riscv_zvf_subext) + +Mask(ZVKB) Var(riscv_zvk_subext) + +Mask(ZVKG) Var(riscv_zvk_subext) + +Mask(ZVKN) Var(riscv_zvk_subext) + +Mask(ZVKNC) Var(riscv_zvk_subext) + +Mask(ZVKNED) Var(riscv_zvk_subext) + +Mask(ZVKNG) Var(riscv_zvk_subext) + +Mask(ZVKNHA) Var(riscv_zvk_subext) + +Mask(ZVKNHB) Var(riscv_zvk_subext) + +Mask(ZVKS) Var(riscv_zvk_subext) + +Mask(ZVKSC) Var(riscv_zvk_subext) + +Mask(ZVKSED) Var(riscv_zvk_subext) + +Mask(ZVKSG) Var(riscv_zvk_subext) + +Mask(ZVKSH) Var(riscv_zvk_subext) + +Mask(ZVKT) Var(riscv_zvk_subext) + +Mask(ZVL1024B) Var(riscv_zvl_subext) + +Mask(ZVL128B) Var(riscv_zvl_subext) + +Mask(ZVL16384B) Var(riscv_zvl_subext) + +Mask(ZVL2048B) Var(riscv_zvl_subext) + +Mask(ZVL256B) Var(riscv_zvl_subext) + +Mask(ZVL32768B) Var(riscv_zvl_subext) + +Mask(ZVL32B) Var(riscv_zvl_subext) + +Mask(ZVL4096B) Var(riscv_zvl_subext) + +Mask(ZVL512B) Var(riscv_zvl_subext) + +Mask(ZVL64B) Var(riscv_zvl_subext) + +Mask(ZVL65536B) Var(riscv_zvl_subext) + +Mask(ZVL8192B) Var(riscv_zvl_subext) + +Mask(ZHINX) Var(riscv_zinx_subext) + +Mask(ZHINXMIN) Var(riscv_zinx_subext) + +Mask(SDTRIG) Var(riscv_sd_subext) + +Mask(SMAIA) Var(riscv_sm_subext) + +Mask(SMEPMP) Var(riscv_sm_subext) + +Mask(SMMPM) Var(riscv_sm_subext) + +Mask(SMNPM) Var(riscv_sm_subext) + +Mask(SMSTATEEN) Var(riscv_sm_subext) + +Mask(SSAIA) Var(riscv_ss_subext) + +Mask(SSCOFPMF) Var(riscv_ss_subext) + +Mask(SSNPM) Var(riscv_ss_subext) + +Mask(SSPM) Var(riscv_ss_subext) + +Mask(SSSTATEEN) Var(riscv_ss_subext) + +Mask(SSTC) Var(riscv_ss_subext) + +Mask(SSSTRICT) Var(riscv_ss_subext) + +Mask(SUPM) Var(riscv_su_subext) + +Mask(SVINVAL) Var(riscv_sv_subext) + +Mask(SVNAPOT) Var(riscv_sv_subext) + +Mask(SVPBMT) Var(riscv_sv_subext) + +Mask(SVVPTC) Var(riscv_sv_subext) + +Mask(SVADU) Var(riscv_sv_subext) + +Mask(SVADE) Var(riscv_sv_subext) + +Mask(XCVALU) Var(riscv_xcv_subext) + +Mask(XCVBI) Var(riscv_xcv_subext) + +Mask(XCVELW) Var(riscv_xcv_subext) + +Mask(XCVMAC) Var(riscv_xcv_subext) + +Mask(XCVSIMD) Var(riscv_xcv_subext) + +Mask(XSFCEASE) Var(riscv_xsf_subext) + +Mask(XSFVCP) Var(riscv_xsf_subext) + +Mask(XSFVFNRCLIPXFQF) Var(riscv_xsf_subext) + +Mask(XSFVQMACCDOD) Var(riscv_xsf_subext) + +Mask(XSFVQMACCQOQ) Var(riscv_xsf_subext) + +Mask(XTHEADBA) Var(riscv_xthead_subext) + +Mask(XTHEADBB) Var(riscv_xthead_subext) + +Mask(XTHEADBS) Var(riscv_xthead_subext) + +Mask(XTHEADCMO) Var(riscv_xthead_subext) + +Mask(XTHEADCONDMOV) Var(riscv_xthead_subext) + +Mask(XTHEADFMEMIDX) Var(riscv_xthead_subext) + +Mask(XTHEADFMV) Var(riscv_xthead_subext) + +Mask(XTHEADINT) Var(riscv_xthead_subext) + +Mask(XTHEADMAC) Var(riscv_xthead_subext) + +Mask(XTHEADMEMIDX) Var(riscv_xthead_subext) + +Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) + +Mask(XTHEADSYNC) Var(riscv_xthead_subext) + +Mask(XTHEADVECTOR) Var(riscv_xthead_subext) + +Mask(XVENTANACONDOPS) Var(riscv_xventana_subext) + diff --git a/gcc/config/riscv/riscv-ext.opt.urls b/gcc/config/riscv/riscv-ext.opt.urls new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/gcc/config/riscv/riscv-ext.opt.urls diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 9766b89..0f3bca5 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -136,16 +136,16 @@ enum rvv_vector_bits_enum { /* Bit of riscv_zvl_flags will set continually, N-1 bit will set if N-bit is set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use popcount to calculate the minimal VLEN. */ -#define TARGET_MIN_VLEN \ - ((riscv_zvl_flags == 0) \ - ? 0 \ - : 32 << (__builtin_popcount (riscv_zvl_flags) - 1)) +#define TARGET_MIN_VLEN \ + ((riscv_zvl_subext == 0) \ + ? 0 \ + : 32 << (__builtin_popcount (riscv_zvl_subext) - 1)) /* Same as TARGET_MIN_VLEN, but take an OPTS as gcc_options. */ #define TARGET_MIN_VLEN_OPTS(opts) \ - ((opts->x_riscv_zvl_flags == 0) \ + ((opts->x_riscv_zvl_subext == 0) \ ? 0 \ - : 32 << (__builtin_popcount (opts->x_riscv_zvl_flags) - 1)) + : 32 << (__builtin_popcount (opts->x_riscv_zvl_subext) - 1)) /* The maximum LMUL according to user configuration. */ #define TARGET_MAX_LMUL \ @@ -164,4 +164,12 @@ enum riscv_tls_type { #define GPR2VR_COST_UNPROVIDED -1 +/* Extra extension flags, used for carry extra info for a RISC-V extension. */ +enum +{ + EXT_FLAG_MACRO = 1 << 0, +}; + +#define BITMASK_NOT_YET_ALLOCATED -1 + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h index 7b3fdae..c5d9fab 100644 --- a/gcc/config/riscv/riscv-subset.h +++ b/gcc/config/riscv/riscv-subset.h @@ -129,6 +129,5 @@ extern bool riscv_minimal_hwprobe_feature_bits (const char *, location_t); extern bool riscv_ext_is_subset (struct cl_target_option *, struct cl_target_option *); -extern int riscv_x_target_flags_isa_mask (void); #endif /* ! GCC_RISCV_SUBSET_H */ diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index f3c706bf..f652a12 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3842,26 +3842,26 @@ check_required_extensions (const function_instance &instance) required_extensions |= RVV_REQUIRE_RV64BIT; } - uint64_t riscv_isa_flags = 0; + uint64_t isa_flags = 0; if (TARGET_VECTOR_ELEN_BF_16) - riscv_isa_flags |= RVV_REQUIRE_ELEN_BF_16; + isa_flags |= RVV_REQUIRE_ELEN_BF_16; if (TARGET_VECTOR_ELEN_FP_16) - riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_16; + isa_flags |= RVV_REQUIRE_ELEN_FP_16; if (TARGET_VECTOR_ELEN_FP_32) - riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_32; + isa_flags |= RVV_REQUIRE_ELEN_FP_32; if (TARGET_VECTOR_ELEN_FP_64) - riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_64; + isa_flags |= RVV_REQUIRE_ELEN_FP_64; if (TARGET_VECTOR_ELEN_64) - riscv_isa_flags |= RVV_REQUIRE_ELEN_64; + isa_flags |= RVV_REQUIRE_ELEN_64; if (TARGET_64BIT) - riscv_isa_flags |= RVV_REQUIRE_RV64BIT; + isa_flags |= RVV_REQUIRE_RV64BIT; if (TARGET_FULL_V) - riscv_isa_flags |= RVV_REQUIRE_FULL_V; + isa_flags |= RVV_REQUIRE_FULL_V; if (TARGET_MIN_VLEN > 32) - riscv_isa_flags |= RVV_REQUIRE_MIN_VLEN_64; + isa_flags |= RVV_REQUIRE_MIN_VLEN_64; - uint64_t missing_extensions = required_extensions & ~riscv_isa_flags; + uint64_t missing_extensions = required_extensions & ~isa_flags; if (missing_extensions != 0) return false; return true; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8b77a35..d28aee4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7918,11 +7918,9 @@ riscv_can_inline_p (tree caller, tree callee) struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree); - int isa_flag_mask = riscv_x_target_flags_isa_mask (); - - /* Callee and caller should have the same target options except for ISA. */ - int callee_target_flags = callee_opts->x_target_flags & ~isa_flag_mask; - int caller_target_flags = caller_opts->x_target_flags & ~isa_flag_mask; + /* Callee and caller should have the same target options. */ + int callee_target_flags = callee_opts->x_target_flags; + int caller_target_flags = caller_opts->x_target_flags; if (callee_target_flags != caller_target_flags) return false; diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 9480dc5..527e095 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -168,23 +168,14 @@ momit-leaf-frame-pointer Target Mask(OMIT_LEAF_FRAME_POINTER) Save Omit the frame pointer in leaf functions. -Mask(64BIT) - -Mask(MUL) - -Mask(ATOMIC) - -Mask(HARD_FLOAT) - -Mask(DOUBLE_FLOAT) - -Mask(RVC) +TargetVariable +int riscv_isa_flags -Mask(RVE) +Mask(64BIT) Var(riscv_isa_flags) -Mask(VECTOR) +Mask(VECTOR) Var(riscv_isa_flags) -Mask(FULL_V) +Mask(FULL_V) Var(riscv_isa_flags) mriscv-attribute Target Var(riscv_emit_attribute_p) Init(-1) @@ -233,97 +224,6 @@ TargetVariable long riscv_stack_protector_guard_offset = 0 TargetVariable -int riscv_zi_subext - -Mask(ZICSR) Var(riscv_zi_subext) - -Mask(ZIFENCEI) Var(riscv_zi_subext) - -Mask(ZIHINTNTL) Var(riscv_zi_subext) - -Mask(ZIHINTPAUSE) Var(riscv_zi_subext) - -Mask(ZICOND) Var(riscv_zi_subext) - -Mask(ZICCAMOA) Var(riscv_zi_subext) - -Mask(ZICCIF) Var(riscv_zi_subext) - -Mask(ZICCLSM) Var(riscv_zi_subext) - -Mask(ZICCRSE) Var(riscv_zi_subext) - -Mask(ZICFISS) Var(riscv_zi_subext) - -Mask(ZICFILP) Var(riscv_zi_subext) - -Mask(ZILSD) Var(riscv_zi_subext) - -TargetVariable -int riscv_za_subext - -Mask(ZAWRS) Var(riscv_za_subext) - -Mask(ZAAMO) Var(riscv_za_subext) - -Mask(ZALRSC) Var(riscv_za_subext) - -Mask(ZABHA) Var(riscv_za_subext) - -Mask(ZACAS) Var(riscv_za_subext) - -Mask(ZA64RS) Var(riscv_za_subext) - -Mask(ZA128RS) Var(riscv_za_subext) - -Mask(ZAMA16B) Var(riscv_za_subext) - -TargetVariable -int riscv_zb_subext - -Mask(ZBA) Var(riscv_zb_subext) - -Mask(ZBB) Var(riscv_zb_subext) - -Mask(ZBC) Var(riscv_zb_subext) - -Mask(ZBS) Var(riscv_zb_subext) - -TargetVariable -int riscv_zinx_subext - -Mask(ZFINX) Var(riscv_zinx_subext) - -Mask(ZDINX) Var(riscv_zinx_subext) - -Mask(ZHINX) Var(riscv_zinx_subext) - -Mask(ZHINXMIN) Var(riscv_zinx_subext) - -TargetVariable -int riscv_zk_subext - -Mask(ZBKB) Var(riscv_zk_subext) - -Mask(ZBKC) Var(riscv_zk_subext) - -Mask(ZBKX) Var(riscv_zk_subext) - -Mask(ZKNE) Var(riscv_zk_subext) - -Mask(ZKND) Var(riscv_zk_subext) - -Mask(ZKNH) Var(riscv_zk_subext) - -Mask(ZKR) Var(riscv_zk_subext) - -Mask(ZKSED) Var(riscv_zk_subext) - -Mask(ZKSH) Var(riscv_zk_subext) - -Mask(ZKT) Var(riscv_zk_subext) - -TargetVariable int riscv_vector_elen_flags Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags) @@ -339,232 +239,6 @@ Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags) Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags) TargetVariable -int riscv_zvl_flags - -Mask(ZVL32B) Var(riscv_zvl_flags) - -Mask(ZVL64B) Var(riscv_zvl_flags) - -Mask(ZVL128B) Var(riscv_zvl_flags) - -Mask(ZVL256B) Var(riscv_zvl_flags) - -Mask(ZVL512B) Var(riscv_zvl_flags) - -Mask(ZVL1024B) Var(riscv_zvl_flags) - -Mask(ZVL2048B) Var(riscv_zvl_flags) - -Mask(ZVL4096B) Var(riscv_zvl_flags) - -Mask(ZVL8192B) Var(riscv_zvl_flags) - -Mask(ZVL16384B) Var(riscv_zvl_flags) - -Mask(ZVL32768B) Var(riscv_zvl_flags) - -Mask(ZVL65536B) Var(riscv_zvl_flags) - -TargetVariable -int riscv_zvb_subext - -Mask(ZVBB) Var(riscv_zvb_subext) - -Mask(ZVBC) Var(riscv_zvb_subext) - -Mask(ZVKB) Var(riscv_zvb_subext) - -TargetVariable -int riscv_zvk_subext - -Mask(ZVKG) Var(riscv_zvk_subext) - -Mask(ZVKNED) Var(riscv_zvk_subext) - -Mask(ZVKNHA) Var(riscv_zvk_subext) - -Mask(ZVKNHB) Var(riscv_zvk_subext) - -Mask(ZVKSED) Var(riscv_zvk_subext) - -Mask(ZVKSH) Var(riscv_zvk_subext) - -Mask(ZVKN) Var(riscv_zvk_subext) - -Mask(ZVKNC) Var(riscv_zvk_subext) - -Mask(ZVKNG) Var(riscv_zvk_subext) - -Mask(ZVKS) Var(riscv_zvk_subext) - -Mask(ZVKSC) Var(riscv_zvk_subext) - -Mask(ZVKSG) Var(riscv_zvk_subext) - -Mask(ZVKT) Var(riscv_zvk_subext) - -TargetVariable -int riscv_zicmo_subext - -Mask(ZICBOZ) Var(riscv_zicmo_subext) - -Mask(ZICBOM) Var(riscv_zicmo_subext) - -Mask(ZICBOP) Var(riscv_zicmo_subext) - -Mask(ZIC64B) Var(riscv_zicmo_subext) - -TargetVariable -int riscv_mop_subext - -Mask(ZIMOP) Var(riscv_mop_subext) - -Mask(ZCMOP) Var(riscv_mop_subext) - -TargetVariable -int riscv_zf_subext - -Mask(ZFBFMIN) Var(riscv_zf_subext) - -Mask(ZFHMIN) Var(riscv_zf_subext) - -Mask(ZFH) Var(riscv_zf_subext) - -Mask(ZVFBFMIN) Var(riscv_zf_subext) - -Mask(ZVFBFWMA) Var(riscv_zf_subext) - -Mask(ZVFHMIN) Var(riscv_zf_subext) - -Mask(ZVFH) Var(riscv_zf_subext) - -TargetVariable -int riscv_zfa_subext - -Mask(ZFA) Var(riscv_zfa_subext) - -TargetVariable -int riscv_zm_subext - -Mask(ZMMUL) Var(riscv_zm_subext) - -TargetVariable -int riscv_zc_subext - -Mask(ZCA) Var(riscv_zc_subext) - -Mask(ZCB) Var(riscv_zc_subext) - -Mask(ZCE) Var(riscv_zc_subext) - -Mask(ZCF) Var(riscv_zc_subext) - -Mask(ZCD) Var(riscv_zc_subext) - -Mask(ZCMP) Var(riscv_zc_subext) - -Mask(ZCMT) Var(riscv_zc_subext) - -Mask(ZCLSD) Var(riscv_zc_subext) - -Mask(XCVBI) Var(riscv_xcv_subext) - -TargetVariable -int riscv_sv_subext - -Mask(SVADE) Var(riscv_sv_subext) - -Mask(SVADU) Var(riscv_sv_subext) - -Mask(SVINVAL) Var(riscv_sv_subext) - -Mask(SVNAPOT) Var(riscv_sv_subext) - -Mask(SVVPTC) Var(riscv_sv_subext) - -TargetVariable -int riscv_ss_subext - -Mask(SSNPM) Var(riscv_ss_subext) - -Mask(SSPM) Var(riscv_ss_subext) - -TargetVariable -int riscv_sm_subext - -Mask(SMNPM) Var(riscv_sm_subext) - -Mask(SMMPM) Var(riscv_sm_subext) - -TargetVariable -int riscv_su_subext - -Mask(SUPM) Var(riscv_su_subext) - -TargetVariable -int riscv_ztso_subext - -Mask(ZTSO) Var(riscv_ztso_subext) - -TargetVariable -int riscv_xcv_subext - -Mask(XCVMAC) Var(riscv_xcv_subext) - -Mask(XCVALU) Var(riscv_xcv_subext) - -Mask(XCVELW) Var(riscv_xcv_subext) - -Mask(XCVSIMD) Var(riscv_xcv_subext) - -TargetVariable -int riscv_xthead_subext - -Mask(XTHEADBA) Var(riscv_xthead_subext) - -Mask(XTHEADBB) Var(riscv_xthead_subext) - -Mask(XTHEADBS) Var(riscv_xthead_subext) - -Mask(XTHEADCMO) Var(riscv_xthead_subext) - -Mask(XTHEADCONDMOV) Var(riscv_xthead_subext) - -Mask(XTHEADFMEMIDX) Var(riscv_xthead_subext) - -Mask(XTHEADFMV) Var(riscv_xthead_subext) - -Mask(XTHEADINT) Var(riscv_xthead_subext) - -Mask(XTHEADMAC) Var(riscv_xthead_subext) - -Mask(XTHEADMEMIDX) Var(riscv_xthead_subext) - -Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) - -Mask(XTHEADSYNC) Var(riscv_xthead_subext) - -Mask(XTHEADVECTOR) Var(riscv_xthead_subext) - -TargetVariable -int riscv_xventana_subext - -Mask(XVENTANACONDOPS) Var(riscv_xventana_subext) - -TargetVariable -int riscv_sifive_subext - -Mask(XSFVCP) Var(riscv_sifive_subext) - -Mask(XSFCEASE) Var(riscv_sifive_subext) - -Mask(XSFVQMACCQOQ) Var(riscv_sifive_subext) - -Mask(XSFVQMACCDOD) Var(riscv_sifive_subext) - -Mask(XSFVFNRCLIPXFQF) Var(riscv_sifive_subext) - -TargetVariable int riscv_fmv_priority = 0 Enum diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv index 12e2b6e..e99d668 100644 --- a/gcc/config/riscv/t-riscv +++ b/gcc/config/riscv/t-riscv @@ -187,3 +187,46 @@ s-riscv-vector-type-indexer.gen.defs: build/genrvv-type-indexer$(build_exeext) $(STAMP) s-riscv-vector-type-indexer.gen.defs genprog+=rvv-type-indexer + +RISCV_EXT_DEFS = \ + $(srcdir)/config/riscv/riscv-ext.def \ + $(srcdir)/config/riscv/riscv-ext-corev.def \ + $(srcdir)/config/riscv/riscv-ext.def \ + $(srcdir)/config/riscv/riscv-ext-sifive.def \ + $(srcdir)/config/riscv/riscv-ext-thead.def \ + $(srcdir)/config/riscv/riscv-ext-ventana.def + +$(srcdir)/config/riscv/riscv-ext.opt: $(RISCV_EXT_DEFS) + +$(srcdir)/config/riscv/riscv-ext.opt: s-riscv-ext.opt ; @true + +build/gen-riscv-ext-opt$(build_exeext): $(srcdir)/config/riscv/gen-riscv-ext-opt.cc \ + $(RISCV_EXT_DEFS) + $(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) $< -o $@ + +s-riscv-ext.opt: build/gen-riscv-ext-opt$(build_exeext) + $(RUN_GEN) build/gen-riscv-ext-opt$(build_exeext) > tmp-riscv-ext.opt + $(SHELL) $(srcdir)/../move-if-change tmp-riscv-ext.opt $(srcdir)/config/riscv/riscv-ext.opt + $(STAMP) s-riscv-ext.opt + +build/gen-riscv-ext-texi$(build_exeext): $(srcdir)/config/riscv/gen-riscv-ext-texi.cc \ + $(RISCV_EXT_DEFS) + $(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) $< -o $@ + + +$(srcdir)/doc/riscv-ext.texi: $(RISCV_EXT_DEFS) +$(srcdir)/doc/riscv-ext.texi: s-riscv-ext.texi ; @true + +# Generate the doc when generating option file. +$(srcdir)/config/riscv/riscv-ext.opt: s-riscv-ext.texi ; @true + +s-riscv-ext.texi: build/gen-riscv-ext-texi$(build_exeext) + $(RUN_GEN) build/gen-riscv-ext-texi$(build_exeext) > tmp-riscv-ext.texi + $(SHELL) $(srcdir)/../move-if-change tmp-riscv-ext.texi $(srcdir)/doc/riscv-ext.texi + $(STAMP) s-riscv-ext.texi + +# Run `riscv-regen' after you changed or added anything from riscv-ext*.def + +.PHONY: riscv-regen + +riscv-regen: s-riscv-ext.texi s-riscv-ext.opt diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index f9b93e6..764e158 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,8 @@ +2025-05-12 Jason Merrill <jason@redhat.com> + + PR c++/120012 + * class.cc (check_non_pod_aggregate): Check is_empty_class. + 2025-05-10 Jason Merrill <jason@redhat.com> PR c++/120204 diff --git a/gcc/diagnostic-format-html.cc b/gcc/diagnostic-format-html.cc index 2d642df..6bb1caf 100644 --- a/gcc/diagnostic-format-html.cc +++ b/gcc/diagnostic-format-html.cc @@ -27,11 +27,14 @@ along with GCC; see the file COPYING3. If not see #include "diagnostic-metadata.h" #include "diagnostic-format.h" #include "diagnostic-format-html.h" +#include "diagnostic-format-text.h" #include "diagnostic-output-file.h" #include "diagnostic-buffer.h" #include "selftest.h" #include "selftest-diagnostic.h" #include "pretty-print-format-impl.h" +#include "pretty-print-urlifier.h" +#include "edit-context.h" #include "intl.h" namespace xml { @@ -280,8 +283,8 @@ public: friend class diagnostic_html_format_buffer; html_builder (diagnostic_context &context, - pretty_printer &pp, - const line_maps *line_maps); + pretty_printer &pp, + const line_maps *line_maps); void on_report_diagnostic (const diagnostic_info &diagnostic, diagnostic_t orig_diag_kind, @@ -303,11 +306,27 @@ public: m_printer = &pp; } + std::unique_ptr<xml::element> + make_element_for_metadata (const diagnostic_metadata &metadata); + + std::unique_ptr<xml::element> + make_element_for_source (const diagnostic_info &diagnostic); + + std::unique_ptr<xml::element> + make_element_for_path (const diagnostic_path &path); + + std::unique_ptr<xml::element> + make_element_for_patch (const diagnostic_info &diagnostic); + private: std::unique_ptr<xml::element> make_element_for_diagnostic (const diagnostic_info &diagnostic, diagnostic_t orig_diag_kind); + std::unique_ptr<xml::element> + make_metadata_element (label_text label, + label_text url); + diagnostic_context &m_context; pretty_printer *m_printer; const line_maps *m_line_maps; @@ -560,28 +579,11 @@ html_builder::make_element_for_diagnostic (const diagnostic_info &diagnostic, if (diagnostic.metadata) { - int cwe = diagnostic.metadata->get_cwe (); - if (cwe) - { - diag_element->add_text (label_text::borrow (" ")); - auto cwe_span = make_span (label_text::borrow ("gcc-cwe-metadata")); - cwe_span->add_text (label_text::borrow ("[")); - { - auto anchor = std::make_unique<xml::element> ("a", true); - anchor->set_attr ("href", label_text::take (get_cwe_url (cwe))); - pretty_printer pp; - pp_printf (&pp, "CWE-%i", cwe); - anchor->add_text - (label_text::take (xstrdup (pp_formatted_text (&pp)))); - cwe_span->add_child (std::move (anchor)); - } - cwe_span->add_text (label_text::borrow ("]")); - diag_element->add_child (std::move (cwe_span)); - } + diag_element->add_text (label_text::borrow (" ")); + diag_element->add_child + (make_element_for_metadata (*diagnostic.metadata)); } - // TODO: show any rules - label_text option_text = label_text::take (m_context.make_option_name (diagnostic.option_id, orig_diag_kind, diagnostic.kind)); @@ -608,20 +610,122 @@ html_builder::make_element_for_diagnostic (const diagnostic_info &diagnostic, diag_element->add_child (std::move (option_span)); } + /* Source (and fix-it hints). */ + if (auto source_element = make_element_for_source (diagnostic)) + diag_element->add_child (std::move (source_element)); + + /* Execution path. */ + if (auto path = diagnostic.richloc->get_path ()) + if (auto path_element = make_element_for_path (*path)) + diag_element->add_child (std::move (path_element)); + + if (auto patch_element = make_element_for_patch (diagnostic)) + diag_element->add_child (std::move (patch_element)); + + return diag_element; +} + +std::unique_ptr<xml::element> +html_builder::make_element_for_source (const diagnostic_info &diagnostic) +{ + // TODO: ideally we'd like to capture elements within the following: + m_context.m_last_location = UNKNOWN_LOCATION; + pp_clear_output_area (m_printer); + diagnostic_show_locus (&m_context, + m_context.m_source_printing, + diagnostic.richloc, diagnostic.kind, + m_printer); + auto text = label_text::take (xstrdup (pp_formatted_text (m_printer))); + pp_clear_output_area (m_printer); + + if (strlen (text.get ()) == 0) + return nullptr; + + auto pre = std::make_unique<xml::element> ("pre", true); + pre->set_attr ("class", label_text::borrow ("gcc-annotated-source")); + pre->add_text (std::move (text)); + return pre; +} + +std::unique_ptr<xml::element> +html_builder::make_element_for_path (const diagnostic_path &path) +{ + m_context.m_last_location = UNKNOWN_LOCATION; + diagnostic_text_output_format text_format (m_context); + pp_show_color (text_format.get_printer ()) = false; + pp_buffer (text_format.get_printer ())->m_flush_p = false; + // TODO: ideally we'd like to capture elements within the following: + text_format.print_path (path); + auto text = label_text::take + (xstrdup (pp_formatted_text (text_format.get_printer ()))); + + if (strlen (text.get ()) == 0) + return nullptr; + + auto pre = std::make_unique<xml::element> ("pre", true); + pre->set_attr ("class", label_text::borrow ("gcc-execution-path")); + pre->add_text (std::move (text)); + return pre; +} + +std::unique_ptr<xml::element> +html_builder::make_element_for_patch (const diagnostic_info &diagnostic) +{ + edit_context ec (m_context.get_file_cache ()); + ec.add_fixits (diagnostic.richloc); + if (char *diff = ec.generate_diff (true)) + if (strlen (diff) > 0) + { + auto element = std::make_unique<xml::element> ("pre", true); + element->set_attr ("class", label_text::borrow ("gcc-generated-patch")); + element->add_text (label_text::take (diff)); + return element; + } + return nullptr; +} + +std::unique_ptr<xml::element> +html_builder::make_metadata_element (label_text label, + label_text url) +{ + auto item = make_span (label_text::borrow ("gcc-metadata-item")); + item->add_text (label_text::borrow ("[")); { - auto pre = std::make_unique<xml::element> ("pre", true); - pre->set_attr ("class", label_text::borrow ("gcc-annotated-source")); - // TODO: ideally we'd like to capture elements within the following: - diagnostic_show_locus (&m_context, m_context.m_source_printing, - diagnostic.richloc, diagnostic.kind, - m_printer); - pre->add_text - (label_text::take (xstrdup (pp_formatted_text (m_printer)))); - pp_clear_output_area (m_printer); - diag_element->add_child (std::move (pre)); + auto anchor = std::make_unique<xml::element> ("a", true); + anchor->set_attr ("href", std::move (url)); + anchor->add_child (std::make_unique<xml::text> (std::move (label))); + item->add_child (std::move (anchor)); } + item->add_text (label_text::borrow ("]")); + return item; +} - return diag_element; +std::unique_ptr<xml::element> +html_builder::make_element_for_metadata (const diagnostic_metadata &metadata) +{ + auto span_metadata = make_span (label_text::borrow ("gcc-metadata")); + + int cwe = metadata.get_cwe (); + if (cwe) + { + pretty_printer pp; + pp_printf (&pp, "CWE-%i", cwe); + label_text label = label_text::take (xstrdup (pp_formatted_text (&pp))); + label_text url = label_text::take (get_cwe_url (cwe)); + span_metadata->add_child + (make_metadata_element (std::move (label), std::move (url))); + } + + for (unsigned idx = 0; idx < metadata.get_num_rules (); ++idx) + { + auto &rule = metadata.get_rule (idx); + label_text label = label_text::take (rule.make_description ()); + label_text url = label_text::take (rule.make_url ()); + span_metadata->add_child + (make_metadata_element (std::move (label), std::move (url))); + } + + return span_metadata; } /* Implementation of diagnostic_context::m_diagrams.m_emission_cb @@ -734,6 +838,8 @@ public: return m_builder.get_document (); } + html_builder &get_builder () { return m_builder; } + protected: html_output_format (diagnostic_context &context, const line_maps *line_maps) @@ -852,6 +958,11 @@ public: return m_format->get_document (); } + html_builder &get_builder () const + { + return m_format->get_builder (); + } + private: class html_buffered_output_format : public html_output_format { @@ -880,7 +991,7 @@ test_simple_log () test_html_diagnostic_context dc; rich_location richloc (line_table, UNKNOWN_LOCATION); - dc.report (DK_ERROR, richloc, nullptr, 0, "this is a test: %i", 42); + dc.report (DK_ERROR, richloc, nullptr, 0, "this is a test: %qs", "foo"); const xml::document &doc = dc.get_document (); @@ -899,20 +1010,70 @@ test_simple_log () " <body>\n" " <div class=\"gcc-diagnostic-list\">\n" " <div class=\"gcc-diagnostic\">\n" - " <span class=\"gcc-message\">this is a test: 42</span>\n" - " <pre class=\"gcc-annotated-source\"></pre>\n" + " <span class=\"gcc-message\">this is a test: `<span class=\"gcc-quoted-text\">foo</span>'</span>\n" " </div>\n" " </div>\n" " </body>\n" "</html>")); } +static void +test_metadata () +{ + test_html_diagnostic_context dc; + html_builder &b = dc.get_builder (); + + { + diagnostic_metadata metadata; + metadata.add_cwe (415); + auto element = b.make_element_for_metadata (metadata); + pretty_printer pp; + element->write_as_xml (&pp, 0, true); + ASSERT_STREQ + (pp_formatted_text (&pp), + "\n" + "<span class=\"gcc-metadata\">" + "<span class=\"gcc-metadata-item\">" + "[" + "<a href=\"https://cwe.mitre.org/data/definitions/415.html\">" + "CWE-415" + "</a>" + "]" + "</span>" + "</span>"); + } + + { + diagnostic_metadata metadata; + diagnostic_metadata::precanned_rule rule ("MISC-42", + "http://example.com"); + metadata.add_rule (rule); + auto element = b.make_element_for_metadata (metadata); + pretty_printer pp; + element->write_as_xml (&pp, 0, true); + ASSERT_STREQ + (pp_formatted_text (&pp), + "\n" + "<span class=\"gcc-metadata\">" + "<span class=\"gcc-metadata-item\">" + "[" + "<a href=\"http://example.com\">" + "MISC-42" + "</a>" + "]" + "</span>" + "</span>"); + } +} + /* Run all of the selftests within this file. */ void diagnostic_format_html_cc_tests () { + auto_fix_quotes fix_quotes; test_simple_log (); + test_metadata (); } } // namespace selftest diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ab89686..ee71801 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31145,501 +31145,8 @@ syntax @samp{<major>p<minor>} or @samp{<major>}, (e.g.@: @samp{m2p1} or @end table Supported extension are listed below: -@multitable @columnfractions .10 .10 .80 -@headitem Extension Name @tab Supported Version @tab Description -@item i -@tab 2.0, 2.1 -@tab Base integer extension. - -@item e -@tab 2.0 -@tab Reduced base integer extension. - -@item g -@tab - -@tab General-purpose computing base extension, @samp{g} will expand to -@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and -@samp{zifencei}. - -@item m -@tab 2.0 -@tab Integer multiplication and division extension. - -@item a -@tab 2.0, 2.1 -@tab Atomic extension. - -@item f -@tab 2.0, 2.2 -@tab Single-precision floating-point extension. - -@item d -@tab 2.0, 2.2 -@tab Double-precision floating-point extension. - -@item c -@tab 2.0 -@tab Compressed extension. - -@item h -@tab 1.0 -@tab Hypervisor extension. - -@item v -@tab 1.0 -@tab Vector extension. - -@item zicsr -@tab 2.0 -@tab Control and status register access extension. - -@item zifencei -@tab 2.0 -@tab Instruction-fetch fence extension. - -@item zicond -@tab 1.0 -@tab Integer conditional operations extension. - -@item za64rs -@tab 1.0 -@tab Reservation set size of 64 bytes. - -@item za128rs -@tab 1.0 -@tab Reservation set size of 128 bytes. - -@item zawrs -@tab 1.0 -@tab Wait-on-reservation-set extension. - -@item zba -@tab 1.0 -@tab Address calculation extension. - -@item zbb -@tab 1.0 -@tab Basic bit manipulation extension. - -@item zbc -@tab 1.0 -@tab Carry-less multiplication extension. - -@item zbs -@tab 1.0 -@tab Single-bit operation extension. - -@item zfinx -@tab 1.0 -@tab Single-precision floating-point in integer registers extension. - -@item zdinx -@tab 1.0 -@tab Double-precision floating-point in integer registers extension. - -@item zhinx -@tab 1.0 -@tab Half-precision floating-point in integer registers extension. - -@item zhinxmin -@tab 1.0 -@tab Minimal half-precision floating-point in integer registers extension. - -@item zbkb -@tab 1.0 -@tab Cryptography bit-manipulation extension. - -@item zbkc -@tab 1.0 -@tab Cryptography carry-less multiply extension. - -@item zbkx -@tab 1.0 -@tab Cryptography crossbar permutation extension. - -@item zkne -@tab 1.0 -@tab AES Encryption extension. - -@item zknd -@tab 1.0 -@tab AES Decryption extension. - -@item zknh -@tab 1.0 -@tab Hash function extension. - -@item zkr -@tab 1.0 -@tab Entropy source extension. - -@item zksed -@tab 1.0 -@tab SM4 block cipher extension. - -@item zksh -@tab 1.0 -@tab SM3 hash function extension. - -@item zkt -@tab 1.0 -@tab Data independent execution latency extension. - -@item zk -@tab 1.0 -@tab Standard scalar cryptography extension. - -@item zkn -@tab 1.0 -@tab NIST algorithm suite extension. - -@item zks -@tab 1.0 -@tab ShangMi algorithm suite extension. -@item zihintntl -@tab 1.0 -@tab Non-temporal locality hints extension. - -@item zihintpause -@tab 1.0 -@tab Pause hint extension. - -@item zicboz -@tab 1.0 -@tab Cache-block zero extension. - -@item zicbom -@tab 1.0 -@tab Cache-block management extension. - -@item zicbop -@tab 1.0 -@tab Cache-block prefetch extension. - -@item zic64b -@tab 1.0 -@tab Cache block size isf 64 bytes. - -@item ziccamoa -@tab 1.0 -@tab Main memory supports all atomics in A. - -@item ziccif -@tab 1.0 -@tab Main memory supports instruction fetch with atomicity requirement. - -@item zicclsm -@tab 1.0 -@tab Main memory supports misaligned loads/stores. - -@item ziccrse -@tab 1.0 -@tab Main memory supports forward progress on LR/SC sequences. - -@item zicntr -@tab 2.0 -@tab Standard extension for base counters and timers. - -@item zihpm -@tab 2.0 -@tab Standard extension for hardware performance counters. - -@item ztso -@tab 1.0 -@tab Total store ordering extension. - -@item zve32x -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve32f -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64x -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64f -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zve64d -@tab 1.0 -@tab Vector extensions for embedded processors. - -@item zvl32b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl64b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl128b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl256b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl512b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl1024b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl2048b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvl4096b -@tab 1.0 -@tab Minimum vector length standard extensions - -@item zvbb -@tab 1.0 -@tab Vector basic bit-manipulation extension. - -@item zvbc -@tab 1.0 -@tab Vector carryless multiplication extension. - -@item zvkb -@tab 1.0 -@tab Vector cryptography bit-manipulation extension. - -@item zvkg -@tab 1.0 -@tab Vector GCM/GMAC extension. - -@item zvkned -@tab 1.0 -@tab Vector AES block cipher extension. - -@item zvknha -@tab 1.0 -@tab Vector SHA-2 secure hash extension. - -@item zvknhb -@tab 1.0 -@tab Vector SHA-2 secure hash extension. - -@item zvksed -@tab 1.0 -@tab Vector SM4 Block Cipher extension. - -@item zvksh -@tab 1.0 -@tab Vector SM3 Secure Hash extension. - -@item zvkn -@tab 1.0 -@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to -@samp{zvkned}, @samp{zvknhb}, @samp{zvkb} and @samp{zvkt}. - -@item zvknc -@tab 1.0 -@tab Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc} -will expand to @samp{zvkn} and @samp{zvbc}. - -@item zvkng -@tab 1.0 -@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand -to @samp{zvkn} and @samp{zvkg}. - -@item zvks -@tab 1.0 -@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand -to @samp{zvksed}, @samp{zvksh}, @samp{zvkb} and @samp{zvkt}. - -@item zvksc -@tab 1.0 -@tab Vector ShangMi algorithm suite with carryless multiplication extension, -@samp{zvksc} will expand to @samp{zvks} and @samp{zvbc}. - -@item zvksg -@tab 1.0 -@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand -to @samp{zvks} and @samp{zvkg}. - -@item zvkt -@tab 1.0 -@tab Vector data independent execution latency extension. - -@item zfh -@tab 1.0 -@tab Half-precision floating-point extension. - -@item zfhmin -@tab 1.0 -@tab Minimal half-precision floating-point extension. - -@item zvfh -@tab 1.0 -@tab Vector half-precision floating-point extension. - -@item zvfhmin -@tab 1.0 -@tab Vector minimal half-precision floating-point extension. - -@item zvfbfmin -@tab 1.0 -@tab Vector BF16 converts extension. - -@item zfa -@tab 1.0 -@tab Additional floating-point extension. - -@item zmmul -@tab 1.0 -@tab Integer multiplication extension. - -@item zca -@tab 1.0 -@tab Integer compressed instruction extension. - -@item zcf -@tab 1.0 -@tab Compressed single-precision floating point loads and stores extension. - -@item zcd -@tab 1.0 -@tab Compressed double-precision floating point loads and stores extension. - -@item zcb -@tab 1.0 -@tab Simple compressed instruction extension. - -@item zce -@tab 1.0 -@tab Compressed instruction extensions for embedded processors. - -@item zcmp -@tab 1.0 -@tab Compressed push pop extension. - -@item zcmt -@tab 1.0 -@tab Table jump instruction extension. - -@item smaia -@tab 1.0 -@tab Advanced interrupt architecture extension. - -@item smepmp -@tab 1.0 -@tab PMP Enhancements for memory access and execution prevention on Machine mode. - -@item smstateen -@tab 1.0 -@tab State enable extension. - -@item ssaia -@tab 1.0 -@tab Advanced interrupt architecture extension for supervisor-mode. - -@item sscofpmf -@tab 1.0 -@tab Count overflow & filtering extension. - -@item ssstateen -@tab 1.0 -@tab State-enable extension for supervisor-mode. - -@item sstc -@tab 1.0 -@tab Supervisor-mode timer interrupts extension. - -@item svade -@tab 1.0 -@tab Cause exception when hardware updating of A/D bits is disabled - -@item svadu -@tab 1.0 -@tab Hardware Updating of A/D Bits extension. - -@item svinval -@tab 1.0 -@tab Fine-grained address-translation cache invalidation extension. - -@item svnapot -@tab 1.0 -@tab NAPOT translation contiguity extension. - -@item svpbmt -@tab 1.0 -@tab Page-based memory types extension. - -@item xcvmac -@tab 1.0 -@tab Core-V multiply-accumulate extension. - -@item xcvalu -@tab 1.0 -@tab Core-V miscellaneous ALU extension. - -@item xcvelw -@tab 1.0 -@tab Core-V event load word extension. - -@item xtheadba -@tab 1.0 -@tab T-head address calculation extension. - -@item xtheadbb -@tab 1.0 -@tab T-head basic bit-manipulation extension. - -@item xtheadbs -@tab 1.0 -@tab T-head single-bit instructions extension. - -@item xtheadcmo -@tab 1.0 -@tab T-head cache management operations extension. - -@item xtheadcondmov -@tab 1.0 -@tab T-head conditional move extension. - -@item xtheadfmemidx -@tab 1.0 -@tab T-head indexed memory operations for floating-point registers extension. - -@item xtheadfmv -@tab 1.0 -@tab T-head double floating-point high-bit data transmission extension. - -@item xtheadint -@tab 1.0 -@tab T-head acceleration interruption extension. - -@item xtheadmac -@tab 1.0 -@tab T-head multiply-accumulate extension. - -@item xtheadmemidx -@tab 1.0 -@tab T-head indexed memory operation extension. - -@item xtheadmempair -@tab 1.0 -@tab T-head two-GPR memory operation extension. - -@item xtheadsync -@tab 1.0 -@tab T-head multi-core synchronization extension. - -@item xventanacondops -@tab 1.0 -@tab Ventana integer conditional operations extension. - -@end multitable +@include riscv-ext.texi When @option{-march=} is not specified, use the setting from @option{-mcpu}. diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi new file mode 100644 index 0000000..968654b --- /dev/null +++ b/gcc/doc/riscv-ext.texi @@ -0,0 +1,637 @@ +@c Copyright (C) 2025 Free Software Foundation, Inc. +@c This is part of the GCC manual. +@c For copying conditions, see the file gcc/doc/include/fdl.texi. + +@c This file is generated automatically using +@c gcc/config/riscv/gen-riscv-ext-texi.cc from: +@c gcc/config/riscv/riscv-ext.def +@c gcc/config/riscv/riscv-opts.h + +@c Please *DO NOT* edit manually. + +@multitable @columnfractions .10 .10 .80 +@headitem Extension Name @tab Supported Version @tab Description + +@item g +@tab - +@tab General-purpose computing base extension, @samp{g} will expand to +@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and +@samp{zifencei}. + +@item e +@tab 2.0 +@tab Reduced base integer extension + +@item i +@tab 2.0 2.1 +@tab Base integer extension + +@item m +@tab 2.0 +@tab Integer multiplication and division extension + +@item a +@tab 2.0 2.1 +@tab Atomic extension + +@item f +@tab 2.0 2.2 +@tab Single-precision floating-point extension + +@item d +@tab 2.0 2.2 +@tab Double-precision floating-point extension + +@item c +@tab 2.0 +@tab Compressed extension + +@item b +@tab 1.0 +@tab b extension + +@item v +@tab 1.0 +@tab Vector extension + +@item h +@tab 1.0 +@tab Hypervisor extension + +@item zic64b +@tab 1.0 +@tab Cache block size isf 64 bytes + +@item zicbom +@tab 1.0 +@tab Cache-block management extension + +@item zicbop +@tab 1.0 +@tab Cache-block prefetch extension + +@item zicboz +@tab 1.0 +@tab Cache-block zero extension + +@item ziccamoa +@tab 1.0 +@tab Main memory supports all atomics in A + +@item ziccif +@tab 1.0 +@tab Main memory supports instruction fetch with atomicity requirement + +@item zicclsm +@tab 1.0 +@tab Main memory supports misaligned loads/stores + +@item ziccrse +@tab 1.0 +@tab Main memory supports forward progress on LR/SC sequences + +@item zicfilp +@tab 1.0 +@tab zicfilp extension + +@item zicfiss +@tab 1.0 +@tab zicfiss extension + +@item zicntr +@tab 2.0 +@tab Standard extension for base counters and timers + +@item zicond +@tab 1.0 +@tab Integer conditional operations extension + +@item zicsr +@tab 2.0 +@tab Control and status register access extension + +@item zifencei +@tab 2.0 +@tab Instruction-fetch fence extension + +@item zihintntl +@tab 1.0 +@tab Non-temporal locality hints extension + +@item zihintpause +@tab 2.0 +@tab Pause hint extension + +@item zihpm +@tab 2.0 +@tab Standard extension for hardware performance counters + +@item zimop +@tab 1.0 +@tab zimop extension + +@item zilsd +@tab 1.0 +@tab Load/Store pair instructions extension + +@item zmmul +@tab 1.0 +@tab Integer multiplication extension + +@item za128rs +@tab 1.0 +@tab Reservation set size of 128 bytes + +@item za64rs +@tab 1.0 +@tab Reservation set size of 64 bytes + +@item zaamo +@tab 1.0 +@tab zaamo extension + +@item zabha +@tab 1.0 +@tab zabha extension + +@item zacas +@tab 1.0 +@tab zacas extension + +@item zalrsc +@tab 1.0 +@tab zalrsc extension + +@item zawrs +@tab 1.0 +@tab Wait-on-reservation-set extension + +@item zama16b +@tab 1.0 +@tab Zama16b extension, Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic. + +@item zfa +@tab 1.0 +@tab Additional floating-point extension + +@item zfbfmin +@tab 1.0 +@tab zfbfmin extension + +@item zfh +@tab 1.0 +@tab Half-precision floating-point extension + +@item zfhmin +@tab 1.0 +@tab Minimal half-precision floating-point extension + +@item zfinx +@tab 1.0 +@tab Single-precision floating-point in integer registers extension + +@item zdinx +@tab 1.0 +@tab Double-precision floating-point in integer registers extension + +@item zca +@tab 1.0 +@tab Integer compressed instruction extension + +@item zcb +@tab 1.0 +@tab Simple compressed instruction extension + +@item zcd +@tab 1.0 +@tab Compressed double-precision floating point loads and stores extension + +@item zce +@tab 1.0 +@tab Compressed instruction extensions for embedded processors + +@item zcf +@tab 1.0 +@tab Compressed single-precision floating point loads and stores extension + +@item zcmop +@tab 1.0 +@tab zcmop extension + +@item zcmp +@tab 1.0 +@tab Compressed push pop extension + +@item zcmt +@tab 1.0 +@tab Table jump instruction extension + +@item zclsd +@tab 1.0 +@tab Compressed load/store pair instructions extension + +@item zba +@tab 1.0 +@tab Address calculation extension + +@item zbb +@tab 1.0 +@tab Basic bit manipulation extension + +@item zbc +@tab 1.0 +@tab Carry-less multiplication extension + +@item zbkb +@tab 1.0 +@tab Cryptography bit-manipulation extension + +@item zbkc +@tab 1.0 +@tab Cryptography carry-less multiply extension + +@item zbkx +@tab 1.0 +@tab Cryptography crossbar permutation extension + +@item zbs +@tab 1.0 +@tab Single-bit operation extension + +@item zk +@tab 1.0 +@tab Standard scalar cryptography extension + +@item zkn +@tab 1.0 +@tab NIST algorithm suite extension + +@item zknd +@tab 1.0 +@tab AES Decryption extension + +@item zkne +@tab 1.0 +@tab AES Encryption extension + +@item zknh +@tab 1.0 +@tab Hash function extension + +@item zkr +@tab 1.0 +@tab Entropy source extension + +@item zks +@tab 1.0 +@tab ShangMi algorithm suite extension + +@item zksed +@tab 1.0 +@tab SM4 block cipher extension + +@item zksh +@tab 1.0 +@tab SM3 hash function extension + +@item zkt +@tab 1.0 +@tab Data independent execution latency extension + +@item ztso +@tab 1.0 +@tab Total store ordering extension + +@item zvbb +@tab 1.0 +@tab Vector basic bit-manipulation extension + +@item zvbc +@tab 1.0 +@tab Vector carryless multiplication extension + +@item zve32f +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve32x +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve64d +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve64f +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zve64x +@tab 1.0 +@tab Vector extensions for embedded processors + +@item zvfbfmin +@tab 1.0 +@tab Vector BF16 converts extension + +@item zvfbfwma +@tab 1.0 +@tab zvfbfwma extension + +@item zvfh +@tab 1.0 +@tab Vector half-precision floating-point extension + +@item zvfhmin +@tab 1.0 +@tab Vector minimal half-precision floating-point extension + +@item zvkb +@tab 1.0 +@tab Vector cryptography bit-manipulation extension + +@item zvkg +@tab 1.0 +@tab Vector GCM/GMAC extension + +@item zvkn +@tab 1.0 +@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to + +@item zvknc +@tab 1.0 +@tab Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc} + +@item zvkned +@tab 1.0 +@tab Vector AES block cipher extension + +@item zvkng +@tab 1.0 +@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand + +@item zvknha +@tab 1.0 +@tab Vector SHA-2 secure hash extension + +@item zvknhb +@tab 1.0 +@tab Vector SHA-2 secure hash extension + +@item zvks +@tab 1.0 +@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand + +@item zvksc +@tab 1.0 +@tab Vector ShangMi algorithm suite with carryless multiplication extension, + +@item zvksed +@tab 1.0 +@tab Vector SM4 Block Cipher extension + +@item zvksg +@tab 1.0 +@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand + +@item zvksh +@tab 1.0 +@tab Vector SM3 Secure Hash extension + +@item zvkt +@tab 1.0 +@tab Vector data independent execution latency extension + +@item zvl1024b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl128b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl16384b +@tab 1.0 +@tab zvl16384b extension + +@item zvl2048b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl256b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl32768b +@tab 1.0 +@tab zvl32768b extension + +@item zvl32b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl4096b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl512b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl64b +@tab 1.0 +@tab Minimum vector length standard extensions + +@item zvl65536b +@tab 1.0 +@tab zvl65536b extension + +@item zvl8192b +@tab 1.0 +@tab zvl8192b extension + +@item zhinx +@tab 1.0 +@tab Half-precision floating-point in integer registers extension + +@item zhinxmin +@tab 1.0 +@tab Minimal half-precision floating-point in integer registers extension + +@item sdtrig +@tab 1.0 +@tab sdtrig extension + +@item smaia +@tab 1.0 +@tab Advanced interrupt architecture extension + +@item smepmp +@tab 1.0 +@tab PMP Enhancements for memory access and execution prevention on Machine mode + +@item smmpm +@tab 1.0 +@tab smmpm extension + +@item smnpm +@tab 1.0 +@tab smnpm extension + +@item smstateen +@tab 1.0 +@tab State enable extension + +@item ssaia +@tab 1.0 +@tab Advanced interrupt architecture extension for supervisor-mode + +@item sscofpmf +@tab 1.0 +@tab Count overflow & filtering extension + +@item ssnpm +@tab 1.0 +@tab ssnpm extension + +@item sspm +@tab 1.0 +@tab sspm extension + +@item ssstateen +@tab 1.0 +@tab State-enable extension for supervisor-mode + +@item sstc +@tab 1.0 +@tab Supervisor-mode timer interrupts extension + +@item ssstrict +@tab 1.0 +@tab ssstrict extension + +@item supm +@tab 1.0 +@tab supm extension + +@item svinval +@tab 1.0 +@tab Fine-grained address-translation cache invalidation extension + +@item svnapot +@tab 1.0 +@tab NAPOT translation contiguity extension + +@item svpbmt +@tab 1.0 +@tab Page-based memory types extension + +@item svvptc +@tab 1.0 +@tab svvptc extension + +@item svadu +@tab 1.0 +@tab Hardware Updating of A/D Bits extension + +@item svade +@tab 1.0 +@tab Cause exception when hardware updating of A/D bits is disabled + +@item xcvalu +@tab 1.0 +@tab Core-V miscellaneous ALU extension + +@item xcvbi +@tab 1.0 +@tab xcvbi extension + +@item xcvelw +@tab 1.0 +@tab Core-V event load word extension + +@item xcvmac +@tab 1.0 +@tab Core-V multiply-accumulate extension + +@item xcvsimd +@tab 1.0 +@tab xcvsimd extension + +@item xsfcease +@tab 1.0 +@tab xsfcease extension + +@item xsfvcp +@tab 1.0 +@tab xsfvcp extension + +@item xsfvfnrclipxfqf +@tab 1.0 +@tab xsfvfnrclipxfqf extension + +@item xsfvqmaccdod +@tab 1.0 +@tab xsfvqmaccdod extension + +@item xsfvqmaccqoq +@tab 1.0 +@tab xsfvqmaccqoq extension + +@item xtheadba +@tab 1.0 +@tab T-head address calculation extension + +@item xtheadbb +@tab 1.0 +@tab T-head basic bit-manipulation extension + +@item xtheadbs +@tab 1.0 +@tab T-head single-bit instructions extension + +@item xtheadcmo +@tab 1.0 +@tab T-head cache management operations extension + +@item xtheadcondmov +@tab 1.0 +@tab T-head conditional move extension + +@item xtheadfmemidx +@tab 1.0 +@tab T-head indexed memory operations for floating-point registers extension + +@item xtheadfmv +@tab 1.0 +@tab T-head double floating-point high-bit data transmission extension + +@item xtheadint +@tab 1.0 +@tab T-head acceleration interruption extension + +@item xtheadmac +@tab 1.0 +@tab T-head multiply-accumulate extension + +@item xtheadmemidx +@tab 1.0 +@tab T-head indexed memory operation extension + +@item xtheadmempair +@tab 1.0 +@tab T-head two-GPR memory operation extension + +@item xtheadsync +@tab 1.0 +@tab T-head multi-core synchronization extension + +@item xtheadvector +@tab 1.0 +@tab xtheadvector extension + +@item xventanacondops +@tab 1.0 +@tab Ventana integer conditional operations extension + +@end multitable diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc index 440cbdd..fce5ee2 100644 --- a/gcc/fortran/trans-intrinsic.cc +++ b/gcc/fortran/trans-intrinsic.cc @@ -4715,22 +4715,6 @@ maybe_absent_optional_variable (gfc_expr *e) } -/* Remove unneeded kind= argument from actual argument list when the - result conversion is dealt with in a different place. */ - -static void -strip_kind_from_actual (gfc_actual_arglist * actual) -{ - for (gfc_actual_arglist *a = actual; a; a = a->next) - { - if (a && a->name && strcmp (a->name, "kind") == 0) - { - gfc_free_expr (a->expr); - a->expr = NULL; - } - } -} - /* Emit code for minloc or maxloc intrinsic. There are many different cases we need to handle. For performance reasons we sometimes create two loops instead of one, where the second one is much simpler. @@ -4925,7 +4909,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * expr, enum tree_code op) tree b_if, b_else; tree back; gfc_loopinfo loop, *ploop; - gfc_actual_arglist *actual, *array_arg, *dim_arg, *mask_arg, *kind_arg; + gfc_actual_arglist *array_arg, *dim_arg, *mask_arg, *kind_arg; gfc_actual_arglist *back_arg; gfc_ss *arrayss = nullptr; gfc_ss *maskss = nullptr; @@ -4944,8 +4928,7 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * expr, enum tree_code op) int n; bool optional_mask; - actual = expr->value.function.actual; - array_arg = actual; + array_arg = expr->value.function.actual; dim_arg = array_arg->next; mask_arg = dim_arg->next; kind_arg = mask_arg->next; @@ -4954,14 +4937,16 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * expr, enum tree_code op) bool dim_present = dim_arg->expr != nullptr; bool nested_loop = dim_present && expr->rank > 0; - /* The last argument, BACK, is passed by value. Ensure that - by setting its name to %VAL. */ - for (gfc_actual_arglist *a = actual; a; a = a->next) + /* Remove kind. */ + if (kind_arg->expr) { - if (a->next == NULL) - a->name = "%VAL"; + gfc_free_expr (kind_arg->expr); + kind_arg->expr = NULL; } + /* Pass BACK argument by value. */ + back_arg->name = "%VAL"; + if (se->ss) { if (se->ss->info->useflags) @@ -4983,25 +4968,19 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * expr, enum tree_code op) } } - arrayexpr = actual->expr; + arrayexpr = array_arg->expr; - /* Special case for character maxloc. Remove unneeded actual - arguments, then call a library function. */ + /* Special case for character maxloc. Remove unneeded "dim" actual + argument, then call a library function. */ if (arrayexpr->ts.type == BT_CHARACTER) { gcc_assert (expr->rank == 0); - gfc_actual_arglist *a = actual; - strip_kind_from_actual (a); - while (a) + if (dim_arg->expr) { - if (a->name && strcmp (a->name, "dim") == 0) - { - gfc_free_expr (a->expr); - a->expr = NULL; - } - a = a->next; + gfc_free_expr (dim_arg->expr); + dim_arg->expr = NULL; } gfc_conv_intrinsic_funcall (se, expr); return; diff --git a/gcc/gimple-fold.cc b/gcc/gimple-fold.cc index e63fd6f..b8c1588 100644 --- a/gcc/gimple-fold.cc +++ b/gcc/gimple-fold.cc @@ -6276,6 +6276,32 @@ replace_stmt_with_simplification (gimple_stmt_iterator *gsi, } else if (!inplace) { + /* For throwing comparisons, see if the GIMPLE_COND is the same as + the comparison would be. + This can happen due to the match pattern for + `(ne (cmp @0 @1) integer_zerop)` which creates a new expression + for the comparison. */ + if (TREE_CODE_CLASS (code) == tcc_comparison + && flag_exceptions + && cfun->can_throw_non_call_exceptions + && operation_could_trap_p (code, + FLOAT_TYPE_P (TREE_TYPE (ops[0])), + false, NULL_TREE)) + { + tree lhs = gimple_cond_lhs (cond_stmt); + if (gimple_cond_code (cond_stmt) == NE_EXPR + && TREE_CODE (lhs) == SSA_NAME + && INTEGRAL_TYPE_P (TREE_TYPE (lhs)) + && integer_zerop (gimple_cond_rhs (cond_stmt))) + { + gimple *s = SSA_NAME_DEF_STMT (lhs); + if (is_gimple_assign (s) + && gimple_assign_rhs_code (s) == code + && operand_equal_p (gimple_assign_rhs1 (s), ops[0]) + && operand_equal_p (gimple_assign_rhs2 (s), ops[1])) + return false; + } + } tree res = maybe_push_res_to_seq (res_op, seq); if (!res) return false; diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index a9ed995..cfc235c 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2025-05-12 Joseph Myers <josmyers@redhat.com> + + * sv.po: Update. + 2025-04-30 Joseph Myers <josmyers@redhat.com> * be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b9e39f2..b7e62e8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,106 @@ +2025-05-13 Andrew MacLeod <amacleod@redhat.com> + + * gcc.dg/tree-ssa/vrp124.c: New. + +2025-05-12 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add test helper macros. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c: New test. + * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c: New test. + +2025-05-12 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/sat/sat_arith.h: Add test helper macros. + * gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c: New test. + +2025-05-12 Jason Merrill <jason@redhat.com> + + PR c++/120012 + * g++.dg/abi/base-defaulted2.C: New test. + +2025-05-12 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/120188 + * lib/gm2-dg.exp (gm2-dg-frontend-configure-check): New function. + (gm2-dg-runtest): Add -O2 to the option_list. + * gm2.dg/doc/examples/plugin/fail/assignvalue.mod: New test. + * gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp: New test. + +2025-05-12 Thomas Schwinge <tschwinge@baylibre.com> + + * gcc.target/nvptx/march-map=sm_61.c: Adjust. + * gcc.target/nvptx/march-map=sm_62.c: Likewise. + * gcc.target/nvptx/march=sm_61.c: New. + +2025-05-12 Thomas Schwinge <tschwinge@baylibre.com> + + * gcc.target/nvptx/mptx=5.0.c: New. + +2025-05-12 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/116445 + * gcc.target/arm/unsigned-extend-2.c: Fix dg directives. + +2025-05-12 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * gcc.target/riscv/arch-ss-1.c: New test. + * gcc.target/riscv/arch-ss-2.c: New test. + +2025-05-12 Dongyan Chen <chendongyan@isrc.iscas.ac.cn> + + * gcc.target/riscv/arch-zilsd-1.c: New. + * gcc.target/riscv/arch-zilsd-2.c: New. + * gcc.target/riscv/arch-zilsd-3.c: New. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/ivopts.c: Remove test for iwmmxt + * lib/target-supports.exp + (check_effective_target_arm_iwmmxt_ok): Delete. + +2025-05-12 Richard Earnshaw <rearnsha@arm.com> + + * gcc.target/arm/mmx-1.c: Removed. + * gcc.target/arm/mmx-2.c: Removed. + * gcc.target/arm/pr64208.c: Removed. + * gcc.target/arm/pr79145.c: Removed. + * gcc.target/arm/pr99724.c: Removed. + * gcc.target/arm/pr99786.c: Removed. + +2025-05-12 Richard Biener <rguenther@suse.de> + + PR testsuite/120222 + * gcc.dg/tree-ssa/gen-vect-28.c: Use noipa on main_1. + +2025-05-12 Jiawei <jiawei@iscas.ac.cn> + + * gcc.target/riscv/arch-52.c: Fix regular expression. + +2025-05-12 Chao-ying Fu <cfu@wavecomp.com> + + * gcc.target/mips/pr54240.c: Scan phiopt2. + 2025-05-11 Jan Hubicka <hubicka@ucw.cz> * gcc.target/i386/pr91446.c: xfail. diff --git a/gcc/testsuite/c-c++-common/pr118868-1.c b/gcc/testsuite/c-c++-common/pr118868-1.c new file mode 100644 index 0000000..d0a9e77f7 --- /dev/null +++ b/gcc/testsuite/c-c++-common/pr118868-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ + +/* PR middle-end/118868 */ + +/* __builtin_assoc_barrier should work on pointers without any ICE */ +void *f(void *a) +{ + return __builtin_assoc_barrier(a); +} diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr119903-1.C b/gcc/testsuite/g++.dg/tree-ssa/pr119903-1.C new file mode 100644 index 0000000..605f989 --- /dev/null +++ b/gcc/testsuite/g++.dg/tree-ssa/pr119903-1.C @@ -0,0 +1,24 @@ +// { dg-do compile { target c++11 } } +// { dg-options "-O2 -fnon-call-exceptions -ftrapping-math -fdump-tree-optimized-eh" } + +// PR tree-optimization/119903 +// match and simplify would cause the internal throwable fp comparison +// to become only external throwable and lose the landing pad. + +int f() noexcept; +int g() noexcept; + +int m(double a) +{ + try { + if (a < 1.0) + return f(); + return g(); + }catch(...) + { + return -1; + } +} + +// Make sure There is a landing pad for the non-call exception from the comparison. +// { dg-final { scan-tree-dump "LP " "optimized" } } diff --git a/gcc/testsuite/gcc.dg/html-output/missing-semicolon.py b/gcc/testsuite/gcc.dg/html-output/missing-semicolon.py index 8687168..8ac1f14 100644 --- a/gcc/testsuite/gcc.dg/html-output/missing-semicolon.py +++ b/gcc/testsuite/gcc.dg/html-output/missing-semicolon.py @@ -60,7 +60,8 @@ def test_basics(html_tree): pre = diag.find('xhtml:pre', ns) assert pre is not None - assert pre.attrib['class'] == 'gcc-annotated-source' + assert pre.attrib['class'] == 'gcc-generated-patch' + assert pre.text.startswith('--- ') # For reference, here's the generated HTML: """ @@ -76,7 +77,9 @@ def test_basics(html_tree): <div class="gcc-diagnostic-list"> <div class="gcc-diagnostic"> <span class="gcc-message">expected '<span class="gcc-quoted-text">;</span>' before '<span class="gcc-quoted-text">}</span>' token</span> - <pre class="gcc-annotated-source"></pre> + <pre class="gcc-generated-patch"> + [...snip...] + </pre> </div> </div> </body> diff --git a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.c b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.c new file mode 100644 index 0000000..2499e8d --- /dev/null +++ b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-fdiagnostics-set-output=experimental-html" } */ +/* { dg-additional-options "-fdiagnostics-show-caret" } */ + +extern char *gets (char *s); + +void test_cwe (void) +{ + char buf[1024]; + gets (buf); +} + +/* Use a Python script to verify various properties about the generated + HTML file: + { dg-final { run-html-pytest diagnostic-test-metadata-html.c "diagnostic-test-metadata-html.py" } } */ diff --git a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.py b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.py new file mode 100644 index 0000000..e475e95 --- /dev/null +++ b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-metadata-html.py @@ -0,0 +1,68 @@ +# Verify that metadata works in HTML output. + +from htmltest import * + +import pytest + +@pytest.fixture(scope='function', autouse=True) +def html_tree(): + return html_tree_from_env() + +XHTML = 'http://www.w3.org/1999/xhtml' +ns = {'xhtml': XHTML} + +def make_tag(local_name): + return f'{{{XHTML}}}' + local_name + +def test_metadata(html_tree): + root = html_tree.getroot () + assert root.tag == make_tag('html') + + body = root.find('xhtml:body', ns) + assert body is not None + + diag_list = body.find('xhtml:div', ns) + assert diag_list is not None + assert diag_list.attrib['class'] == 'gcc-diagnostic-list' + + diag = diag_list.find('xhtml:div', ns) + assert diag is not None + assert diag.attrib['class'] == 'gcc-diagnostic' + + spans = diag.findall('xhtml:span', ns) + metadata = spans[1] + assert metadata.attrib['class'] == 'gcc-metadata' + assert metadata[0].tag == make_tag('span') + assert metadata[0].attrib['class'] == 'gcc-metadata-item' + assert metadata[0].text == '[' + assert metadata[0][0].tag == make_tag('a') + assert metadata[0][0].attrib['href'] == 'https://cwe.mitre.org/data/definitions/242.html' + assert metadata[0][0].text == 'CWE-242' + assert metadata[0][0].tail == ']' + + assert metadata[1].tag == make_tag('span') + assert metadata[1].attrib['class'] == 'gcc-metadata-item' + assert metadata[1].text == '[' + assert metadata[1][0].tag == make_tag('a') + assert metadata[1][0].attrib['href'] == 'https://example.com/' + assert metadata[1][0].text == 'STR34-C' + assert metadata[1][0].tail == ']' + + src = diag.find('xhtml:pre', ns) + assert src.attrib['class'] == 'gcc-annotated-source' + assert src.text == ( + ' gets (buf);\n' + ' ^~~~~~~~~~\n') + +# For reference, here's the generated HTML: +""" + <body> + <div class="gcc-diagnostic-list"> + <div class="gcc-diagnostic"> + <span class="gcc-message">never use '<span class="gcc-quoted-text">gets</span>'</span> + <span class="gcc-metadata"><span class="gcc-metadata-item">[<a href="https://cwe.mitre.org/data/definitions/242.html">CWE-242</a>]</span><span class="gcc-metadata-item">[<a href="https://example.com/">STR34-C</a>]</span></span> + ...etc... + </div> + </div> + </body> +""" diff --git a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.c b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.c index b8134ae..26605f7 100644 --- a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.c +++ b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-fdiagnostics-show-caret -fdiagnostics-show-line-numbers -fdiagnostics-path-format=inline-events" } */ +/* { dg-options "-fdiagnostics-show-caret -fdiagnostics-show-line-numbers -fdiagnostics-path-format=inline-events -fdiagnostics-add-output=experimental-html" } */ #include <stddef.h> #include <stdlib.h> @@ -52,3 +52,7 @@ make_a_list_of_random_ints_badly(PyObject *self, | (3) when calling 'PyList_Append', passing NULL from (1) as argument 1 { dg-end-multiline-output "" } */ } + +/* Use a Python script to verify various properties about the generated + HTML file: + { dg-final { run-html-pytest diagnostic-test-paths-2.c "diagnostic-test-paths-2.py" } } */ diff --git a/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.py b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.py new file mode 100644 index 0000000..c212e49 --- /dev/null +++ b/gcc/testsuite/gcc.dg/plugin/diagnostic-test-paths-2.py @@ -0,0 +1,35 @@ +# Verify that execution paths work in HTML output. + +from htmltest import * + +import pytest + +@pytest.fixture(scope='function', autouse=True) +def html_tree(): + return html_tree_from_env() + +XHTML = 'http://www.w3.org/1999/xhtml' +ns = {'xhtml': XHTML} + +def make_tag(local_name): + return f'{{{XHTML}}}' + local_name + +def test_paths(html_tree): + root = html_tree.getroot () + assert root.tag == make_tag('html') + + body = root.find('xhtml:body', ns) + assert body is not None + + diag_list = body.find('xhtml:div', ns) + assert diag_list is not None + assert diag_list.attrib['class'] == 'gcc-diagnostic-list' + + diag = diag_list.find('xhtml:div', ns) + assert diag is not None + assert diag.attrib['class'] == 'gcc-diagnostic' + + pre = diag.findall('xhtml:pre', ns) + assert pre[0].attrib['class'] == 'gcc-annotated-source' + assert pre[1].attrib['class'] == 'gcc-execution-path' + assert pre[1].text.startswith(" 'make_a_list_of_random_ints_badly': events 1-3") diff --git a/gcc/testsuite/gcc.dg/plugin/plugin.exp b/gcc/testsuite/gcc.dg/plugin/plugin.exp index a84fbae..a066b67 100644 --- a/gcc/testsuite/gcc.dg/plugin/plugin.exp +++ b/gcc/testsuite/gcc.dg/plugin/plugin.exp @@ -105,6 +105,7 @@ set plugin_test_list [list \ diagnostic-test-inlining-4.c } \ { diagnostic_plugin_test_metadata.cc diagnostic-test-metadata.c \ + diagnostic-test-metadata-html.c \ diagnostic-test-metadata-sarif.c } \ { diagnostic_plugin_test_nesting.cc \ diagnostic-test-nesting-text-plain.c \ diff --git a/gcc/testsuite/gfortran.dg/pr120191_1.f90 b/gcc/testsuite/gfortran.dg/pr120191_1.f90 new file mode 100644 index 0000000..13a787d --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr120191_1.f90 @@ -0,0 +1,614 @@ +! PR fortran/120191 +! { dg-do run } + + integer(kind=1) :: a1(10, 10, 10), b1(10) + integer(kind=2) :: a2(10, 10, 10), b2(10) + integer(kind=4) :: a4(10, 10, 10), b4(10) + integer(kind=8) :: a8(10, 10, 10), b8(10) + real(kind=4) :: r4(10, 10, 10), s4(10) + real(kind=8) :: r8(10, 10, 10), s8(10) + logical :: l1(10, 10, 10), l2(10), l3 + l1 = .true. + l2 = .true. + l3 = .true. + a1 = 0 + if (any (maxloc (a1) .ne. 1)) stop 1 + if (any (maxloc (a1, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (a1, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (a1, kind=2) .ne. 1)) stop 4 + if (any (maxloc (a1, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (a1, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (maxloc (a1, 1) .ne. 1)) stop 7 + if (any (maxloc (a1, 1, back=.false.) .ne. 1)) stop 8 + if (any (maxloc (a1, 1, back=.true.) .ne. 10)) stop 9 + if (any (maxloc (a1, 1, kind=1) .ne. 1)) stop 10 + if (any (maxloc (a1, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (maxloc (a1, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (maxloc (a1, 1, l1) .ne. 1)) stop 13 + if (any (maxloc (a1, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (maxloc (a1, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (maxloc (a1, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (maxloc (a1, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (maxloc (a1, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (maxloc (a1, 1, l3) .ne. 1)) stop 19 + if (any (maxloc (a1, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (maxloc (a1, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (maxloc (a1, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (maxloc (a1, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (maxloc (a1, 1, l3, 2, .true.) .ne. 10)) stop 24 + b1 = 0 + if (any (maxloc (b1) .ne. 1)) stop 1 + if (any (maxloc (b1, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (b1, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (b1, kind=2) .ne. 1)) stop 4 + if (any (maxloc (b1, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (b1, kind=8, back=.true.) .ne. 10)) stop 6 + if (maxloc (b1, 1) .ne. 1) stop 7 + if (maxloc (b1, 1, back=.false.) .ne. 1) stop 8 + if (maxloc (b1, 1, back=.true.) .ne. 10) stop 9 + if (maxloc (b1, 1, kind=1) .ne. 1) stop 10 + if (maxloc (b1, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (maxloc (b1, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (maxloc (b1, 1, l2) .ne. 1) stop 13 + if (maxloc (b1, 1, l2, back=.false.) .ne. 1) stop 14 + if (maxloc (b1, 1, l2, back=.true.) .ne. 10) stop 15 + if (maxloc (b1, 1, l2, kind=8) .ne. 1) stop 16 + if (maxloc (b1, 1, l2, 4, .false.) .ne. 1) stop 17 + if (maxloc (b1, 1, l2, 2, .true.) .ne. 10) stop 18 + if (maxloc (b1, 1, l3) .ne. 1) stop 19 + if (maxloc (b1, 1, l3, back=.false.) .ne. 1) stop 20 + if (maxloc (b1, 1, l3, back=.true.) .ne. 10) stop 21 + if (maxloc (b1, 1, l3, kind=8) .ne. 1) stop 22 + if (maxloc (b1, 1, l3, 4, .false.) .ne. 1) stop 23 + if (maxloc (b1, 1, l3, 2, .true.) .ne. 10) stop 24 + a2 = 0 + if (any (maxloc (a2) .ne. 1)) stop 1 + if (any (maxloc (a2, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (a2, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (a2, kind=2) .ne. 1)) stop 4 + if (any (maxloc (a2, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (a2, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (maxloc (a2, 1) .ne. 1)) stop 7 + if (any (maxloc (a2, 1, back=.false.) .ne. 1)) stop 8 + if (any (maxloc (a2, 1, back=.true.) .ne. 10)) stop 9 + if (any (maxloc (a2, 1, kind=1) .ne. 1)) stop 10 + if (any (maxloc (a2, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (maxloc (a2, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (maxloc (a2, 1, l1) .ne. 1)) stop 13 + if (any (maxloc (a2, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (maxloc (a2, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (maxloc (a2, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (maxloc (a2, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (maxloc (a2, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (maxloc (a2, 1, l3) .ne. 1)) stop 19 + if (any (maxloc (a2, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (maxloc (a2, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (maxloc (a2, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (maxloc (a2, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (maxloc (a2, 1, l3, 2, .true.) .ne. 10)) stop 24 + b2 = 0 + if (any (maxloc (b2) .ne. 1)) stop 1 + if (any (maxloc (b2, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (b2, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (b2, kind=2) .ne. 1)) stop 4 + if (any (maxloc (b2, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (b2, kind=8, back=.true.) .ne. 10)) stop 6 + if (maxloc (b2, 1) .ne. 1) stop 7 + if (maxloc (b2, 1, back=.false.) .ne. 1) stop 8 + if (maxloc (b2, 1, back=.true.) .ne. 10) stop 9 + if (maxloc (b2, 1, kind=1) .ne. 1) stop 10 + if (maxloc (b2, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (maxloc (b2, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (maxloc (b2, 1, l2) .ne. 1) stop 13 + if (maxloc (b2, 1, l2, back=.false.) .ne. 1) stop 14 + if (maxloc (b2, 1, l2, back=.true.) .ne. 10) stop 15 + if (maxloc (b2, 1, l2, kind=8) .ne. 1) stop 16 + if (maxloc (b2, 1, l2, 4, .false.) .ne. 1) stop 17 + if (maxloc (b2, 1, l2, 2, .true.) .ne. 10) stop 18 + if (maxloc (b2, 1, l3) .ne. 1) stop 19 + if (maxloc (b2, 1, l3, back=.false.) .ne. 1) stop 20 + if (maxloc (b2, 1, l3, back=.true.) .ne. 10) stop 21 + if (maxloc (b2, 1, l3, kind=8) .ne. 1) stop 22 + if (maxloc (b2, 1, l3, 4, .false.) .ne. 1) stop 23 + if (maxloc (b2, 1, l3, 2, .true.) .ne. 10) stop 24 + a4 = 0 + if (any (maxloc (a4) .ne. 1)) stop 1 + if (any (maxloc (a4, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (a4, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (a4, kind=2) .ne. 1)) stop 4 + if (any (maxloc (a4, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (a4, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (maxloc (a4, 1) .ne. 1)) stop 7 + if (any (maxloc (a4, 1, back=.false.) .ne. 1)) stop 8 + if (any (maxloc (a4, 1, back=.true.) .ne. 10)) stop 9 + if (any (maxloc (a4, 1, kind=1) .ne. 1)) stop 10 + if (any (maxloc (a4, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (maxloc (a4, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (maxloc (a4, 1, l1) .ne. 1)) stop 13 + if (any (maxloc (a4, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (maxloc (a4, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (maxloc (a4, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (maxloc (a4, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (maxloc (a4, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (maxloc (a4, 1, l3) .ne. 1)) stop 19 + if (any (maxloc (a4, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (maxloc (a4, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (maxloc (a4, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (maxloc (a4, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (maxloc (a4, 1, l3, 2, .true.) .ne. 10)) stop 24 + b4 = 0 + if (any (maxloc (b4) .ne. 1)) stop 1 + if (any (maxloc (b4, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (b4, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (b4, kind=2) .ne. 1)) stop 4 + if (any (maxloc (b4, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (b4, kind=8, back=.true.) .ne. 10)) stop 6 + if (maxloc (b4, 1) .ne. 1) stop 7 + if (maxloc (b4, 1, back=.false.) .ne. 1) stop 8 + if (maxloc (b4, 1, back=.true.) .ne. 10) stop 9 + if (maxloc (b4, 1, kind=1) .ne. 1) stop 10 + if (maxloc (b4, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (maxloc (b4, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (maxloc (b4, 1, l2) .ne. 1) stop 13 + if (maxloc (b4, 1, l2, back=.false.) .ne. 1) stop 14 + if (maxloc (b4, 1, l2, back=.true.) .ne. 10) stop 15 + if (maxloc (b4, 1, l2, kind=8) .ne. 1) stop 16 + if (maxloc (b4, 1, l2, 4, .false.) .ne. 1) stop 17 + if (maxloc (b4, 1, l2, 2, .true.) .ne. 10) stop 18 + if (maxloc (b4, 1, l3) .ne. 1) stop 19 + if (maxloc (b4, 1, l3, back=.false.) .ne. 1) stop 20 + if (maxloc (b4, 1, l3, back=.true.) .ne. 10) stop 21 + if (maxloc (b4, 1, l3, kind=8) .ne. 1) stop 22 + if (maxloc (b4, 1, l3, 4, .false.) .ne. 1) stop 23 + if (maxloc (b4, 1, l3, 2, .true.) .ne. 10) stop 24 + a8 = 0 + if (any (maxloc (a8) .ne. 1)) stop 1 + if (any (maxloc (a8, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (a8, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (a8, kind=2) .ne. 1)) stop 4 + if (any (maxloc (a8, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (a8, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (maxloc (a8, 1) .ne. 1)) stop 7 + if (any (maxloc (a8, 1, back=.false.) .ne. 1)) stop 8 + if (any (maxloc (a8, 1, back=.true.) .ne. 10)) stop 9 + if (any (maxloc (a8, 1, kind=1) .ne. 1)) stop 10 + if (any (maxloc (a8, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (maxloc (a8, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (maxloc (a8, 1, l1) .ne. 1)) stop 13 + if (any (maxloc (a8, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (maxloc (a8, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (maxloc (a8, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (maxloc (a8, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (maxloc (a8, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (maxloc (a8, 1, l3) .ne. 1)) stop 19 + if (any (maxloc (a8, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (maxloc (a8, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (maxloc (a8, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (maxloc (a8, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (maxloc (a8, 1, l3, 2, .true.) .ne. 10)) stop 24 + b8 = 0 + if (any (maxloc (b8) .ne. 1)) stop 1 + if (any (maxloc (b8, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (b8, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (b8, kind=2) .ne. 1)) stop 4 + if (any (maxloc (b8, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (b8, kind=8, back=.true.) .ne. 10)) stop 6 + if (maxloc (b8, 1) .ne. 1) stop 7 + if (maxloc (b8, 1, back=.false.) .ne. 1) stop 8 + if (maxloc (b8, 1, back=.true.) .ne. 10) stop 9 + if (maxloc (b8, 1, kind=1) .ne. 1) stop 10 + if (maxloc (b8, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (maxloc (b8, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (maxloc (b8, 1, l2) .ne. 1) stop 13 + if (maxloc (b8, 1, l2, back=.false.) .ne. 1) stop 14 + if (maxloc (b8, 1, l2, back=.true.) .ne. 10) stop 15 + if (maxloc (b8, 1, l2, kind=8) .ne. 1) stop 16 + if (maxloc (b8, 1, l2, 4, .false.) .ne. 1) stop 17 + if (maxloc (b8, 1, l2, 2, .true.) .ne. 10) stop 18 + if (maxloc (b8, 1, l3) .ne. 1) stop 19 + if (maxloc (b8, 1, l3, back=.false.) .ne. 1) stop 20 + if (maxloc (b8, 1, l3, back=.true.) .ne. 10) stop 21 + if (maxloc (b8, 1, l3, kind=8) .ne. 1) stop 22 + if (maxloc (b8, 1, l3, 4, .false.) .ne. 1) stop 23 + if (maxloc (b8, 1, l3, 2, .true.) .ne. 10) stop 24 + r4 = 0.0 + if (any (maxloc (r4) .ne. 1)) stop 1 + if (any (maxloc (r4, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (r4, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (r4, kind=2) .ne. 1)) stop 4 + if (any (maxloc (r4, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (r4, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (maxloc (r4, 1) .ne. 1)) stop 7 + if (any (maxloc (r4, 1, back=.false.) .ne. 1)) stop 8 + if (any (maxloc (r4, 1, back=.true.) .ne. 10)) stop 9 + if (any (maxloc (r4, 1, kind=1) .ne. 1)) stop 10 + if (any (maxloc (r4, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (maxloc (r4, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (maxloc (r4, 1, l1) .ne. 1)) stop 13 + if (any (maxloc (r4, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (maxloc (r4, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (maxloc (r4, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (maxloc (r4, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (maxloc (r4, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (maxloc (r4, 1, l3) .ne. 1)) stop 19 + if (any (maxloc (r4, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (maxloc (r4, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (maxloc (r4, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (maxloc (r4, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (maxloc (r4, 1, l3, 2, .true.) .ne. 10)) stop 24 + s4 = 0.0 + if (any (maxloc (s4) .ne. 1)) stop 1 + if (any (maxloc (s4, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (s4, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (s4, kind=2) .ne. 1)) stop 4 + if (any (maxloc (s4, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (s4, kind=8, back=.true.) .ne. 10)) stop 6 + if (maxloc (s4, 1) .ne. 1) stop 7 + if (maxloc (s4, 1, back=.false.) .ne. 1) stop 8 + if (maxloc (s4, 1, back=.true.) .ne. 10) stop 9 + if (maxloc (s4, 1, kind=1) .ne. 1) stop 10 + if (maxloc (s4, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (maxloc (s4, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (maxloc (s4, 1, l2) .ne. 1) stop 13 + if (maxloc (s4, 1, l2, back=.false.) .ne. 1) stop 14 + if (maxloc (s4, 1, l2, back=.true.) .ne. 10) stop 15 + if (maxloc (s4, 1, l2, kind=8) .ne. 1) stop 16 + if (maxloc (s4, 1, l2, 4, .false.) .ne. 1) stop 17 + if (maxloc (s4, 1, l2, 2, .true.) .ne. 10) stop 18 + if (maxloc (s4, 1, l3) .ne. 1) stop 19 + if (maxloc (s4, 1, l3, back=.false.) .ne. 1) stop 20 + if (maxloc (s4, 1, l3, back=.true.) .ne. 10) stop 21 + if (maxloc (s4, 1, l3, kind=8) .ne. 1) stop 22 + if (maxloc (s4, 1, l3, 4, .false.) .ne. 1) stop 23 + if (maxloc (s4, 1, l3, 2, .true.) .ne. 10) stop 24 + r8 = 0.0 + if (any (maxloc (r8) .ne. 1)) stop 1 + if (any (maxloc (r8, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (r8, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (r8, kind=2) .ne. 1)) stop 4 + if (any (maxloc (r8, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (r8, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (maxloc (r8, 1) .ne. 1)) stop 7 + if (any (maxloc (r8, 1, back=.false.) .ne. 1)) stop 8 + if (any (maxloc (r8, 1, back=.true.) .ne. 10)) stop 9 + if (any (maxloc (r8, 1, kind=1) .ne. 1)) stop 10 + if (any (maxloc (r8, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (maxloc (r8, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (maxloc (r8, 1, l1) .ne. 1)) stop 13 + if (any (maxloc (r8, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (maxloc (r8, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (maxloc (r8, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (maxloc (r8, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (maxloc (r8, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (maxloc (r8, 1, l3) .ne. 1)) stop 19 + if (any (maxloc (r8, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (maxloc (r8, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (maxloc (r8, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (maxloc (r8, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (maxloc (r8, 1, l3, 2, .true.) .ne. 10)) stop 24 + s8 = 0.0 + if (any (maxloc (s8) .ne. 1)) stop 1 + if (any (maxloc (s8, back=.false.) .ne. 1)) stop 2 + if (any (maxloc (s8, back=.true.) .ne. 10)) stop 3 + if (any (maxloc (s8, kind=2) .ne. 1)) stop 4 + if (any (maxloc (s8, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (maxloc (s8, kind=8, back=.true.) .ne. 10)) stop 6 + if (maxloc (s8, 1) .ne. 1) stop 7 + if (maxloc (s8, 1, back=.false.) .ne. 1) stop 8 + if (maxloc (s8, 1, back=.true.) .ne. 10) stop 9 + if (maxloc (s8, 1, kind=1) .ne. 1) stop 10 + if (maxloc (s8, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (maxloc (s8, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (maxloc (s8, 1, l2) .ne. 1) stop 13 + if (maxloc (s8, 1, l2, back=.false.) .ne. 1) stop 14 + if (maxloc (s8, 1, l2, back=.true.) .ne. 10) stop 15 + if (maxloc (s8, 1, l2, kind=8) .ne. 1) stop 16 + if (maxloc (s8, 1, l2, 4, .false.) .ne. 1) stop 17 + if (maxloc (s8, 1, l2, 2, .true.) .ne. 10) stop 18 + if (maxloc (s8, 1, l3) .ne. 1) stop 19 + if (maxloc (s8, 1, l3, back=.false.) .ne. 1) stop 20 + if (maxloc (s8, 1, l3, back=.true.) .ne. 10) stop 21 + if (maxloc (s8, 1, l3, kind=8) .ne. 1) stop 22 + if (maxloc (s8, 1, l3, 4, .false.) .ne. 1) stop 23 + if (maxloc (s8, 1, l3, 2, .true.) .ne. 10) stop 24 + a1 = 0 + if (any (minloc (a1) .ne. 1)) stop 1 + if (any (minloc (a1, back=.false.) .ne. 1)) stop 2 + if (any (minloc (a1, back=.true.) .ne. 10)) stop 3 + if (any (minloc (a1, kind=2) .ne. 1)) stop 4 + if (any (minloc (a1, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (a1, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (minloc (a1, 1) .ne. 1)) stop 7 + if (any (minloc (a1, 1, back=.false.) .ne. 1)) stop 8 + if (any (minloc (a1, 1, back=.true.) .ne. 10)) stop 9 + if (any (minloc (a1, 1, kind=1) .ne. 1)) stop 10 + if (any (minloc (a1, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (minloc (a1, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (minloc (a1, 1, l1) .ne. 1)) stop 13 + if (any (minloc (a1, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (minloc (a1, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (minloc (a1, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (minloc (a1, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (minloc (a1, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (minloc (a1, 1, l3) .ne. 1)) stop 19 + if (any (minloc (a1, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (minloc (a1, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (minloc (a1, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (minloc (a1, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (minloc (a1, 1, l3, 2, .true.) .ne. 10)) stop 24 + b1 = 0 + if (any (minloc (b1) .ne. 1)) stop 1 + if (any (minloc (b1, back=.false.) .ne. 1)) stop 2 + if (any (minloc (b1, back=.true.) .ne. 10)) stop 3 + if (any (minloc (b1, kind=2) .ne. 1)) stop 4 + if (any (minloc (b1, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (b1, kind=8, back=.true.) .ne. 10)) stop 6 + if (minloc (b1, 1) .ne. 1) stop 7 + if (minloc (b1, 1, back=.false.) .ne. 1) stop 8 + if (minloc (b1, 1, back=.true.) .ne. 10) stop 9 + if (minloc (b1, 1, kind=1) .ne. 1) stop 10 + if (minloc (b1, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (minloc (b1, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (minloc (b1, 1, l2) .ne. 1) stop 13 + if (minloc (b1, 1, l2, back=.false.) .ne. 1) stop 14 + if (minloc (b1, 1, l2, back=.true.) .ne. 10) stop 15 + if (minloc (b1, 1, l2, kind=8) .ne. 1) stop 16 + if (minloc (b1, 1, l2, 4, .false.) .ne. 1) stop 17 + if (minloc (b1, 1, l2, 2, .true.) .ne. 10) stop 18 + if (minloc (b1, 1, l3) .ne. 1) stop 19 + if (minloc (b1, 1, l3, back=.false.) .ne. 1) stop 20 + if (minloc (b1, 1, l3, back=.true.) .ne. 10) stop 21 + if (minloc (b1, 1, l3, kind=8) .ne. 1) stop 22 + if (minloc (b1, 1, l3, 4, .false.) .ne. 1) stop 23 + if (minloc (b1, 1, l3, 2, .true.) .ne. 10) stop 24 + a2 = 0 + if (any (minloc (a2) .ne. 1)) stop 1 + if (any (minloc (a2, back=.false.) .ne. 1)) stop 2 + if (any (minloc (a2, back=.true.) .ne. 10)) stop 3 + if (any (minloc (a2, kind=2) .ne. 1)) stop 4 + if (any (minloc (a2, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (a2, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (minloc (a2, 1) .ne. 1)) stop 7 + if (any (minloc (a2, 1, back=.false.) .ne. 1)) stop 8 + if (any (minloc (a2, 1, back=.true.) .ne. 10)) stop 9 + if (any (minloc (a2, 1, kind=1) .ne. 1)) stop 10 + if (any (minloc (a2, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (minloc (a2, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (minloc (a2, 1, l1) .ne. 1)) stop 13 + if (any (minloc (a2, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (minloc (a2, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (minloc (a2, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (minloc (a2, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (minloc (a2, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (minloc (a2, 1, l3) .ne. 1)) stop 19 + if (any (minloc (a2, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (minloc (a2, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (minloc (a2, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (minloc (a2, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (minloc (a2, 1, l3, 2, .true.) .ne. 10)) stop 24 + b2 = 0 + if (any (minloc (b2) .ne. 1)) stop 1 + if (any (minloc (b2, back=.false.) .ne. 1)) stop 2 + if (any (minloc (b2, back=.true.) .ne. 10)) stop 3 + if (any (minloc (b2, kind=2) .ne. 1)) stop 4 + if (any (minloc (b2, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (b2, kind=8, back=.true.) .ne. 10)) stop 6 + if (minloc (b2, 1) .ne. 1) stop 7 + if (minloc (b2, 1, back=.false.) .ne. 1) stop 8 + if (minloc (b2, 1, back=.true.) .ne. 10) stop 9 + if (minloc (b2, 1, kind=1) .ne. 1) stop 10 + if (minloc (b2, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (minloc (b2, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (minloc (b2, 1, l2) .ne. 1) stop 13 + if (minloc (b2, 1, l2, back=.false.) .ne. 1) stop 14 + if (minloc (b2, 1, l2, back=.true.) .ne. 10) stop 15 + if (minloc (b2, 1, l2, kind=8) .ne. 1) stop 16 + if (minloc (b2, 1, l2, 4, .false.) .ne. 1) stop 17 + if (minloc (b2, 1, l2, 2, .true.) .ne. 10) stop 18 + if (minloc (b2, 1, l3) .ne. 1) stop 19 + if (minloc (b2, 1, l3, back=.false.) .ne. 1) stop 20 + if (minloc (b2, 1, l3, back=.true.) .ne. 10) stop 21 + if (minloc (b2, 1, l3, kind=8) .ne. 1) stop 22 + if (minloc (b2, 1, l3, 4, .false.) .ne. 1) stop 23 + if (minloc (b2, 1, l3, 2, .true.) .ne. 10) stop 24 + a4 = 0 + if (any (minloc (a4) .ne. 1)) stop 1 + if (any (minloc (a4, back=.false.) .ne. 1)) stop 2 + if (any (minloc (a4, back=.true.) .ne. 10)) stop 3 + if (any (minloc (a4, kind=2) .ne. 1)) stop 4 + if (any (minloc (a4, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (a4, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (minloc (a4, 1) .ne. 1)) stop 7 + if (any (minloc (a4, 1, back=.false.) .ne. 1)) stop 8 + if (any (minloc (a4, 1, back=.true.) .ne. 10)) stop 9 + if (any (minloc (a4, 1, kind=1) .ne. 1)) stop 10 + if (any (minloc (a4, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (minloc (a4, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (minloc (a4, 1, l1) .ne. 1)) stop 13 + if (any (minloc (a4, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (minloc (a4, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (minloc (a4, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (minloc (a4, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (minloc (a4, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (minloc (a4, 1, l3) .ne. 1)) stop 19 + if (any (minloc (a4, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (minloc (a4, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (minloc (a4, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (minloc (a4, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (minloc (a4, 1, l3, 2, .true.) .ne. 10)) stop 24 + b4 = 0 + if (any (minloc (b4) .ne. 1)) stop 1 + if (any (minloc (b4, back=.false.) .ne. 1)) stop 2 + if (any (minloc (b4, back=.true.) .ne. 10)) stop 3 + if (any (minloc (b4, kind=2) .ne. 1)) stop 4 + if (any (minloc (b4, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (b4, kind=8, back=.true.) .ne. 10)) stop 6 + if (minloc (b4, 1) .ne. 1) stop 7 + if (minloc (b4, 1, back=.false.) .ne. 1) stop 8 + if (minloc (b4, 1, back=.true.) .ne. 10) stop 9 + if (minloc (b4, 1, kind=1) .ne. 1) stop 10 + if (minloc (b4, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (minloc (b4, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (minloc (b4, 1, l2) .ne. 1) stop 13 + if (minloc (b4, 1, l2, back=.false.) .ne. 1) stop 14 + if (minloc (b4, 1, l2, back=.true.) .ne. 10) stop 15 + if (minloc (b4, 1, l2, kind=8) .ne. 1) stop 16 + if (minloc (b4, 1, l2, 4, .false.) .ne. 1) stop 17 + if (minloc (b4, 1, l2, 2, .true.) .ne. 10) stop 18 + if (minloc (b4, 1, l3) .ne. 1) stop 19 + if (minloc (b4, 1, l3, back=.false.) .ne. 1) stop 20 + if (minloc (b4, 1, l3, back=.true.) .ne. 10) stop 21 + if (minloc (b4, 1, l3, kind=8) .ne. 1) stop 22 + if (minloc (b4, 1, l3, 4, .false.) .ne. 1) stop 23 + if (minloc (b4, 1, l3, 2, .true.) .ne. 10) stop 24 + a8 = 0 + if (any (minloc (a8) .ne. 1)) stop 1 + if (any (minloc (a8, back=.false.) .ne. 1)) stop 2 + if (any (minloc (a8, back=.true.) .ne. 10)) stop 3 + if (any (minloc (a8, kind=2) .ne. 1)) stop 4 + if (any (minloc (a8, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (a8, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (minloc (a8, 1) .ne. 1)) stop 7 + if (any (minloc (a8, 1, back=.false.) .ne. 1)) stop 8 + if (any (minloc (a8, 1, back=.true.) .ne. 10)) stop 9 + if (any (minloc (a8, 1, kind=1) .ne. 1)) stop 10 + if (any (minloc (a8, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (minloc (a8, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (minloc (a8, 1, l1) .ne. 1)) stop 13 + if (any (minloc (a8, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (minloc (a8, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (minloc (a8, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (minloc (a8, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (minloc (a8, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (minloc (a8, 1, l3) .ne. 1)) stop 19 + if (any (minloc (a8, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (minloc (a8, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (minloc (a8, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (minloc (a8, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (minloc (a8, 1, l3, 2, .true.) .ne. 10)) stop 24 + b8 = 0 + if (any (minloc (b8) .ne. 1)) stop 1 + if (any (minloc (b8, back=.false.) .ne. 1)) stop 2 + if (any (minloc (b8, back=.true.) .ne. 10)) stop 3 + if (any (minloc (b8, kind=2) .ne. 1)) stop 4 + if (any (minloc (b8, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (b8, kind=8, back=.true.) .ne. 10)) stop 6 + if (minloc (b8, 1) .ne. 1) stop 7 + if (minloc (b8, 1, back=.false.) .ne. 1) stop 8 + if (minloc (b8, 1, back=.true.) .ne. 10) stop 9 + if (minloc (b8, 1, kind=1) .ne. 1) stop 10 + if (minloc (b8, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (minloc (b8, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (minloc (b8, 1, l2) .ne. 1) stop 13 + if (minloc (b8, 1, l2, back=.false.) .ne. 1) stop 14 + if (minloc (b8, 1, l2, back=.true.) .ne. 10) stop 15 + if (minloc (b8, 1, l2, kind=8) .ne. 1) stop 16 + if (minloc (b8, 1, l2, 4, .false.) .ne. 1) stop 17 + if (minloc (b8, 1, l2, 2, .true.) .ne. 10) stop 18 + if (minloc (b8, 1, l3) .ne. 1) stop 19 + if (minloc (b8, 1, l3, back=.false.) .ne. 1) stop 20 + if (minloc (b8, 1, l3, back=.true.) .ne. 10) stop 21 + if (minloc (b8, 1, l3, kind=8) .ne. 1) stop 22 + if (minloc (b8, 1, l3, 4, .false.) .ne. 1) stop 23 + if (minloc (b8, 1, l3, 2, .true.) .ne. 10) stop 24 + r4 = 0.0 + if (any (minloc (r4) .ne. 1)) stop 1 + if (any (minloc (r4, back=.false.) .ne. 1)) stop 2 + if (any (minloc (r4, back=.true.) .ne. 10)) stop 3 + if (any (minloc (r4, kind=2) .ne. 1)) stop 4 + if (any (minloc (r4, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (r4, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (minloc (r4, 1) .ne. 1)) stop 7 + if (any (minloc (r4, 1, back=.false.) .ne. 1)) stop 8 + if (any (minloc (r4, 1, back=.true.) .ne. 10)) stop 9 + if (any (minloc (r4, 1, kind=1) .ne. 1)) stop 10 + if (any (minloc (r4, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (minloc (r4, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (minloc (r4, 1, l1) .ne. 1)) stop 13 + if (any (minloc (r4, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (minloc (r4, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (minloc (r4, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (minloc (r4, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (minloc (r4, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (minloc (r4, 1, l3) .ne. 1)) stop 19 + if (any (minloc (r4, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (minloc (r4, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (minloc (r4, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (minloc (r4, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (minloc (r4, 1, l3, 2, .true.) .ne. 10)) stop 24 + s4 = 0.0 + if (any (minloc (s4) .ne. 1)) stop 1 + if (any (minloc (s4, back=.false.) .ne. 1)) stop 2 + if (any (minloc (s4, back=.true.) .ne. 10)) stop 3 + if (any (minloc (s4, kind=2) .ne. 1)) stop 4 + if (any (minloc (s4, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (s4, kind=8, back=.true.) .ne. 10)) stop 6 + if (minloc (s4, 1) .ne. 1) stop 7 + if (minloc (s4, 1, back=.false.) .ne. 1) stop 8 + if (minloc (s4, 1, back=.true.) .ne. 10) stop 9 + if (minloc (s4, 1, kind=1) .ne. 1) stop 10 + if (minloc (s4, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (minloc (s4, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (minloc (s4, 1, l2) .ne. 1) stop 13 + if (minloc (s4, 1, l2, back=.false.) .ne. 1) stop 14 + if (minloc (s4, 1, l2, back=.true.) .ne. 10) stop 15 + if (minloc (s4, 1, l2, kind=8) .ne. 1) stop 16 + if (minloc (s4, 1, l2, 4, .false.) .ne. 1) stop 17 + if (minloc (s4, 1, l2, 2, .true.) .ne. 10) stop 18 + if (minloc (s4, 1, l3) .ne. 1) stop 19 + if (minloc (s4, 1, l3, back=.false.) .ne. 1) stop 20 + if (minloc (s4, 1, l3, back=.true.) .ne. 10) stop 21 + if (minloc (s4, 1, l3, kind=8) .ne. 1) stop 22 + if (minloc (s4, 1, l3, 4, .false.) .ne. 1) stop 23 + if (minloc (s4, 1, l3, 2, .true.) .ne. 10) stop 24 + r8 = 0.0 + if (any (minloc (r8) .ne. 1)) stop 1 + if (any (minloc (r8, back=.false.) .ne. 1)) stop 2 + if (any (minloc (r8, back=.true.) .ne. 10)) stop 3 + if (any (minloc (r8, kind=2) .ne. 1)) stop 4 + if (any (minloc (r8, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (r8, kind=8, back=.true.) .ne. 10)) stop 6 + if (any (minloc (r8, 1) .ne. 1)) stop 7 + if (any (minloc (r8, 1, back=.false.) .ne. 1)) stop 8 + if (any (minloc (r8, 1, back=.true.) .ne. 10)) stop 9 + if (any (minloc (r8, 1, kind=1) .ne. 1)) stop 10 + if (any (minloc (r8, 1, kind=2, back=.false.) .ne. 1)) stop 11 + if (any (minloc (r8, 1, kind=4, back=.true.) .ne. 10)) stop 12 + if (any (minloc (r8, 1, l1) .ne. 1)) stop 13 + if (any (minloc (r8, 1, l1, back=.false.) .ne. 1)) stop 14 + if (any (minloc (r8, 1, l1, back=.true.) .ne. 10)) stop 15 + if (any (minloc (r8, 1, l1, kind=8) .ne. 1)) stop 16 + if (any (minloc (r8, 1, l1, 4, .false.) .ne. 1)) stop 17 + if (any (minloc (r8, 1, l1, 2, .true.) .ne. 10)) stop 18 + if (any (minloc (r8, 1, l3) .ne. 1)) stop 19 + if (any (minloc (r8, 1, l3, back=.false.) .ne. 1)) stop 20 + if (any (minloc (r8, 1, l3, back=.true.) .ne. 10)) stop 21 + if (any (minloc (r8, 1, l3, kind=8) .ne. 1)) stop 22 + if (any (minloc (r8, 1, l3, 4, .false.) .ne. 1)) stop 23 + if (any (minloc (r8, 1, l3, 2, .true.) .ne. 10)) stop 24 + s8 = 0.0 + if (any (minloc (s8) .ne. 1)) stop 1 + if (any (minloc (s8, back=.false.) .ne. 1)) stop 2 + if (any (minloc (s8, back=.true.) .ne. 10)) stop 3 + if (any (minloc (s8, kind=2) .ne. 1)) stop 4 + if (any (minloc (s8, kind=4, back=.false.) .ne. 1)) stop 5 + if (any (minloc (s8, kind=8, back=.true.) .ne. 10)) stop 6 + if (minloc (s8, 1) .ne. 1) stop 7 + if (minloc (s8, 1, back=.false.) .ne. 1) stop 8 + if (minloc (s8, 1, back=.true.) .ne. 10) stop 9 + if (minloc (s8, 1, kind=1) .ne. 1) stop 10 + if (minloc (s8, 1, kind=2, back=.false.) .ne. 1) stop 11 + if (minloc (s8, 1, kind=4, back=.true.) .ne. 10) stop 12 + if (minloc (s8, 1, l2) .ne. 1) stop 13 + if (minloc (s8, 1, l2, back=.false.) .ne. 1) stop 14 + if (minloc (s8, 1, l2, back=.true.) .ne. 10) stop 15 + if (minloc (s8, 1, l2, kind=8) .ne. 1) stop 16 + if (minloc (s8, 1, l2, 4, .false.) .ne. 1) stop 17 + if (minloc (s8, 1, l2, 2, .true.) .ne. 10) stop 18 + if (minloc (s8, 1, l3) .ne. 1) stop 19 + if (minloc (s8, 1, l3, back=.false.) .ne. 1) stop 20 + if (minloc (s8, 1, l3, back=.true.) .ne. 10) stop 21 + if (minloc (s8, 1, l3, kind=8) .ne. 1) stop 22 + if (minloc (s8, 1, l3, 4, .false.) .ne. 1) stop 23 + if (minloc (s8, 1, l3, 2, .true.) .ne. 10) stop 24 +end diff --git a/gcc/testsuite/gfortran.dg/pr120191_2.f90 b/gcc/testsuite/gfortran.dg/pr120191_2.f90 new file mode 100644 index 0000000..6334286 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr120191_2.f90 @@ -0,0 +1,84 @@ +! PR fortran/120191 +! { dg-do run } + + character(kind=1, len=2) :: a(4, 4, 4), b(4) + logical :: l(4, 4, 4), m, n(4) + a = 'aa' + b = 'aa' + l = .true. + m = .true. + n = .true. + if (any (maxloc (a) .ne. 1)) stop 1 + if (any (maxloc (a, dim=1) .ne. 1)) stop 2 + if (any (maxloc (a, 1) .ne. 1)) stop 3 + if (any (maxloc (a, dim=1, mask=l, kind=4, back=.false.) .ne. 1)) stop 4 + if (any (maxloc (a, 1, l, 4, .false.) .ne. 1)) stop 5 + if (any (maxloc (a, dim=1, mask=m, kind=4, back=.false.) .ne. 1)) stop 6 + if (any (maxloc (a, 1, m, 4, .false.) .ne. 1)) stop 7 + if (any (maxloc (a, dim=1, mask=l, kind=4, back=.true.) .ne. 4)) stop 8 + if (any (maxloc (a, 1, l, 4, .true.) .ne. 4)) stop 9 + if (any (maxloc (a, dim=1, mask=m, kind=4, back=.true.) .ne. 4)) stop 10 + if (any (maxloc (a, 1, m, 4, .true.) .ne. 4)) stop 11 + if (any (maxloc (b) .ne. 1)) stop 12 + if (maxloc (b, dim=1) .ne. 1) stop 13 + if (maxloc (b, 1) .ne. 1) stop 14 + if (maxloc (b, dim=1, mask=n, kind=4, back=.false.) .ne. 1) stop 15 + if (maxloc (b, 1, n, 4, .false.) .ne. 1) stop 16 + if (maxloc (b, dim=1, mask=m, kind=4, back=.false.) .ne. 1) stop 17 + if (maxloc (b, 1, m, 4, .false.) .ne. 1) stop 18 + if (maxloc (b, dim=1, mask=n, kind=4, back=.true.) .ne. 4) stop 19 + if (maxloc (b, 1, n, 4, .true.) .ne. 4) stop 20 + if (maxloc (b, dim=1, mask=m, kind=4, back=.true.) .ne. 4) stop 21 + if (maxloc (b, 1, m, 4, .true.) .ne. 4) stop 22 + l = .false. + m = .false. + n = .false. + if (any (maxloc (a, dim=1, mask=l, kind=4, back=.false.) .ne. 0)) stop 23 + if (any (maxloc (a, 1, l, 4, .false.) .ne. 0)) stop 24 + if (maxloc (b, dim=1, mask=n, kind=4, back=.false.) .ne. 0) stop 25 + if (maxloc (b, 1, n, 4, .false.) .ne. 0) stop 26 + if (maxloc (b, dim=1, mask=m, kind=4, back=.false.) .ne. 0) stop 27 + if (maxloc (b, 1, m, 4, .false.) .ne. 0) stop 28 + if (maxloc (b, dim=1, mask=n, kind=4, back=.true.) .ne. 0) stop 29 + if (maxloc (b, 1, n, 4, .true.) .ne. 0) stop 30 + if (maxloc (b, dim=1, mask=m, kind=4, back=.true.) .ne. 0) stop 31 + if (maxloc (b, 1, m, 4, .true.) .ne. 0) stop 32 + l = .true. + m = .true. + n = .true. + if (any (minloc (a) .ne. 1)) stop 1 + if (any (minloc (a, dim=1) .ne. 1)) stop 2 + if (any (minloc (a, 1) .ne. 1)) stop 3 + if (any (minloc (a, dim=1, mask=l, kind=4, back=.false.) .ne. 1)) stop 4 + if (any (minloc (a, 1, l, 4, .false.) .ne. 1)) stop 5 + if (any (minloc (a, dim=1, mask=m, kind=4, back=.false.) .ne. 1)) stop 6 + if (any (minloc (a, 1, m, 4, .false.) .ne. 1)) stop 7 + if (any (minloc (a, dim=1, mask=l, kind=4, back=.true.) .ne. 4)) stop 8 + if (any (minloc (a, 1, l, 4, .true.) .ne. 4)) stop 9 + if (any (minloc (a, dim=1, mask=m, kind=4, back=.true.) .ne. 4)) stop 10 + if (any (minloc (a, 1, m, 4, .true.) .ne. 4)) stop 11 + if (any (minloc (b) .ne. 1)) stop 12 + if (minloc (b, dim=1) .ne. 1) stop 13 + if (minloc (b, 1) .ne. 1) stop 14 + if (minloc (b, dim=1, mask=n, kind=4, back=.false.) .ne. 1) stop 15 + if (minloc (b, 1, n, 4, .false.) .ne. 1) stop 16 + if (minloc (b, dim=1, mask=m, kind=4, back=.false.) .ne. 1) stop 17 + if (minloc (b, 1, m, 4, .false.) .ne. 1) stop 18 + if (minloc (b, dim=1, mask=n, kind=4, back=.true.) .ne. 4) stop 19 + if (minloc (b, 1, n, 4, .true.) .ne. 4) stop 20 + if (minloc (b, dim=1, mask=m, kind=4, back=.true.) .ne. 4) stop 21 + if (minloc (b, 1, m, 4, .true.) .ne. 4) stop 22 + l = .false. + m = .false. + n = .false. + if (any (minloc (a, dim=1, mask=l, kind=4, back=.false.) .ne. 0)) stop 23 + if (any (minloc (a, 1, l, 4, .false.) .ne. 0)) stop 24 + if (minloc (b, dim=1, mask=n, kind=4, back=.false.) .ne. 0) stop 25 + if (minloc (b, 1, n, 4, .false.) .ne. 0) stop 26 + if (minloc (b, dim=1, mask=m, kind=4, back=.false.) .ne. 0) stop 27 + if (minloc (b, 1, m, 4, .false.) .ne. 0) stop 28 + if (minloc (b, dim=1, mask=n, kind=4, back=.true.) .ne. 0) stop 29 + if (minloc (b, 1, n, 4, .true.) .ne. 0) stop 30 + if (minloc (b, dim=1, mask=m, kind=4, back=.true.) .ne. 0) stop 31 + if (minloc (b, 1, m, 4, .true.) .ne. 0) stop 32 +end diff --git a/gcc/testsuite/gfortran.dg/pr120191_3.f90 b/gcc/testsuite/gfortran.dg/pr120191_3.f90 new file mode 100644 index 0000000..26e4095 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr120191_3.f90 @@ -0,0 +1,23 @@ +! PR fortran/120191 +! { dg-do run } + + character(kind=1, len=2) :: a(4, 4, 4), b(4) + logical :: l(4, 4, 4), m, n(4) + a = 'aa' + b = 'aa' + l = .false. + m = .false. + n = .false. + if (any (maxloc (a, dim=1, mask=m, kind=4, back=.false.) .ne. 0)) stop 1 + if (any (maxloc (a, 1, m, 4, .false.) .ne. 0)) stop 2 + if (any (maxloc (a, dim=1, mask=l, kind=4, back=.true.) .ne. 0)) stop 3 + if (any (maxloc (a, 1, l, 4, .true.) .ne. 0)) stop 4 + if (any (maxloc (a, dim=1, mask=m, kind=4, back=.true.) .ne. 0)) stop 5 + if (any (maxloc (a, 1, m, 4, .true.) .ne. 0)) stop 6 + if (any (minloc (a, dim=1, mask=m, kind=4, back=.false.) .ne. 0)) stop 7 + if (any (minloc (a, 1, m, 4, .false.) .ne. 0)) stop 8 + if (any (minloc (a, dim=1, mask=l, kind=4, back=.true.) .ne. 0)) stop 9 + if (any (minloc (a, 1, l, 4, .true.) .ne. 0)) stop 10 + if (any (minloc (a, dim=1, mask=m, kind=4, back=.true.) .ne. 0)) stop 11 + if (any (minloc (a, 1, m, 4, .true.) .ne. 0)) stop 12 +end diff --git a/gcc/testsuite/gfortran.dg/pr120196.f90 b/gcc/testsuite/gfortran.dg/pr120196.f90 new file mode 100644 index 0000000..368c43a --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr120196.f90 @@ -0,0 +1,26 @@ +! PR libfortran/120196 +! { dg-do run } + +program pr120196 + character(len=:, kind=1), allocatable :: a(:), s + character(len=:, kind=4), allocatable :: b(:), t + logical, allocatable :: l(:) + logical :: m + allocate (character(len=16, kind=1) :: a(10), s) + allocate (l(10)) + a(:) = "" + s = "*" + l = .true. + m = .true. + if (findloc (a, s, dim=1, back=.true.) .ne. 0) stop 1 + if (findloc (a, s, mask=l, dim=1, back=.true.) .ne. 0) stop 2 + if (findloc (a, s, mask=m, dim=1, back=.true.) .ne. 0) stop 3 + deallocate (a, s) + allocate (character(len=16, kind=4) :: b(10), t) + b(:) = "" + t = "*" + if (findloc (b, t, dim=1, back=.true.) .ne. 0) stop 4 + if (findloc (b, t, mask=l, dim=1, back=.true.) .ne. 0) stop 5 + if (findloc (b, t, mask=m, dim=1, back=.true.) .ne. 0) stop 6 + deallocate (b, t, l) +end program pr120196 diff --git a/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp b/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp index 8a41ff8..6ddf2d5 100644 --- a/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp +++ b/gcc/testsuite/gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp @@ -11,7 +11,7 @@ gm2_init_pim4 $srcdir/$subdir dg-init # If the --enable-plugin has not been enabled during configure, bail. -if { ![gm2-dg-frontend-configure-check "enable-plugin" ] } { +if { ![info exists TESTING_IN_BUILD_TREE] || ![info exists ENABLE_PLUGIN] } { return } diff --git a/gcc/tree-cfg.cc b/gcc/tree-cfg.cc index 6a95b82..928459a 100644 --- a/gcc/tree-cfg.cc +++ b/gcc/tree-cfg.cc @@ -3870,7 +3870,6 @@ verify_gimple_assign_unary (gassign *stmt) case NEGATE_EXPR: case ABS_EXPR: case BIT_NOT_EXPR: - case PAREN_EXPR: case CONJ_EXPR: /* Disallow pointer and offset types for many of the unary gimple. */ if (POINTER_TYPE_P (lhs_type) @@ -3883,6 +3882,17 @@ verify_gimple_assign_unary (gassign *stmt) } break; + case PAREN_EXPR: + /* Disallow non arthmetic types on PAREN_EXPR. */ + if (AGGREGATE_TYPE_P (lhs_type)) + { + error ("invalid types for %qs", code_name); + debug_generic_expr (lhs_type); + debug_generic_expr (rhs1_type); + return true; + } + break; + case ABSU_EXPR: if (!ANY_INTEGRAL_TYPE_P (lhs_type) || !TYPE_UNSIGNED (lhs_type) diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc index fe6f3cf..2d1a688 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -9698,7 +9698,7 @@ vectorizable_nonlinear_induction (loop_vec_info loop_vinfo, gphi *phi = dyn_cast <gphi *> (stmt_info->stmt); - tree vectype = STMT_VINFO_VECTYPE (stmt_info); + tree vectype = SLP_TREE_VECTYPE (slp_node); poly_uint64 nunits = TYPE_VECTOR_SUBPARTS (vectype); enum vect_induction_op_type induction_type = STMT_VINFO_LOOP_PHI_EVOLUTION_TYPE (stmt_info); @@ -9723,7 +9723,7 @@ vectorizable_nonlinear_induction (loop_vec_info loop_vinfo, /* TODO: Support multi-lane SLP for nonlinear iv. There should be separate vector iv update for each iv and a permutation to generate wanted vector iv. */ - if (slp_node && SLP_TREE_LANES (slp_node) > 1) + if (SLP_TREE_LANES (slp_node) > 1) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -9934,13 +9934,7 @@ vectorizable_nonlinear_induction (loop_vec_info loop_vinfo, add_phi_arg (induction_phi, vec_def, loop_latch_edge (iv_loop), UNKNOWN_LOCATION); - if (slp_node) - slp_node->push_vec_def (induction_phi); - else - { - STMT_VINFO_VEC_STMTS (stmt_info).safe_push (induction_phi); - *vec_stmt = induction_phi; - } + slp_node->push_vec_def (induction_phi); /* In case that vectorization factor (VF) is bigger than the number of elements that we can fit in a vectype (nunits), we have to generate @@ -9970,10 +9964,7 @@ vectorizable_nonlinear_induction (loop_vec_info loop_vinfo, induction_type); gsi_insert_seq_before (&si, stmts, GSI_SAME_STMT); new_stmt = SSA_NAME_DEF_STMT (vec_def); - if (slp_node) - slp_node->push_vec_def (new_stmt); - else - STMT_VINFO_VEC_STMTS (stmt_info).safe_push (new_stmt); + slp_node->push_vec_def (new_stmt); } } @@ -9999,15 +9990,13 @@ vectorizable_induction (loop_vec_info loop_vinfo, stmt_vector_for_cost *cost_vec) { class loop *loop = LOOP_VINFO_LOOP (loop_vinfo); - unsigned ncopies; bool nested_in_vect_loop = false; class loop *iv_loop; tree vec_def; edge pe = loop_preheader_edge (loop); basic_block new_bb; - tree new_vec, vec_init = NULL_TREE, vec_step, t; + tree vec_init = NULL_TREE, vec_step, t; tree new_name; - gimple *new_stmt; gphi *induction_phi; tree induc_def, vec_dest; poly_uint64 vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo); @@ -10034,15 +10023,9 @@ vectorizable_induction (loop_vec_info loop_vinfo, return vectorizable_nonlinear_induction (loop_vinfo, stmt_info, vec_stmt, slp_node, cost_vec); - tree vectype = STMT_VINFO_VECTYPE (stmt_info); + tree vectype = SLP_TREE_VECTYPE (slp_node); poly_uint64 nunits = TYPE_VECTOR_SUBPARTS (vectype); - if (slp_node) - ncopies = 1; - else - ncopies = vect_get_num_copies (loop_vinfo, vectype); - gcc_assert (ncopies >= 1); - /* FORNOW. These restrictions should be relaxed. */ if (nested_in_vect_loop_p (loop, stmt_info)) { @@ -10052,14 +10035,6 @@ vectorizable_induction (loop_vec_info loop_vinfo, edge latch_e; tree loop_arg; - if (ncopies > 1) - { - if (dump_enabled_p ()) - dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, - "multiple types in nested loop.\n"); - return false; - } - exit_phi = NULL; latch_e = loop_latch_edge (loop->inner); loop_arg = PHI_ARG_DEF_FROM_EDGE (phi, latch_e); @@ -10096,7 +10071,7 @@ vectorizable_induction (loop_vec_info loop_vinfo, iv_loop = loop; gcc_assert (iv_loop == (gimple_bb (phi))->loop_father); - if (slp_node && (!nunits.is_constant () && SLP_TREE_LANES (slp_node) != 1)) + if (!nunits.is_constant () && SLP_TREE_LANES (slp_node) != 1) { /* The current SLP code creates the step value element-by-element. */ if (dump_enabled_p ()) @@ -10152,41 +10127,28 @@ vectorizable_induction (loop_vec_info loop_vinfo, if (!vec_stmt) /* transformation not required. */ { unsigned inside_cost = 0, prologue_cost = 0; - if (slp_node) - { - /* We eventually need to set a vector type on invariant - arguments. */ - unsigned j; - slp_tree child; - FOR_EACH_VEC_ELT (SLP_TREE_CHILDREN (slp_node), j, child) - if (!vect_maybe_update_slp_op_vectype - (child, SLP_TREE_VECTYPE (slp_node))) - { - if (dump_enabled_p ()) - dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, - "incompatible vector types for " - "invariants\n"); - return false; - } - /* loop cost for vec_loop. */ - inside_cost - = record_stmt_cost (cost_vec, - SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node), - vector_stmt, stmt_info, 0, vect_body); - /* prologue cost for vec_init (if not nested) and step. */ - prologue_cost = record_stmt_cost (cost_vec, 1 + !nested_in_vect_loop, - scalar_to_vec, - stmt_info, 0, vect_prologue); - } - else /* if (!slp_node) */ - { - /* loop cost for vec_loop. */ - inside_cost = record_stmt_cost (cost_vec, ncopies, vector_stmt, - stmt_info, 0, vect_body); - /* prologue cost for vec_init and vec_step. */ - prologue_cost = record_stmt_cost (cost_vec, 2, scalar_to_vec, - stmt_info, 0, vect_prologue); - } + /* We eventually need to set a vector type on invariant + arguments. */ + unsigned j; + slp_tree child; + FOR_EACH_VEC_ELT (SLP_TREE_CHILDREN (slp_node), j, child) + if (!vect_maybe_update_slp_op_vectype + (child, SLP_TREE_VECTYPE (slp_node))) + { + if (dump_enabled_p ()) + dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, + "incompatible vector types for " + "invariants\n"); + return false; + } + /* loop cost for vec_loop. */ + inside_cost = record_stmt_cost (cost_vec, + SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node), + vector_stmt, stmt_info, 0, vect_body); + /* prologue cost for vec_init (if not nested) and step. */ + prologue_cost = record_stmt_cost (cost_vec, 1 + !nested_in_vect_loop, + scalar_to_vec, + stmt_info, 0, vect_prologue); if (dump_enabled_p ()) dump_printf_loc (MSG_NOTE, vect_location, "vect_model_induction_cost: inside_cost = %d, " @@ -10217,670 +10179,374 @@ vectorizable_induction (loop_vec_info loop_vinfo, with group size 3 we need [i0, i1, i2, i0 + S0] [i1 + S1, i2 + S2, i0 + 2*S0, i1 + 2*S1] [i2 + 2*S2, i0 + 3*S0, i1 + 3*S1, i2 + 3*S2]. */ - if (slp_node) + gimple_stmt_iterator incr_si; + bool insert_after; + standard_iv_increment_position (iv_loop, &incr_si, &insert_after); + + /* The initial values are vectorized, but any lanes > group_size + need adjustment. */ + slp_tree init_node + = SLP_TREE_CHILDREN (slp_node)[pe->dest_idx]; + + /* Gather steps. Since we do not vectorize inductions as + cycles we have to reconstruct the step from SCEV data. */ + unsigned group_size = SLP_TREE_LANES (slp_node); + tree *steps = XALLOCAVEC (tree, group_size); + tree *inits = XALLOCAVEC (tree, group_size); + stmt_vec_info phi_info; + FOR_EACH_VEC_ELT (SLP_TREE_SCALAR_STMTS (slp_node), i, phi_info) + { + steps[i] = STMT_VINFO_LOOP_PHI_EVOLUTION_PART (phi_info); + if (!init_node) + inits[i] = gimple_phi_arg_def (as_a<gphi *> (phi_info->stmt), + pe->dest_idx); + } + + /* Now generate the IVs. */ + unsigned nvects = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node); + gcc_assert (multiple_p (nunits * nvects, group_size)); + unsigned nivs; + unsigned HOST_WIDE_INT const_nunits; + if (nested_in_vect_loop) + nivs = nvects; + else if (nunits.is_constant (&const_nunits)) { - gimple_stmt_iterator incr_si; - bool insert_after; - standard_iv_increment_position (iv_loop, &incr_si, &insert_after); - - /* The initial values are vectorized, but any lanes > group_size - need adjustment. */ - slp_tree init_node - = SLP_TREE_CHILDREN (slp_node)[pe->dest_idx]; - - /* Gather steps. Since we do not vectorize inductions as - cycles we have to reconstruct the step from SCEV data. */ - unsigned group_size = SLP_TREE_LANES (slp_node); - tree *steps = XALLOCAVEC (tree, group_size); - tree *inits = XALLOCAVEC (tree, group_size); - stmt_vec_info phi_info; - FOR_EACH_VEC_ELT (SLP_TREE_SCALAR_STMTS (slp_node), i, phi_info) - { - steps[i] = STMT_VINFO_LOOP_PHI_EVOLUTION_PART (phi_info); - if (!init_node) - inits[i] = gimple_phi_arg_def (as_a<gphi *> (phi_info->stmt), - pe->dest_idx); - } - - /* Now generate the IVs. */ - unsigned nvects = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node); - gcc_assert (multiple_p (nunits * nvects, group_size)); - unsigned nivs; - unsigned HOST_WIDE_INT const_nunits; - if (nested_in_vect_loop) - nivs = nvects; - else if (nunits.is_constant (&const_nunits)) - { - /* Compute the number of distinct IVs we need. First reduce - group_size if it is a multiple of const_nunits so we get - one IV for a group_size of 4 but const_nunits 2. */ - unsigned group_sizep = group_size; - if (group_sizep % const_nunits == 0) - group_sizep = group_sizep / const_nunits; - nivs = least_common_multiple (group_sizep, - const_nunits) / const_nunits; - } - else - { - gcc_assert (SLP_TREE_LANES (slp_node) == 1); - nivs = 1; - } - gimple_seq init_stmts = NULL; - tree lupdate_mul = NULL_TREE; - if (!nested_in_vect_loop) + /* Compute the number of distinct IVs we need. First reduce + group_size if it is a multiple of const_nunits so we get + one IV for a group_size of 4 but const_nunits 2. */ + unsigned group_sizep = group_size; + if (group_sizep % const_nunits == 0) + group_sizep = group_sizep / const_nunits; + nivs = least_common_multiple (group_sizep, const_nunits) / const_nunits; + } + else + { + gcc_assert (SLP_TREE_LANES (slp_node) == 1); + nivs = 1; + } + gimple_seq init_stmts = NULL; + tree lupdate_mul = NULL_TREE; + if (!nested_in_vect_loop) + { + if (nunits.is_constant (&const_nunits)) { - if (nunits.is_constant (&const_nunits)) - { - /* The number of iterations covered in one vector iteration. */ - unsigned lup_mul = (nvects * const_nunits) / group_size; - lupdate_mul - = build_vector_from_val (step_vectype, - SCALAR_FLOAT_TYPE_P (stept) - ? build_real_from_wide (stept, lup_mul, - UNSIGNED) - : build_int_cstu (stept, lup_mul)); - } - else - { - if (SCALAR_FLOAT_TYPE_P (stept)) - { - tree tem = build_int_cst (integer_type_node, vf); - lupdate_mul = gimple_build (&init_stmts, FLOAT_EXPR, - stept, tem); - } - else - lupdate_mul = build_int_cst (stept, vf); - lupdate_mul = gimple_build_vector_from_val (&init_stmts, - step_vectype, - lupdate_mul); - } + /* The number of iterations covered in one vector iteration. */ + unsigned lup_mul = (nvects * const_nunits) / group_size; + lupdate_mul + = build_vector_from_val (step_vectype, + SCALAR_FLOAT_TYPE_P (stept) + ? build_real_from_wide (stept, lup_mul, + UNSIGNED) + : build_int_cstu (stept, lup_mul)); } - tree peel_mul = NULL_TREE; - if (LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo)) + else { if (SCALAR_FLOAT_TYPE_P (stept)) - peel_mul = gimple_build (&init_stmts, FLOAT_EXPR, stept, - LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo)); - else - peel_mul = gimple_convert (&init_stmts, stept, - LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo)); - peel_mul = gimple_build_vector_from_val (&init_stmts, - step_vectype, peel_mul); - - /* If early break then we have to create a new PHI which we can use as - an offset to adjust the induction reduction in early exits. - - This is because when peeling for alignment using masking, the first - few elements of the vector can be inactive. As such if we find the - entry in the first iteration we have adjust the starting point of - the scalar code. - - We do this by creating a new scalar PHI that keeps track of whether - we are the first iteration of the loop (with the additional masking) - or whether we have taken a loop iteration already. - - The generated sequence: - - pre-header: - bb1: - i_1 = <number of leading inactive elements> - - header: - bb2: - i_2 = PHI <i_1(bb1), 0(latch)> - … - - early-exit: - bb3: - i_3 = iv_step * i_2 + PHI<vector-iv> - - The first part of the adjustment to create i_1 and i_2 are done here - and the last part creating i_3 is done in - vectorizable_live_operations when the induction extraction is - materialized. */ - if (LOOP_VINFO_EARLY_BREAKS (loop_vinfo) - && !LOOP_VINFO_MASK_NITERS_PFA_OFFSET (loop_vinfo)) { - auto skip_niters = LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo); - tree ty_skip_niters = TREE_TYPE (skip_niters); - tree break_lhs_phi = vect_get_new_vect_var (ty_skip_niters, - vect_scalar_var, - "pfa_iv_offset"); - gphi *nphi = create_phi_node (break_lhs_phi, bb); - add_phi_arg (nphi, skip_niters, pe, UNKNOWN_LOCATION); - add_phi_arg (nphi, build_zero_cst (ty_skip_niters), - loop_latch_edge (iv_loop), UNKNOWN_LOCATION); - - LOOP_VINFO_MASK_NITERS_PFA_OFFSET (loop_vinfo) - = PHI_RESULT (nphi); + tree tem = build_int_cst (integer_type_node, vf); + lupdate_mul = gimple_build (&init_stmts, FLOAT_EXPR, stept, tem); } + else + lupdate_mul = build_int_cst (stept, vf); + lupdate_mul = gimple_build_vector_from_val (&init_stmts, step_vectype, + lupdate_mul); } - tree step_mul = NULL_TREE; - unsigned ivn; - auto_vec<tree> vec_steps; - for (ivn = 0; ivn < nivs; ++ivn) + } + tree peel_mul = NULL_TREE; + if (LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo)) + { + if (SCALAR_FLOAT_TYPE_P (stept)) + peel_mul = gimple_build (&init_stmts, FLOAT_EXPR, stept, + LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo)); + else + peel_mul = gimple_convert (&init_stmts, stept, + LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo)); + peel_mul = gimple_build_vector_from_val (&init_stmts, + step_vectype, peel_mul); + + /* If early break then we have to create a new PHI which we can use as + an offset to adjust the induction reduction in early exits. + + This is because when peeling for alignment using masking, the first + few elements of the vector can be inactive. As such if we find the + entry in the first iteration we have adjust the starting point of + the scalar code. + + We do this by creating a new scalar PHI that keeps track of whether + we are the first iteration of the loop (with the additional masking) + or whether we have taken a loop iteration already. + + The generated sequence: + + pre-header: + bb1: + i_1 = <number of leading inactive elements> + + header: + bb2: + i_2 = PHI <i_1(bb1), 0(latch)> + … + + early-exit: + bb3: + i_3 = iv_step * i_2 + PHI<vector-iv> + + The first part of the adjustment to create i_1 and i_2 are done here + and the last part creating i_3 is done in + vectorizable_live_operations when the induction extraction is + materialized. */ + if (LOOP_VINFO_EARLY_BREAKS (loop_vinfo) + && !LOOP_VINFO_MASK_NITERS_PFA_OFFSET (loop_vinfo)) + { + auto skip_niters = LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo); + tree ty_skip_niters = TREE_TYPE (skip_niters); + tree break_lhs_phi = vect_get_new_vect_var (ty_skip_niters, + vect_scalar_var, + "pfa_iv_offset"); + gphi *nphi = create_phi_node (break_lhs_phi, bb); + add_phi_arg (nphi, skip_niters, pe, UNKNOWN_LOCATION); + add_phi_arg (nphi, build_zero_cst (ty_skip_niters), + loop_latch_edge (iv_loop), UNKNOWN_LOCATION); + + LOOP_VINFO_MASK_NITERS_PFA_OFFSET (loop_vinfo) = PHI_RESULT (nphi); + } + } + tree step_mul = NULL_TREE; + unsigned ivn; + auto_vec<tree> vec_steps; + for (ivn = 0; ivn < nivs; ++ivn) + { + gimple_seq stmts = NULL; + bool invariant = true; + if (nunits.is_constant (&const_nunits)) { - gimple_seq stmts = NULL; - bool invariant = true; - if (nunits.is_constant (&const_nunits)) + tree_vector_builder step_elts (step_vectype, const_nunits, 1); + tree_vector_builder init_elts (vectype, const_nunits, 1); + tree_vector_builder mul_elts (step_vectype, const_nunits, 1); + for (unsigned eltn = 0; eltn < const_nunits; ++eltn) { - tree_vector_builder step_elts (step_vectype, const_nunits, 1); - tree_vector_builder init_elts (vectype, const_nunits, 1); - tree_vector_builder mul_elts (step_vectype, const_nunits, 1); - for (unsigned eltn = 0; eltn < const_nunits; ++eltn) - { - /* The scalar steps of the IVs. */ - tree elt = steps[(ivn*const_nunits + eltn) % group_size]; - elt = gimple_convert (&init_stmts, - TREE_TYPE (step_vectype), elt); - step_elts.quick_push (elt); - if (!init_node) - { - /* The scalar inits of the IVs if not vectorized. */ - elt = inits[(ivn*const_nunits + eltn) % group_size]; - if (!useless_type_conversion_p (TREE_TYPE (vectype), - TREE_TYPE (elt))) - elt = gimple_build (&init_stmts, VIEW_CONVERT_EXPR, - TREE_TYPE (vectype), elt); - init_elts.quick_push (elt); - } - /* The number of steps to add to the initial values. */ - unsigned mul_elt = (ivn*const_nunits + eltn) / group_size; - mul_elts.quick_push (SCALAR_FLOAT_TYPE_P (stept) - ? build_real_from_wide (stept, mul_elt, - UNSIGNED) - : build_int_cstu (stept, mul_elt)); - } - vec_step = gimple_build_vector (&init_stmts, &step_elts); - step_mul = gimple_build_vector (&init_stmts, &mul_elts); + /* The scalar steps of the IVs. */ + tree elt = steps[(ivn*const_nunits + eltn) % group_size]; + elt = gimple_convert (&init_stmts, TREE_TYPE (step_vectype), elt); + step_elts.quick_push (elt); if (!init_node) - vec_init = gimple_build_vector (&init_stmts, &init_elts); - } - else - { - if (init_node) - ; - else if (INTEGRAL_TYPE_P (TREE_TYPE (steps[0]))) - { - new_name = gimple_convert (&init_stmts, stept, inits[0]); - /* Build the initial value directly as a VEC_SERIES_EXPR. */ - vec_init = gimple_build (&init_stmts, VEC_SERIES_EXPR, - step_vectype, new_name, steps[0]); - if (!useless_type_conversion_p (vectype, step_vectype)) - vec_init = gimple_build (&init_stmts, VIEW_CONVERT_EXPR, - vectype, vec_init); - } - else { - /* Build: - [base, base, base, ...] - + (vectype) [0, 1, 2, ...] * [step, step, step, ...]. */ - gcc_assert (SCALAR_FLOAT_TYPE_P (TREE_TYPE (steps[0]))); - gcc_assert (flag_associative_math); - gcc_assert (index_vectype != NULL_TREE); - - tree index = build_index_vector (index_vectype, 0, 1); - new_name = gimple_convert (&init_stmts, TREE_TYPE (steps[0]), - inits[0]); - tree base_vec = gimple_build_vector_from_val (&init_stmts, - step_vectype, - new_name); - tree step_vec = gimple_build_vector_from_val (&init_stmts, - step_vectype, - steps[0]); - vec_init = gimple_build (&init_stmts, FLOAT_EXPR, - step_vectype, index); - vec_init = gimple_build (&init_stmts, MULT_EXPR, - step_vectype, vec_init, step_vec); - vec_init = gimple_build (&init_stmts, PLUS_EXPR, - step_vectype, vec_init, base_vec); - if (!useless_type_conversion_p (vectype, step_vectype)) - vec_init = gimple_build (&init_stmts, VIEW_CONVERT_EXPR, - vectype, vec_init); + /* The scalar inits of the IVs if not vectorized. */ + elt = inits[(ivn*const_nunits + eltn) % group_size]; + if (!useless_type_conversion_p (TREE_TYPE (vectype), + TREE_TYPE (elt))) + elt = gimple_build (&init_stmts, VIEW_CONVERT_EXPR, + TREE_TYPE (vectype), elt); + init_elts.quick_push (elt); } - /* iv_loop is nested in the loop to be vectorized. Generate: - vec_step = [S, S, S, S] */ - t = unshare_expr (steps[0]); - gcc_assert (CONSTANT_CLASS_P (t) - || TREE_CODE (t) == SSA_NAME); - vec_step = gimple_build_vector_from_val (&init_stmts, - step_vectype, t); - } - vec_steps.safe_push (vec_step); - if (peel_mul) - { - if (!step_mul) - step_mul = peel_mul; - else - step_mul = gimple_build (&init_stmts, - MINUS_EXPR, step_vectype, - step_mul, peel_mul); - } - - /* Create the induction-phi that defines the induction-operand. */ - vec_dest = vect_get_new_vect_var (vectype, vect_simple_var, - "vec_iv_"); - induction_phi = create_phi_node (vec_dest, iv_loop->header); - induc_def = PHI_RESULT (induction_phi); - - /* Create the iv update inside the loop */ - tree up = vec_step; - if (lupdate_mul) - { - if (LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo)) - { - /* When we're using loop_len produced by SELEC_VL, the - non-final iterations are not always processing VF - elements. So vectorize induction variable instead of - - _21 = vect_vec_iv_.6_22 + { VF, ... }; - - We should generate: - - _35 = .SELECT_VL (ivtmp_33, VF); - vect_cst__22 = [vec_duplicate_expr] _35; - _21 = vect_vec_iv_.6_22 + vect_cst__22; */ - vec_loop_lens *lens = &LOOP_VINFO_LENS (loop_vinfo); - tree len = vect_get_loop_len (loop_vinfo, NULL, lens, 1, - vectype, 0, 0); - if (SCALAR_FLOAT_TYPE_P (stept)) - expr = gimple_build (&stmts, FLOAT_EXPR, stept, len); - else - expr = gimple_convert (&stmts, stept, len); - lupdate_mul = gimple_build_vector_from_val (&stmts, - step_vectype, - expr); - up = gimple_build (&stmts, MULT_EXPR, - step_vectype, vec_step, lupdate_mul); - } - else - up = gimple_build (&init_stmts, - MULT_EXPR, step_vectype, - vec_step, lupdate_mul); - } - vec_def = gimple_convert (&stmts, step_vectype, induc_def); - vec_def = gimple_build (&stmts, - PLUS_EXPR, step_vectype, vec_def, up); - vec_def = gimple_convert (&stmts, vectype, vec_def); - insert_iv_increment (&incr_si, insert_after, stmts); - add_phi_arg (induction_phi, vec_def, loop_latch_edge (iv_loop), - UNKNOWN_LOCATION); - - if (init_node) - vec_init = vect_get_slp_vect_def (init_node, ivn); - if (!nested_in_vect_loop - && step_mul - && !integer_zerop (step_mul)) - { - gcc_assert (invariant); - vec_def = gimple_convert (&init_stmts, step_vectype, vec_init); - up = gimple_build (&init_stmts, MULT_EXPR, step_vectype, - vec_step, step_mul); - vec_def = gimple_build (&init_stmts, PLUS_EXPR, step_vectype, - vec_def, up); - vec_init = gimple_convert (&init_stmts, vectype, vec_def); - } - - /* Set the arguments of the phi node: */ - add_phi_arg (induction_phi, vec_init, pe, UNKNOWN_LOCATION); - - slp_node->push_vec_def (induction_phi); - } - if (!nested_in_vect_loop) - { - /* Fill up to the number of vectors we need for the whole group. */ - if (nunits.is_constant (&const_nunits)) - nivs = least_common_multiple (group_size, - const_nunits) / const_nunits; - else - nivs = 1; - vec_steps.reserve (nivs-ivn); - for (; ivn < nivs; ++ivn) - { - slp_node->push_vec_def (SLP_TREE_VEC_DEFS (slp_node)[0]); - vec_steps.quick_push (vec_steps[0]); + /* The number of steps to add to the initial values. */ + unsigned mul_elt = (ivn*const_nunits + eltn) / group_size; + mul_elts.quick_push (SCALAR_FLOAT_TYPE_P (stept) + ? build_real_from_wide (stept, mul_elt, + UNSIGNED) + : build_int_cstu (stept, mul_elt)); } + vec_step = gimple_build_vector (&init_stmts, &step_elts); + step_mul = gimple_build_vector (&init_stmts, &mul_elts); + if (!init_node) + vec_init = gimple_build_vector (&init_stmts, &init_elts); } - - /* Re-use IVs when we can. We are generating further vector - stmts by adding VF' * stride to the IVs generated above. */ - if (ivn < nvects) + else { - if (nunits.is_constant (&const_nunits)) + if (init_node) + ; + else if (INTEGRAL_TYPE_P (TREE_TYPE (steps[0]))) { - unsigned vfp = (least_common_multiple (group_size, const_nunits) - / group_size); - lupdate_mul - = build_vector_from_val (step_vectype, - SCALAR_FLOAT_TYPE_P (stept) - ? build_real_from_wide (stept, - vfp, UNSIGNED) - : build_int_cstu (stept, vfp)); + new_name = gimple_convert (&init_stmts, stept, inits[0]); + /* Build the initial value directly as a VEC_SERIES_EXPR. */ + vec_init = gimple_build (&init_stmts, VEC_SERIES_EXPR, + step_vectype, new_name, steps[0]); + if (!useless_type_conversion_p (vectype, step_vectype)) + vec_init = gimple_build (&init_stmts, VIEW_CONVERT_EXPR, + vectype, vec_init); } else { - if (SCALAR_FLOAT_TYPE_P (stept)) - { - tree tem = build_int_cst (integer_type_node, nunits); - lupdate_mul = gimple_build (&init_stmts, FLOAT_EXPR, - stept, tem); - } - else - lupdate_mul = build_int_cst (stept, nunits); - lupdate_mul = gimple_build_vector_from_val (&init_stmts, - step_vectype, - lupdate_mul); - } - for (; ivn < nvects; ++ivn) - { - gimple *iv - = SSA_NAME_DEF_STMT (SLP_TREE_VEC_DEFS (slp_node)[ivn - nivs]); - tree def = gimple_get_lhs (iv); - if (ivn < 2*nivs) - vec_steps[ivn - nivs] - = gimple_build (&init_stmts, MULT_EXPR, step_vectype, - vec_steps[ivn - nivs], lupdate_mul); - gimple_seq stmts = NULL; - def = gimple_convert (&stmts, step_vectype, def); - def = gimple_build (&stmts, PLUS_EXPR, step_vectype, - def, vec_steps[ivn % nivs]); - def = gimple_convert (&stmts, vectype, def); - if (gimple_code (iv) == GIMPLE_PHI) - gsi_insert_seq_before (&si, stmts, GSI_SAME_STMT); - else - { - gimple_stmt_iterator tgsi = gsi_for_stmt (iv); - gsi_insert_seq_after (&tgsi, stmts, GSI_CONTINUE_LINKING); - } - slp_node->push_vec_def (def); + /* Build: + [base, base, base, ...] + + (vectype) [0, 1, 2, ...] * [step, step, step, ...]. */ + gcc_assert (SCALAR_FLOAT_TYPE_P (TREE_TYPE (steps[0]))); + gcc_assert (flag_associative_math); + gcc_assert (index_vectype != NULL_TREE); + + tree index = build_index_vector (index_vectype, 0, 1); + new_name = gimple_convert (&init_stmts, TREE_TYPE (steps[0]), + inits[0]); + tree base_vec = gimple_build_vector_from_val (&init_stmts, + step_vectype, + new_name); + tree step_vec = gimple_build_vector_from_val (&init_stmts, + step_vectype, + steps[0]); + vec_init = gimple_build (&init_stmts, FLOAT_EXPR, + step_vectype, index); + vec_init = gimple_build (&init_stmts, MULT_EXPR, + step_vectype, vec_init, step_vec); + vec_init = gimple_build (&init_stmts, PLUS_EXPR, + step_vectype, vec_init, base_vec); + if (!useless_type_conversion_p (vectype, step_vectype)) + vec_init = gimple_build (&init_stmts, VIEW_CONVERT_EXPR, + vectype, vec_init); } + /* iv_loop is nested in the loop to be vectorized. Generate: + vec_step = [S, S, S, S] */ + t = unshare_expr (steps[0]); + gcc_assert (CONSTANT_CLASS_P (t) + || TREE_CODE (t) == SSA_NAME); + vec_step = gimple_build_vector_from_val (&init_stmts, + step_vectype, t); + } + vec_steps.safe_push (vec_step); + if (peel_mul) + { + if (!step_mul) + step_mul = peel_mul; + else + step_mul = gimple_build (&init_stmts, + MINUS_EXPR, step_vectype, + step_mul, peel_mul); } - new_bb = gsi_insert_seq_on_edge_immediate (pe, init_stmts); - gcc_assert (!new_bb); + /* Create the induction-phi that defines the induction-operand. */ + vec_dest = vect_get_new_vect_var (vectype, vect_simple_var, + "vec_iv_"); + induction_phi = create_phi_node (vec_dest, iv_loop->header); + induc_def = PHI_RESULT (induction_phi); - return true; - } - - tree init_expr = vect_phi_initial_value (phi); - - gimple_seq stmts = NULL; - if (!nested_in_vect_loop) - { - /* Convert the initial value to the IV update type. */ - tree new_type = TREE_TYPE (step_expr); - init_expr = gimple_convert (&stmts, new_type, init_expr); - - /* If we are using the loop mask to "peel" for alignment then we need - to adjust the start value here. */ - tree skip_niters = LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo); - if (skip_niters != NULL_TREE) + /* Create the iv update inside the loop */ + tree up = vec_step; + if (lupdate_mul) { - if (FLOAT_TYPE_P (vectype)) - skip_niters = gimple_build (&stmts, FLOAT_EXPR, new_type, - skip_niters); - else - skip_niters = gimple_convert (&stmts, new_type, skip_niters); - tree skip_step = gimple_build (&stmts, MULT_EXPR, new_type, - skip_niters, step_expr); - init_expr = gimple_build (&stmts, MINUS_EXPR, new_type, - init_expr, skip_step); - } - } + if (LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo)) + { + /* When we're using loop_len produced by SELEC_VL, the + non-final iterations are not always processing VF + elements. So vectorize induction variable instead of - if (stmts) - { - new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts); - gcc_assert (!new_bb); - } + _21 = vect_vec_iv_.6_22 + { VF, ... }; - /* Create the vector that holds the initial_value of the induction. */ - if (nested_in_vect_loop) - { - /* iv_loop is nested in the loop to be vectorized. init_expr had already - been created during vectorization of previous stmts. We obtain it - from the STMT_VINFO_VEC_STMT of the defining stmt. */ - auto_vec<tree> vec_inits; - vect_get_vec_defs_for_operand (loop_vinfo, stmt_info, 1, - init_expr, &vec_inits); - vec_init = vec_inits[0]; - /* If the initial value is not of proper type, convert it. */ - if (!useless_type_conversion_p (vectype, TREE_TYPE (vec_init))) - { - new_stmt - = gimple_build_assign (vect_get_new_ssa_name (vectype, - vect_simple_var, - "vec_iv_"), - VIEW_CONVERT_EXPR, - build1 (VIEW_CONVERT_EXPR, vectype, - vec_init)); - vec_init = gimple_assign_lhs (new_stmt); - new_bb = gsi_insert_on_edge_immediate (loop_preheader_edge (iv_loop), - new_stmt); - gcc_assert (!new_bb); - } - } - else - { - /* iv_loop is the loop to be vectorized. Create: - vec_init = [X, X+S, X+2*S, X+3*S] (S = step_expr, X = init_expr) */ - stmts = NULL; - new_name = gimple_convert (&stmts, TREE_TYPE (step_expr), init_expr); + We should generate: - unsigned HOST_WIDE_INT const_nunits; - if (nunits.is_constant (&const_nunits)) - { - tree_vector_builder elts (step_vectype, const_nunits, 1); - elts.quick_push (new_name); - for (i = 1; i < const_nunits; i++) - { - /* Create: new_name_i = new_name + step_expr */ - new_name = gimple_build (&stmts, PLUS_EXPR, TREE_TYPE (new_name), - new_name, step_expr); - elts.quick_push (new_name); + _35 = .SELECT_VL (ivtmp_33, VF); + vect_cst__22 = [vec_duplicate_expr] _35; + _21 = vect_vec_iv_.6_22 + vect_cst__22; */ + vec_loop_lens *lens = &LOOP_VINFO_LENS (loop_vinfo); + tree len = vect_get_loop_len (loop_vinfo, NULL, lens, 1, + vectype, 0, 0); + if (SCALAR_FLOAT_TYPE_P (stept)) + expr = gimple_build (&stmts, FLOAT_EXPR, stept, len); + else + expr = gimple_convert (&stmts, stept, len); + lupdate_mul = gimple_build_vector_from_val (&stmts, step_vectype, + expr); + up = gimple_build (&stmts, MULT_EXPR, + step_vectype, vec_step, lupdate_mul); } - /* Create a vector from [new_name_0, new_name_1, ..., - new_name_nunits-1] */ - vec_init = gimple_build_vector (&stmts, &elts); - } - else if (INTEGRAL_TYPE_P (TREE_TYPE (step_expr))) - /* Build the initial value directly from a VEC_SERIES_EXPR. */ - vec_init = gimple_build (&stmts, VEC_SERIES_EXPR, step_vectype, - new_name, step_expr); - else - { - /* Build: - [base, base, base, ...] - + (vectype) [0, 1, 2, ...] * [step, step, step, ...]. */ - gcc_assert (SCALAR_FLOAT_TYPE_P (TREE_TYPE (step_expr))); - gcc_assert (flag_associative_math); - gcc_assert (index_vectype != NULL_TREE); - - tree index = build_index_vector (index_vectype, 0, 1); - tree base_vec = gimple_build_vector_from_val (&stmts, step_vectype, - new_name); - tree step_vec = gimple_build_vector_from_val (&stmts, step_vectype, - step_expr); - vec_init = gimple_build (&stmts, FLOAT_EXPR, step_vectype, index); - vec_init = gimple_build (&stmts, MULT_EXPR, step_vectype, - vec_init, step_vec); - vec_init = gimple_build (&stmts, PLUS_EXPR, step_vectype, - vec_init, base_vec); - } - vec_init = gimple_convert (&stmts, vectype, vec_init); + else + up = gimple_build (&init_stmts, MULT_EXPR, step_vectype, + vec_step, lupdate_mul); + } + vec_def = gimple_convert (&stmts, step_vectype, induc_def); + vec_def = gimple_build (&stmts, PLUS_EXPR, step_vectype, vec_def, up); + vec_def = gimple_convert (&stmts, vectype, vec_def); + insert_iv_increment (&incr_si, insert_after, stmts); + add_phi_arg (induction_phi, vec_def, loop_latch_edge (iv_loop), + UNKNOWN_LOCATION); - if (stmts) + if (init_node) + vec_init = vect_get_slp_vect_def (init_node, ivn); + if (!nested_in_vect_loop + && step_mul + && !integer_zerop (step_mul)) { - new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts); - gcc_assert (!new_bb); + gcc_assert (invariant); + vec_def = gimple_convert (&init_stmts, step_vectype, vec_init); + up = gimple_build (&init_stmts, MULT_EXPR, step_vectype, + vec_step, step_mul); + vec_def = gimple_build (&init_stmts, PLUS_EXPR, step_vectype, + vec_def, up); + vec_init = gimple_convert (&init_stmts, vectype, vec_def); } - } - - - /* Create the vector that holds the step of the induction. */ - gimple_stmt_iterator *step_iv_si = NULL; - if (nested_in_vect_loop) - /* iv_loop is nested in the loop to be vectorized. Generate: - vec_step = [S, S, S, S] */ - new_name = step_expr; - else if (LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo)) - { - /* When we're using loop_len produced by SELEC_VL, the non-final - iterations are not always processing VF elements. So vectorize - induction variable instead of - _21 = vect_vec_iv_.6_22 + { VF, ... }; + /* Set the arguments of the phi node: */ + add_phi_arg (induction_phi, vec_init, pe, UNKNOWN_LOCATION); - We should generate: - - _35 = .SELECT_VL (ivtmp_33, VF); - vect_cst__22 = [vec_duplicate_expr] _35; - _21 = vect_vec_iv_.6_22 + vect_cst__22; */ - gcc_assert (!slp_node); - gimple_seq seq = NULL; - vec_loop_lens *lens = &LOOP_VINFO_LENS (loop_vinfo); - tree len = vect_get_loop_len (loop_vinfo, NULL, lens, 1, vectype, 0, 0); - expr = force_gimple_operand (fold_convert (TREE_TYPE (step_expr), - unshare_expr (len)), - &seq, true, NULL_TREE); - new_name = gimple_build (&seq, MULT_EXPR, TREE_TYPE (step_expr), expr, - step_expr); - gsi_insert_seq_before (&si, seq, GSI_SAME_STMT); - step_iv_si = &si; + slp_node->push_vec_def (induction_phi); } - else + if (!nested_in_vect_loop) { - /* iv_loop is the loop to be vectorized. Generate: - vec_step = [VF*S, VF*S, VF*S, VF*S] */ - gimple_seq seq = NULL; - if (SCALAR_FLOAT_TYPE_P (TREE_TYPE (step_expr))) - { - expr = build_int_cst (integer_type_node, vf); - expr = gimple_build (&seq, FLOAT_EXPR, TREE_TYPE (step_expr), expr); - } + /* Fill up to the number of vectors we need for the whole group. */ + if (nunits.is_constant (&const_nunits)) + nivs = least_common_multiple (group_size, const_nunits) / const_nunits; else - expr = build_int_cst (TREE_TYPE (step_expr), vf); - new_name = gimple_build (&seq, MULT_EXPR, TREE_TYPE (step_expr), - expr, step_expr); - if (seq) + nivs = 1; + vec_steps.reserve (nivs-ivn); + for (; ivn < nivs; ++ivn) { - new_bb = gsi_insert_seq_on_edge_immediate (pe, seq); - gcc_assert (!new_bb); + slp_node->push_vec_def (SLP_TREE_VEC_DEFS (slp_node)[0]); + vec_steps.quick_push (vec_steps[0]); } } - t = unshare_expr (new_name); - gcc_assert (CONSTANT_CLASS_P (new_name) - || TREE_CODE (new_name) == SSA_NAME); - new_vec = build_vector_from_val (step_vectype, t); - vec_step = vect_init_vector (loop_vinfo, stmt_info, - new_vec, step_vectype, step_iv_si); - - - /* Create the following def-use cycle: - loop prolog: - vec_init = ... - vec_step = ... - loop: - vec_iv = PHI <vec_init, vec_loop> - ... - STMT - ... - vec_loop = vec_iv + vec_step; */ - - /* Create the induction-phi that defines the induction-operand. */ - vec_dest = vect_get_new_vect_var (vectype, vect_simple_var, "vec_iv_"); - induction_phi = create_phi_node (vec_dest, iv_loop->header); - induc_def = PHI_RESULT (induction_phi); - - /* Create the iv update inside the loop */ - stmts = NULL; - vec_def = gimple_convert (&stmts, step_vectype, induc_def); - vec_def = gimple_build (&stmts, PLUS_EXPR, step_vectype, vec_def, vec_step); - vec_def = gimple_convert (&stmts, vectype, vec_def); - gsi_insert_seq_before (&si, stmts, GSI_SAME_STMT); - new_stmt = SSA_NAME_DEF_STMT (vec_def); - - /* Set the arguments of the phi node: */ - add_phi_arg (induction_phi, vec_init, pe, UNKNOWN_LOCATION); - add_phi_arg (induction_phi, vec_def, loop_latch_edge (iv_loop), - UNKNOWN_LOCATION); - - STMT_VINFO_VEC_STMTS (stmt_info).safe_push (induction_phi); - *vec_stmt = induction_phi; - - /* In case that vectorization factor (VF) is bigger than the number - of elements that we can fit in a vectype (nunits), we have to generate - more than one vector stmt - i.e - we need to "unroll" the - vector stmt by a factor VF/nunits. For more details see documentation - in vectorizable_operation. */ - - if (ncopies > 1) + /* Re-use IVs when we can. We are generating further vector + stmts by adding VF' * stride to the IVs generated above. */ + if (ivn < nvects) { - gimple_seq seq = NULL; - /* FORNOW. This restriction should be relaxed. */ - gcc_assert (!nested_in_vect_loop); - /* We expect LOOP_VINFO_USING_SELECT_VL_P to be false if ncopies > 1. */ - gcc_assert (!LOOP_VINFO_USING_SELECT_VL_P (loop_vinfo)); - - /* Create the vector that holds the step of the induction. */ - if (SCALAR_FLOAT_TYPE_P (TREE_TYPE (step_expr))) + if (nunits.is_constant (&const_nunits)) { - expr = build_int_cst (integer_type_node, nunits); - expr = gimple_build (&seq, FLOAT_EXPR, TREE_TYPE (step_expr), expr); + unsigned vfp = (least_common_multiple (group_size, const_nunits) + / group_size); + lupdate_mul + = build_vector_from_val (step_vectype, + SCALAR_FLOAT_TYPE_P (stept) + ? build_real_from_wide (stept, + vfp, UNSIGNED) + : build_int_cstu (stept, vfp)); } else - expr = build_int_cst (TREE_TYPE (step_expr), nunits); - new_name = gimple_build (&seq, MULT_EXPR, TREE_TYPE (step_expr), - expr, step_expr); - if (seq) { - new_bb = gsi_insert_seq_on_edge_immediate (pe, seq); - gcc_assert (!new_bb); - } - - t = unshare_expr (new_name); - gcc_assert (CONSTANT_CLASS_P (new_name) - || TREE_CODE (new_name) == SSA_NAME); - new_vec = build_vector_from_val (step_vectype, t); - vec_step = vect_init_vector (loop_vinfo, stmt_info, - new_vec, step_vectype, NULL); - - vec_def = induc_def; - for (i = 1; i < ncopies + 1; i++) - { - /* vec_i = vec_prev + vec_step */ - gimple_seq stmts = NULL; - vec_def = gimple_convert (&stmts, step_vectype, vec_def); - vec_def = gimple_build (&stmts, - PLUS_EXPR, step_vectype, vec_def, vec_step); - vec_def = gimple_convert (&stmts, vectype, vec_def); - - gsi_insert_seq_before (&si, stmts, GSI_SAME_STMT); - if (i < ncopies) + if (SCALAR_FLOAT_TYPE_P (stept)) { - new_stmt = SSA_NAME_DEF_STMT (vec_def); - STMT_VINFO_VEC_STMTS (stmt_info).safe_push (new_stmt); + tree tem = build_int_cst (integer_type_node, nunits); + lupdate_mul = gimple_build (&init_stmts, FLOAT_EXPR, stept, tem); } else + lupdate_mul = build_int_cst (stept, nunits); + lupdate_mul = gimple_build_vector_from_val (&init_stmts, step_vectype, + lupdate_mul); + } + for (; ivn < nvects; ++ivn) + { + gimple *iv + = SSA_NAME_DEF_STMT (SLP_TREE_VEC_DEFS (slp_node)[ivn - nivs]); + tree def = gimple_get_lhs (iv); + if (ivn < 2*nivs) + vec_steps[ivn - nivs] + = gimple_build (&init_stmts, MULT_EXPR, step_vectype, + vec_steps[ivn - nivs], lupdate_mul); + gimple_seq stmts = NULL; + def = gimple_convert (&stmts, step_vectype, def); + def = gimple_build (&stmts, PLUS_EXPR, step_vectype, + def, vec_steps[ivn % nivs]); + def = gimple_convert (&stmts, vectype, def); + if (gimple_code (iv) == GIMPLE_PHI) + gsi_insert_seq_before (&si, stmts, GSI_SAME_STMT); + else { - /* vec_1 = vec_iv + (VF/n * S) - vec_2 = vec_1 + (VF/n * S) - ... - vec_n = vec_prev + (VF/n * S) = vec_iv + VF * S = vec_loop - - vec_n is used as vec_loop to save the large step register and - related operations. */ - add_phi_arg (induction_phi, vec_def, loop_latch_edge (iv_loop), - UNKNOWN_LOCATION); + gimple_stmt_iterator tgsi = gsi_for_stmt (iv); + gsi_insert_seq_after (&tgsi, stmts, GSI_CONTINUE_LINKING); } + slp_node->push_vec_def (def); } } - if (dump_enabled_p ()) - dump_printf_loc (MSG_NOTE, vect_location, - "transform induction: created def-use cycle: %G%G", - (gimple *) induction_phi, SSA_NAME_DEF_STMT (vec_def)); + new_bb = gsi_insert_seq_on_edge_immediate (pe, init_stmts); + gcc_assert (!new_bb); return true; } |