diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/s390/s390.h | 8 | ||||
| -rw-r--r-- | gcc/config/s390/s390.md | 56 |
3 files changed, 47 insertions, 26 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 48192ec..75bb642 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2003-08-23 Ulrich Weigand <uweigand@de.ibm.com> + + * config/s390/s390.h (LOAD_EXTEND_OP): Remove. + * config/s390/s390.md ("movhi"): New expander; old insn renamed to ... + ("*movhi"): ... this. + ("movqi", "*movqi"): Likewise. + ("movqi_64"): Remove. + ("*zero_extendhisi2_31"): Change predicate to s_operand. + 2003-08-23 Dale Johannesen <dalej@apple.com> * calls.c (emit_library_call_value_1): Fix obvious errors in arguments to emit_group_store. diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index 12bdb5f..1e8cfa9 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -1090,14 +1090,6 @@ extern int s390_nr_constants; tablejump instruction. */ #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) -/* Load from integral MODE < SI from memory into register makes sign_extend - or zero_extend - In our case sign_extension happens for Halfwords, other no extension. */ -#define LOAD_EXTEND_OP(MODE) \ -(TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \ - (MODE) == HImode ? SIGN_EXTEND : NIL) \ - : ((MODE) == HImode ? SIGN_EXTEND : NIL)) - /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 6bf46f8..a190bad 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -1295,7 +1295,25 @@ ; movhi instruction pattern(s). ; -(define_insn "movhi" +(define_expand "movhi" + [(set (match_operand:HI 0 "nonimmediate_operand" "") + (match_operand:HI 1 "general_operand" ""))] + "" +{ + /* Make it explicit that loading a register from memory + always sign-extends (at least) to SImode. */ + if (optimize && !no_new_pseudos + && register_operand (operands[0], VOIDmode) + && memory_operand (operands[1], VOIDmode)) + { + rtx tmp = gen_reg_rtx (SImode); + rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); + emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); + operands[1] = gen_lowpart (HImode, tmp); + } +}) + +(define_insn "*movhi" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] "" @@ -1324,23 +1342,25 @@ ; movqi instruction pattern(s). ; -(define_insn "movqi_64" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q") - (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))] - "TARGET_64BIT" - "@ - lr\t%0,%1 - lhi\t%0,%b1 - llgc\t%0,%1 - stc\t%1,%0 - stcy\t%1,%0 - mvi\t%0,%b1 - mviy\t%0,%b1 - mvc\t%O0(1,%R0),%1" - [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS") - (set_attr "type" "lr,*,*,store,store,store,store,cs")]) +(define_expand "movqi" + [(set (match_operand:QI 0 "nonimmediate_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" +{ + /* On 64-bit, zero-extending from memory to register + is just as fast as a QImode load. */ + if (TARGET_64BIT && optimize && !no_new_pseudos + && register_operand (operands[0], VOIDmode) + && memory_operand (operands[1], VOIDmode)) + { + rtx tmp = gen_reg_rtx (DImode); + rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); + emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); + operands[1] = gen_lowpart (QImode, tmp); + } +}) -(define_insn "movqi" +(define_insn "*movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] "" @@ -2478,7 +2498,7 @@ (define_insn_and_split "*zero_extendhisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") - (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS"))) + (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) (clobber (reg:CC 33))] "!TARGET_64BIT" "#" |