diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 40 | ||||
| -rw-r--r-- | gcc/config/i386/i386-modes.def | 1 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 17 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 13 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 66 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 133 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr32280-1.c | 18 |
8 files changed, 180 insertions, 113 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fce7c7c..47731da 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,43 @@ +2009-12-17 Uros Bizjak <ubizjak@gmail.com> + + PR target/32280 + * config/i386/i386-modes.def (V1TI): New vector mode. + * config/i386/i386.h (VALID_SSE_REG_MODE): Add V1TImode. + (SSE_REG_MODE_P): Ditto. + * config/i386/sse.md (SSEMODE16): New mode iterator. + (AVXMODE16): Ditto. + (avxvecmode): Handle V1TI mode. + (*avx_mov<mode>_internal): Use AVXMODE16 instead of AVXMODE. + (mov<mode>): Use SSEMODE16 instead of SSEMODE. + (*mov<mode>_internal): Ditto. + (push<mode>1): Ditto. + (movmisalign<mode>): Ditto. + (sse2_ashlv1ti): Rename from sse2_ashlti. + (sse2_lshrv1ti): Rename from sse2_lshrti. + (*avx_ashlv1ti): Rename from *avx_ashlti and move from i386.md. + (*avx_lshrv1ti): Rename from *avx_lshrti and move from i386.md. + (vec_shl_<mode>): Convert operands to V1TImode and use V1TI shift. + (vec_shr_<mode>): Ditto. + (*sse2_mulv4si3): Update for renamed sse2_ashlv1ti3. + (udot_prodv4si): Ditto. + * config/i386/i386.c (classify_argument): Handle V1TImode. + (function_arg_advance_32): Ditto. + (function_arg_32): Ditto. + (ix86_expand_sse4_unpack): Convert operands to V1TImode and update + for renamed gen_sse2_lshrv1ti3. + (ix86_expand_args_builtin) <V2DI_FTYPE_V2DI_INT_CONVERT>: Set rmode + to V1TImode. + (struct builtin_description) <__builtin_ia32_pslldqi128>: Update + for renamed sse2_ashlv1ti3. + <__builtin_ia32_psrldqi128>: Update for renamed sse2_lshrv1ti3. + + Revert: + 2007-06-11 Uros Bizjak <ubizjak@gmail.com> + + PR target/32280 + * config/i386/sse.md ("sse2_ashlti", "sse2_lshrti3"): Move ... + * config/i386/i386.md ("sse2_ashlti", "sse2_lshrti3"): ... to here. + 2009-12-17 Richard Earnshaw <rearnsha@arm.com> PR target/42372 diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def index f2e06ee..c1e82cc 100644 --- a/gcc/config/i386/i386-modes.def +++ b/gcc/config/i386/i386-modes.def @@ -80,6 +80,7 @@ VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ VECTOR_MODES (FLOAT, 64); /* V32HF V16SF V8DF */ +VECTOR_MODE (INT, TI, 1); /* V1TI */ VECTOR_MODE (INT, DI, 1); /* V1DI */ VECTOR_MODE (INT, SI, 1); /* V1SI */ VECTOR_MODE (INT, QI, 2); /* V2QI */ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 281bd41..dfe12de 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -5346,7 +5346,7 @@ classify_argument (enum machine_mode mode, const_tree type, } /* for V1xx modes, just use the base mode */ - if (VECTOR_MODE_P (mode) && mode != V1DImode + if (VECTOR_MODE_P (mode) && mode != V1DImode && mode != V1TImode && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes) mode = GET_MODE_INNER (mode); @@ -5470,6 +5470,7 @@ classify_argument (enum machine_mode mode, const_tree type, classes[0] = X86_64_SSE_CLASS; classes[1] = X86_64_SSEUP_CLASS; return 2; + case V1TImode: case V1DImode: case V2SFmode: case V2SImode: @@ -5814,6 +5815,7 @@ function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode, case V4HImode: case V2SImode: case V2SFmode: + case V1TImode: case V1DImode: if (!type || !AGGREGATE_TYPE_P (type)) { @@ -6001,6 +6003,7 @@ function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode, case V4HImode: case V2SImode: case V2SFmode: + case V1TImode: case V1DImode: if (!type || !AGGREGATE_TYPE_P (type)) { @@ -16391,9 +16394,9 @@ ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p) { /* Shift higher 8 bytes to lower 8 bytes. */ src = gen_reg_rtx (imode); - emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src), - gen_lowpart (TImode, operands[1]), - GEN_INT (64))); + emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, src), + gen_lowpart (V1TImode, operands[1]), + GEN_INT (64))); } else src = operands[1]; @@ -21886,7 +21889,7 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT }, + { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT }, { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT }, { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT }, { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT }, @@ -21894,7 +21897,7 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT }, { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT }, + { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT }, { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT }, { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT }, { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT }, @@ -23492,7 +23495,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, break; case V2DI_FTYPE_V2DI_INT_CONVERT: nargs = 2; - rmode = V2DImode; + rmode = V1TImode; nargs_constant = 1; break; case V8HI_FTYPE_V8HI_INT: diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 860d234..962a14c 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1013,7 +1013,8 @@ enum target_cpu_default || (MODE) == V2DImode || (MODE) == DFmode) #define VALID_SSE_REG_MODE(MODE) \ - ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ + ((MODE) == V1TImode || (MODE) == TImode \ + || (MODE) == V4SFmode || (MODE) == V4SImode \ || (MODE) == SFmode || (MODE) == TFmode) #define VALID_MMX_REG_MODE_3DNOW(MODE) \ @@ -1051,11 +1052,11 @@ enum target_cpu_default /* Return true for modes passed in SSE registers. */ #define SSE_REG_MODE_P(MODE) \ - ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ - || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ - || (MODE) == V4SFmode || (MODE) == V4SImode || (MODE) == V32QImode \ - || (MODE) == V16HImode || (MODE) == V8SImode || (MODE) == V4DImode \ - || (MODE) == V8SFmode || (MODE) == V4DFmode) + ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ + || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ + || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ + || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ + || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 22e6049..b4a8a83 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -717,10 +717,8 @@ (umax "maxu") (umin "minu")]) (define_code_attr maxminfprefix [(smax "max") (smin "min")]) -;; Mapping of parallel logic operators +;; Mapping of logic operators (define_code_iterator any_logic [and ior xor]) - -;; Mapping of parallel logic operators (define_code_iterator any_or [ior xor]) ;; Base name for insn mnemonic. @@ -9680,37 +9678,6 @@ "TARGET_64BIT" "ix86_expand_binary_operator (ASHIFT, TImode, operands); DONE;") -;; This pattern must be defined before *ashlti3_1 to prevent -;; combine pass from converting sse2_ashlti3 to *ashlti3_1. - -(define_insn "*avx_ashlti3" - [(set (match_operand:TI 0 "register_operand" "=x") - (ashift:TI (match_operand:TI 1 "register_operand" "x") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] - "TARGET_AVX" -{ - operands[2] = GEN_INT (INTVAL (operands[2]) / 8); - return "vpslldq\t{%2, %1, %0|%0, %1, %2}"; -} - [(set_attr "type" "sseishft") - (set_attr "prefix" "vex") - (set_attr "length_immediate" "1") - (set_attr "mode" "TI")]) - -(define_insn "sse2_ashlti3" - [(set (match_operand:TI 0 "register_operand" "=x") - (ashift:TI (match_operand:TI 1 "register_operand" "0") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] - "TARGET_SSE2" -{ - operands[2] = GEN_INT (INTVAL (operands[2]) / 8); - return "pslldq\t{%2, %0|%0, %2}"; -} - [(set_attr "type" "sseishft") - (set_attr "prefix_data16" "1") - (set_attr "length_immediate" "1") - (set_attr "mode" "TI")]) - (define_insn "*ashlti3_1" [(set (match_operand:TI 0 "register_operand" "=&r,r") (ashift:TI (match_operand:TI 1 "reg_or_pm1_operand" "n,0") @@ -11534,37 +11501,6 @@ "TARGET_64BIT" "ix86_expand_binary_operator (LSHIFTRT, TImode, operands); DONE;") -;; This pattern must be defined before *lshrti3_1 to prevent -;; combine pass from converting sse2_lshrti3 to *lshrti3_1. - -(define_insn "*avx_lshrti3" - [(set (match_operand:TI 0 "register_operand" "=x") - (lshiftrt:TI (match_operand:TI 1 "register_operand" "x") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] - "TARGET_AVX" -{ - operands[2] = GEN_INT (INTVAL (operands[2]) / 8); - return "vpsrldq\t{%2, %1, %0|%0, %1, %2}"; -} - [(set_attr "type" "sseishft") - (set_attr "prefix" "vex") - (set_attr "length_immediate" "1") - (set_attr "mode" "TI")]) - -(define_insn "sse2_lshrti3" - [(set (match_operand:TI 0 "register_operand" "=x") - (lshiftrt:TI (match_operand:TI 1 "register_operand" "0") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] - "TARGET_SSE2" -{ - operands[2] = GEN_INT (INTVAL (operands[2]) / 8); - return "psrldq\t{%2, %0|%0, %2}"; -} - [(set_attr "type" "sseishft") - (set_attr "prefix_data16" "1") - (set_attr "length_immediate" "1") - (set_attr "mode" "TI")]) - (define_insn "*lshrti3_1" [(set (match_operand:TI 0 "register_operand" "=r") (lshiftrt:TI (match_operand:TI 1 "register_operand" "0") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 24d6635..9bbea80 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -19,12 +19,12 @@ ;; <http://www.gnu.org/licenses/>. -;; 16 byte integral modes handled by SSE, minus TImode, which gets -;; special-cased for TARGET_64BIT. +;; 16 byte integral modes handled by SSE (define_mode_iterator SSEMODEI [V16QI V8HI V4SI V2DI]) ;; All 16-byte vector modes handled by SSE (define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF]) +(define_mode_iterator SSEMODE16 [V16QI V8HI V4SI V2DI V1TI V4SF V2DF]) ;; 32 byte integral vector modes handled by AVX (define_mode_iterator AVX256MODEI [V32QI V16HI V8SI V4DI]) @@ -39,7 +39,10 @@ (define_mode_iterator AVXMODEDI [V4DI V2DI]) ;; All vector modes handled by AVX -(define_mode_iterator AVXMODE [V16QI V8HI V4SI V2DI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF]) +(define_mode_iterator AVXMODE + [V16QI V8HI V4SI V2DI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF]) +(define_mode_iterator AVXMODE16 + [V16QI V8HI V4SI V2DI V1TI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF]) ;; Mix-n-match (define_mode_iterator SSEMODE12 [V16QI V8HI]) @@ -121,9 +124,9 @@ ;; Mapping for AVX (define_mode_attr avxvecmode - [(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V4SF "V4SF") - (V2DF "V2DF") (V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI") - (V8SF "V8SF") (V4DF "V4DF")]) + [(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI") + (V4SF "V4SF") (V8SF "V8SF") (V2DF "V2DF") (V4DF "V4DF") + (V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")]) (define_mode_attr avxvecpsmode [(V16QI "V4SF") (V8HI "V4SF") (V4SI "V4SF") (V2DI "V4SF") (V32QI "V8SF") (V16HI "V8SF") (V8SI "V8SF") (V4DI "V8SF")]) @@ -172,8 +175,8 @@ }) (define_insn "*avx_mov<mode>_internal" - [(set (match_operand:AVXMODE 0 "nonimmediate_operand" "=x,x ,m") - (match_operand:AVXMODE 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))] + [(set (match_operand:AVXMODE16 0 "nonimmediate_operand" "=x,x ,m") + (match_operand:AVXMODE16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))] "TARGET_AVX && (register_operand (operands[0], <MODE>mode) || register_operand (operands[1], <MODE>mode))" @@ -207,8 +210,8 @@ ;; This is essential for maintaining stable calling conventions. (define_expand "mov<mode>" - [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "") - (match_operand:SSEMODE 1 "nonimmediate_operand" ""))] + [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "") + (match_operand:SSEMODE16 1 "nonimmediate_operand" ""))] "TARGET_SSE" { ix86_expand_vector_move (<MODE>mode, operands); @@ -216,8 +219,8 @@ }) (define_insn "*mov<mode>_internal" - [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "=x,x ,m") - (match_operand:SSEMODE 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))] + [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "=x,x ,m") + (match_operand:SSEMODE16 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))] "TARGET_SSE && (register_operand (operands[0], <MODE>mode) || register_operand (operands[1], <MODE>mode))" @@ -326,7 +329,7 @@ }) (define_expand "push<mode>1" - [(match_operand:SSEMODE 0 "register_operand" "")] + [(match_operand:SSEMODE16 0 "register_operand" "")] "TARGET_SSE" { ix86_expand_push (<MODE>mode, operands[0]); @@ -343,8 +346,8 @@ }) (define_expand "movmisalign<mode>" - [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "") - (match_operand:SSEMODE 1 "nonimmediate_operand" ""))] + [(set (match_operand:SSEMODE16 0 "nonimmediate_operand" "") + (match_operand:SSEMODE16 1 "nonimmediate_operand" ""))] "TARGET_SSE" { ix86_expand_vector_move_misalign (<MODE>mode, operands); @@ -5537,12 +5540,12 @@ /* Shift both input vectors down one element, so that elements 3 and 1 are now in the slots for elements 2 and 0. For K8, at least, this is faster than using a shuffle. */ - emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t2), - gen_lowpart (TImode, op1), - thirtytwo)); - emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t3), - gen_lowpart (TImode, op2), - thirtytwo)); + emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t2), + gen_lowpart (V1TImode, op1), + thirtytwo)); + emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t3), + gen_lowpart (V1TImode, op2), + thirtytwo)); /* Multiply elements 3 and 1. */ emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t4), t2, t3)); @@ -5837,12 +5840,12 @@ t2 = gen_reg_rtx (V4SImode); t3 = gen_reg_rtx (V4SImode); - emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t2), - gen_lowpart (TImode, operands[1]), - GEN_INT (32))); - emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t3), - gen_lowpart (TImode, operands[2]), - GEN_INT (32))); + emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t2), + gen_lowpart (V1TImode, operands[1]), + GEN_INT (32))); + emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t3), + gen_lowpart (V1TImode, operands[2]), + GEN_INT (32))); t4 = gen_reg_rtx (V2DImode); emit_insn (gen_sse2_umulv2siv2di3 (t4, t2, t3)); @@ -5881,6 +5884,21 @@ (const_string "0"))) (set_attr "mode" "TI")]) +(define_insn "*avx_lshrv1ti3" + [(set (match_operand:V1TI 0 "register_operand" "=x") + (lshiftrt:V1TI + (match_operand:V1TI 1 "register_operand" "x") + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] + "TARGET_AVX" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) / 8); + return "vpsrldq\t{%2, %1, %0|%0, %1, %2}"; +} + [(set_attr "type" "sseishft") + (set_attr "prefix" "vex") + (set_attr "length_immediate" "1") + (set_attr "mode" "TI")]) + (define_insn "*avx_lshr<mode>3" [(set (match_operand:SSEMODE248 0 "register_operand" "=x") (lshiftrt:SSEMODE248 @@ -5896,6 +5914,21 @@ (const_string "0"))) (set_attr "mode" "TI")]) +(define_insn "sse2_lshrv1ti3" + [(set (match_operand:V1TI 0 "register_operand" "=x") + (lshiftrt:V1TI + (match_operand:V1TI 1 "register_operand" "0") + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] + "TARGET_SSE2" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) / 8); + return "psrldq\t{%2, %0|%0, %2}"; +} + [(set_attr "type" "sseishft") + (set_attr "prefix_data16" "1") + (set_attr "length_immediate" "1") + (set_attr "mode" "TI")]) + (define_insn "lshr<mode>3" [(set (match_operand:SSEMODE248 0 "register_operand" "=x") (lshiftrt:SSEMODE248 @@ -5911,6 +5944,20 @@ (const_string "0"))) (set_attr "mode" "TI")]) +(define_insn "*avx_ashlv1ti3" + [(set (match_operand:V1TI 0 "register_operand" "=x") + (ashift:V1TI (match_operand:V1TI 1 "register_operand" "x") + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] + "TARGET_AVX" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) / 8); + return "vpslldq\t{%2, %1, %0|%0, %1, %2}"; +} + [(set_attr "type" "sseishft") + (set_attr "prefix" "vex") + (set_attr "length_immediate" "1") + (set_attr "mode" "TI")]) + (define_insn "*avx_ashl<mode>3" [(set (match_operand:SSEMODE248 0 "register_operand" "=x") (ashift:SSEMODE248 @@ -5926,6 +5973,20 @@ (const_string "0"))) (set_attr "mode" "TI")]) +(define_insn "sse2_ashlv1ti3" + [(set (match_operand:V1TI 0 "register_operand" "=x") + (ashift:V1TI (match_operand:V1TI 1 "register_operand" "0") + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] + "TARGET_SSE2" +{ + operands[2] = GEN_INT (INTVAL (operands[2]) / 8); + return "pslldq\t{%2, %0|%0, %2}"; +} + [(set_attr "type" "sseishft") + (set_attr "prefix_data16" "1") + (set_attr "length_immediate" "1") + (set_attr "mode" "TI")]) + (define_insn "ashl<mode>3" [(set (match_operand:SSEMODE248 0 "register_operand" "=x") (ashift:SSEMODE248 @@ -5943,22 +6004,24 @@ (define_expand "vec_shl_<mode>" [(set (match_operand:SSEMODEI 0 "register_operand" "") - (ashift:TI (match_operand:SSEMODEI 1 "register_operand" "") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))] + (ashift:V1TI + (match_operand:SSEMODEI 1 "register_operand" "") + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))] "TARGET_SSE2" { - operands[0] = gen_lowpart (TImode, operands[0]); - operands[1] = gen_lowpart (TImode, operands[1]); + operands[0] = gen_lowpart (V1TImode, operands[0]); + operands[1] = gen_lowpart (V1TImode, operands[1]); }) (define_expand "vec_shr_<mode>" [(set (match_operand:SSEMODEI 0 "register_operand" "") - (lshiftrt:TI (match_operand:SSEMODEI 1 "register_operand" "") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))] + (lshiftrt:V1TI + (match_operand:SSEMODEI 1 "register_operand" "") + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))] "TARGET_SSE2" { - operands[0] = gen_lowpart (TImode, operands[0]); - operands[1] = gen_lowpart (TImode, operands[1]); + operands[0] = gen_lowpart (V1TImode, operands[0]); + operands[1] = gen_lowpart (V1TImode, operands[1]); }) (define_insn "*avx_<code><mode>3" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e523a3d..5de2902 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2009-12-17 Uros Bizjak <ubizjak@gmail.com> + PR target/32280 + * gcc.target/i386/pr32280-1.c: New test. + +2009-12-17 Uros Bizjak <ubizjak@gmail.com> + * objc/execute/forward-1.x: XFAIL for -fgnu-runtime on x86_64-*-darwin*, powerpc*-*-darwin* and alpha*-*-linux* targets. diff --git a/gcc/testsuite/gcc.target/i386/pr32280-1.c b/gcc/testsuite/gcc.target/i386/pr32280-1.c new file mode 100644 index 0000000..1dbe2cc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr32280-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +__uint128_t +t1 (__uint128_t a) +{ + return a << 8; +} + +__uint128_t +t2 (__uint128_t a) +{ + return a >> 8; +} + +/* { dg-final { scan-assembler-not "pslldq" } } */ +/* { dg-final { scan-assembler-not "psrldq" } } */ |