diff options
Diffstat (limited to 'gcc')
39 files changed, 124 insertions, 562 deletions
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index ea72c9c..204910d 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -55,32 +55,36 @@ #define __CR6_LT 2 #define __CR6_LT_REV 3 -/* Synonyms. */ +#include "rs6000-vecdefines.h" + +/* Deprecated interfaces. */ +#define vec_lvx vec_ld +#define vec_lvxl vec_ldl +#define vec_stvx vec_st +#define vec_stvxl vec_stl #define vec_vaddcuw vec_addc #define vec_vand vec_and #define vec_vandc vec_andc -#define vec_vrfip vec_ceil #define vec_vcmpbfp vec_cmpb #define vec_vcmpgefp vec_cmpge #define vec_vctsxs vec_cts #define vec_vctuxs vec_ctu #define vec_vexptefp vec_expte -#define vec_vrfim vec_floor -#define vec_lvx vec_ld -#define vec_lvxl vec_ldl #define vec_vlogefp vec_loge #define vec_vmaddfp vec_madd #define vec_vmhaddshs vec_madds -#define vec_vmladduhm vec_mladd #define vec_vmhraddshs vec_mradds +#define vec_vmladduhm vec_mladd #define vec_vnmsubfp vec_nmsub #define vec_vnor vec_nor #define vec_vor vec_or -#define vec_vpkpx vec_packpx #define vec_vperm vec_perm -#define vec_permxor __builtin_vec_vpermxor +#define vec_vpkpx vec_packpx #define vec_vrefp vec_re +#define vec_vrfim vec_floor #define vec_vrfin vec_round +#define vec_vrfip vec_ceil +#define vec_vrfiz vec_trunc #define vec_vrsqrtefp vec_rsqrte #define vec_vsel vec_sel #define vec_vsldoi vec_sld @@ -91,440 +95,54 @@ #define vec_vspltisw vec_splat_s32 #define vec_vsr vec_srl #define vec_vsro vec_sro -#define vec_stvx vec_st -#define vec_stvxl vec_stl #define vec_vsubcuw vec_subc #define vec_vsum2sws vec_sum2s #define vec_vsumsws vec_sums -#define vec_vrfiz vec_trunc #define vec_vxor vec_xor +/* For _ARCH_PWR8. Always define to support #pragma GCC target. */ +#define vec_vclz vec_cntlz +#define vec_vgbbd vec_gb +#define vec_vmrgew vec_mergee +#define vec_vmrgow vec_mergeo +#define vec_vpopcntu vec_popcnt +#define vec_vrld vec_rl +#define vec_vsld vec_sl +#define vec_vsrd vec_sr +#define vec_vsrad vec_sra + +/* For _ARCH_PWR9. Always define to support #pragma GCC target. */ +#define vec_extract_fp_from_shorth vec_extract_fp32_from_shorth +#define vec_extract_fp_from_shortl vec_extract_fp32_from_shortl +#define vec_vctz vec_cnttz + +/* Synonyms. */ /* Functions that are resolved by the backend to one of the typed builtins. */ -#define vec_vaddfp __builtin_vec_vaddfp -#define vec_addc __builtin_vec_addc -#define vec_adde __builtin_vec_adde -#define vec_addec __builtin_vec_addec -#define vec_vaddsws __builtin_vec_vaddsws -#define vec_vaddshs __builtin_vec_vaddshs -#define vec_vaddsbs __builtin_vec_vaddsbs -#define vec_vavgsw __builtin_vec_vavgsw -#define vec_vavguw __builtin_vec_vavguw -#define vec_vavgsh __builtin_vec_vavgsh -#define vec_vavguh __builtin_vec_vavguh -#define vec_vavgsb __builtin_vec_vavgsb -#define vec_vavgub __builtin_vec_vavgub -#define vec_ceil __builtin_vec_ceil -#define vec_cmpb __builtin_vec_cmpb -#define vec_vcmpeqfp __builtin_vec_vcmpeqfp -#define vec_cmpge __builtin_vec_cmpge -#define vec_vcmpgtfp __builtin_vec_vcmpgtfp -#define vec_vcmpgtsw __builtin_vec_vcmpgtsw -#define vec_vcmpgtuw __builtin_vec_vcmpgtuw -#define vec_vcmpgtsh __builtin_vec_vcmpgtsh -#define vec_vcmpgtuh __builtin_vec_vcmpgtuh -#define vec_vcmpgtsb __builtin_vec_vcmpgtsb -#define vec_vcmpgtub __builtin_vec_vcmpgtub -#define vec_vcfsx __builtin_vec_vcfsx -#define vec_vcfux __builtin_vec_vcfux -#define vec_cts __builtin_vec_cts -#define vec_ctu __builtin_vec_ctu #define vec_cpsgn(x,y) __builtin_vec_copysign(y,x) -#define vec_double __builtin_vec_double -#define vec_doublee __builtin_vec_doublee -#define vec_doubleo __builtin_vec_doubleo -#define vec_doublel __builtin_vec_doublel -#define vec_doubleh __builtin_vec_doubleh -#define vec_expte __builtin_vec_expte -#define vec_float __builtin_vec_float -#define vec_float2 __builtin_vec_float2 -#define vec_floate __builtin_vec_floate -#define vec_floato __builtin_vec_floato -#define vec_floor __builtin_vec_floor -#define vec_loge __builtin_vec_loge -#define vec_madd __builtin_vec_madd -#define vec_madds __builtin_vec_madds -#define vec_mtvscr __builtin_vec_mtvscr -#define vec_reve __builtin_vec_vreve -#define vec_vmaxfp __builtin_vec_vmaxfp -#define vec_vmaxsw __builtin_vec_vmaxsw -#define vec_vmaxsh __builtin_vec_vmaxsh -#define vec_vmaxsb __builtin_vec_vmaxsb -#define vec_vminfp __builtin_vec_vminfp -#define vec_vminsw __builtin_vec_vminsw -#define vec_vminsh __builtin_vec_vminsh -#define vec_vminsb __builtin_vec_vminsb -#define vec_mradds __builtin_vec_mradds -#define vec_vmsumshm __builtin_vec_vmsumshm -#define vec_vmsumuhm __builtin_vec_vmsumuhm -#define vec_vmsummbm __builtin_vec_vmsummbm -#define vec_vmsumubm __builtin_vec_vmsumubm -#define vec_vmsumshs __builtin_vec_vmsumshs -#define vec_vmsumuhs __builtin_vec_vmsumuhs -#define vec_vmsumudm __builtin_vec_vmsumudm -#define vec_vmulesb __builtin_vec_vmulesb -#define vec_vmulesh __builtin_vec_vmulesh -#define vec_vmuleuh __builtin_vec_vmuleuh -#define vec_vmuleub __builtin_vec_vmuleub -#define vec_vmulosh __builtin_vec_vmulosh -#define vec_vmulouh __builtin_vec_vmulouh -#define vec_vmulosb __builtin_vec_vmulosb -#define vec_vmuloub __builtin_vec_vmuloub -#define vec_nmsub __builtin_vec_nmsub -#define vec_packpx __builtin_vec_packpx -#define vec_vpkswss __builtin_vec_vpkswss -#define vec_vpkuwus __builtin_vec_vpkuwus -#define vec_vpkshss __builtin_vec_vpkshss -#define vec_vpkuhus __builtin_vec_vpkuhus -#define vec_vpkswus __builtin_vec_vpkswus -#define vec_vpkshus __builtin_vec_vpkshus -#define vec_re __builtin_vec_re -#define vec_round __builtin_vec_round -#define vec_recipdiv __builtin_vec_recipdiv -#define vec_rlmi __builtin_vec_rlmi -#define vec_vrlnm __builtin_vec_rlnm #define vec_rlnm(a,b,c) (__builtin_vec_rlnm((a),((c)<<8)|(b))) -#define vec_rsqrt __builtin_vec_rsqrt -#define vec_rsqrte __builtin_vec_rsqrte -#define vec_signed __builtin_vec_vsigned -#define vec_signed2 __builtin_vec_vsigned2 -#define vec_signede __builtin_vec_vsignede -#define vec_signedo __builtin_vec_vsignedo -#define vec_unsigned __builtin_vec_vunsigned -#define vec_unsigned2 __builtin_vec_vunsigned2 -#define vec_unsignede __builtin_vec_vunsignede -#define vec_unsignedo __builtin_vec_vunsignedo -#define vec_vsubfp __builtin_vec_vsubfp -#define vec_subc __builtin_vec_subc -#define vec_sube __builtin_vec_sube -#define vec_subec __builtin_vec_subec -#define vec_vsubsws __builtin_vec_vsubsws -#define vec_vsubshs __builtin_vec_vsubshs -#define vec_vsubsbs __builtin_vec_vsubsbs -#define vec_sum4s __builtin_vec_sum4s -#define vec_vsum4shs __builtin_vec_vsum4shs -#define vec_vsum4sbs __builtin_vec_vsum4sbs -#define vec_vsum4ubs __builtin_vec_vsum4ubs -#define vec_sum2s __builtin_vec_sum2s -#define vec_sums __builtin_vec_sums -#define vec_trunc __builtin_vec_trunc -#define vec_vupkhpx __builtin_vec_vupkhpx -#define vec_vupkhsh __builtin_vec_vupkhsh -#define vec_vupkhsb __builtin_vec_vupkhsb -#define vec_vupklpx __builtin_vec_vupklpx -#define vec_vupklsh __builtin_vec_vupklsh -#define vec_vupklsb __builtin_vec_vupklsb -#define vec_abs __builtin_vec_abs -#define vec_nabs __builtin_vec_nabs -#define vec_abss __builtin_vec_abss -#define vec_add __builtin_vec_add -#define vec_adds __builtin_vec_adds -#define vec_and __builtin_vec_and -#define vec_andc __builtin_vec_andc -#define vec_avg __builtin_vec_avg -#define vec_cmpeq __builtin_vec_cmpeq -#define vec_cmpne __builtin_vec_cmpne -#define vec_cmpgt __builtin_vec_cmpgt -#define vec_ctf __builtin_vec_ctf -#define vec_dst __builtin_vec_dst -#define vec_dstst __builtin_vec_dstst -#define vec_dststt __builtin_vec_dststt -#define vec_dstt __builtin_vec_dstt -#define vec_ld __builtin_vec_ld -#define vec_lde __builtin_vec_lde -#define vec_ldl __builtin_vec_ldl -#define vec_lvebx __builtin_vec_lvebx -#define vec_lvehx __builtin_vec_lvehx -#define vec_lvewx __builtin_vec_lvewx -#define vec_xl_zext __builtin_vec_ze_lxvrx -#define vec_xl_sext __builtin_vec_se_lxvrx -#define vec_xst_trunc __builtin_vec_tr_stxvrx -#define vec_neg __builtin_vec_neg -#define vec_pmsum_be __builtin_vec_vpmsum -#define vec_shasigma_be __builtin_crypto_vshasigma -/* Cell only intrinsics. */ -#ifdef __PPU__ -#define vec_lvlx __builtin_vec_lvlx -#define vec_lvlxl __builtin_vec_lvlxl -#define vec_lvrx __builtin_vec_lvrx -#define vec_lvrxl __builtin_vec_lvrxl -#endif -#define vec_lvsl __builtin_vec_lvsl -#define vec_lvsr __builtin_vec_lvsr -#define vec_max __builtin_vec_max -#define vec_mergee __builtin_vec_vmrgew -#define vec_mergeh __builtin_vec_mergeh -#define vec_mergel __builtin_vec_mergel -#define vec_mergeo __builtin_vec_vmrgow -#define vec_min __builtin_vec_min -#define vec_mladd __builtin_vec_mladd -#define vec_msum __builtin_vec_msum -#define vec_msums __builtin_vec_msums -#define vec_mul __builtin_vec_mul -#define vec_mule __builtin_vec_mule -#define vec_mulo __builtin_vec_mulo -#define vec_nor __builtin_vec_nor -#define vec_or __builtin_vec_or -#define vec_pack __builtin_vec_pack -#define vec_packs __builtin_vec_packs -#define vec_packsu __builtin_vec_packsu -#define vec_perm __builtin_vec_perm -#define vec_rl __builtin_vec_rl -#define vec_sel __builtin_vec_sel -#define vec_sl __builtin_vec_sl -#define vec_sld __builtin_vec_sld -#define vec_sldw __builtin_vsx_xxsldwi -#define vec_sll __builtin_vec_sll -#define vec_slo __builtin_vec_slo -#define vec_splat __builtin_vec_splat -#define vec_sr __builtin_vec_sr -#define vec_sra __builtin_vec_sra -#define vec_srl __builtin_vec_srl -#define vec_sro __builtin_vec_sro -#define vec_st __builtin_vec_st -#define vec_ste __builtin_vec_ste -#define vec_stl __builtin_vec_stl -#define vec_stvebx __builtin_vec_stvebx -#define vec_stvehx __builtin_vec_stvehx -#define vec_stvewx __builtin_vec_stvewx -/* Cell only intrinsics. */ -#ifdef __PPU__ -#define vec_stvlx __builtin_vec_stvlx -#define vec_stvlxl __builtin_vec_stvlxl -#define vec_stvrx __builtin_vec_stvrx -#define vec_stvrxl __builtin_vec_stvrxl -#endif -#define vec_sub __builtin_vec_sub -#define vec_subs __builtin_vec_subs -#define vec_sum __builtin_vec_sum -#define vec_unpackh __builtin_vec_unpackh -#define vec_unpackl __builtin_vec_unpackl -#define vec_vaddubm __builtin_vec_vaddubm -#define vec_vaddubs __builtin_vec_vaddubs -#define vec_vadduhm __builtin_vec_vadduhm -#define vec_vadduhs __builtin_vec_vadduhs -#define vec_vadduwm __builtin_vec_vadduwm -#define vec_vadduws __builtin_vec_vadduws -#define vec_vcmpequb __builtin_vec_vcmpequb -#define vec_vcmpequh __builtin_vec_vcmpequh -#define vec_vcmpequw __builtin_vec_vcmpequw -#define vec_vmaxub __builtin_vec_vmaxub -#define vec_vmaxuh __builtin_vec_vmaxuh -#define vec_vmaxuw __builtin_vec_vmaxuw -#define vec_vminub __builtin_vec_vminub -#define vec_vminuh __builtin_vec_vminuh -#define vec_vminuw __builtin_vec_vminuw -#define vec_vmrghb __builtin_vec_vmrghb -#define vec_vmrghh __builtin_vec_vmrghh -#define vec_vmrghw __builtin_vec_vmrghw -#define vec_vmrglb __builtin_vec_vmrglb -#define vec_vmrglh __builtin_vec_vmrglh -#define vec_vmrglw __builtin_vec_vmrglw -#define vec_vpkuhum __builtin_vec_vpkuhum -#define vec_vpkuwum __builtin_vec_vpkuwum -#define vec_vrlb __builtin_vec_vrlb -#define vec_vrlh __builtin_vec_vrlh -#define vec_vrlw __builtin_vec_vrlw -#define vec_vslb __builtin_vec_vslb -#define vec_vslh __builtin_vec_vslh -#define vec_vslw __builtin_vec_vslw -#define vec_vspltb __builtin_vec_vspltb -#define vec_vsplth __builtin_vec_vsplth -#define vec_vspltw __builtin_vec_vspltw -#define vec_vsrab __builtin_vec_vsrab -#define vec_vsrah __builtin_vec_vsrah -#define vec_vsraw __builtin_vec_vsraw -#define vec_vsrb __builtin_vec_vsrb -#define vec_vsrh __builtin_vec_vsrh -#define vec_vsrw __builtin_vec_vsrw -#define vec_vsububs __builtin_vec_vsububs -#define vec_vsububm __builtin_vec_vsububm -#define vec_vsubuhm __builtin_vec_vsubuhm -#define vec_vsubuhs __builtin_vec_vsubuhs -#define vec_vsubuwm __builtin_vec_vsubuwm -#define vec_vsubuws __builtin_vec_vsubuws -#define vec_xor __builtin_vec_xor - -#define vec_extract __builtin_vec_extract -#define vec_insert __builtin_vec_insert -#define vec_splats __builtin_vec_splats -#define vec_promote __builtin_vec_promote #ifdef __VSX__ /* VSX additions */ -#define vec_div __builtin_vec_div -#define vec_mul __builtin_vec_mul -#define vec_msub __builtin_vec_msub -#define vec_nmadd __builtin_vec_nmadd -#define vec_nearbyint __builtin_vec_nearbyint -#define vec_rint __builtin_vec_rint -#define vec_sqrt __builtin_vec_sqrt #define vec_vsx_ld __builtin_vec_vsx_ld #define vec_vsx_st __builtin_vec_vsx_st -#define vec_xl __builtin_vec_vsx_ld -#define vec_xl_be __builtin_vec_xl_be -#define vec_xst __builtin_vec_vsx_st -#define vec_xst_be __builtin_vec_xst_be - -/* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions - instead of __builtin_vec_<xxx> */ -#define vec_xxsldwi __builtin_vsx_xxsldwi -#define vec_xxpermdi __builtin_vsx_xxpermdi -#endif - -#ifdef _ARCH_PWR8 -/* Vector additions added in ISA 2.07. */ -#define vec_eqv __builtin_vec_eqv -#define vec_nand __builtin_vec_nand -#define vec_orc __builtin_vec_orc -#define vec_vaddcuq __builtin_vec_vaddcuq -#define vec_vaddudm __builtin_vec_vaddudm -#define vec_vadduqm __builtin_vec_vadduqm -#define vec_vbpermq __builtin_vec_vbpermq -#define vec_bperm __builtin_vec_vbperm_api -#define vec_vclz __builtin_vec_vclz -#define vec_cntlz __builtin_vec_vclz -#define vec_vclzb __builtin_vec_vclzb -#define vec_vclzd __builtin_vec_vclzd -#define vec_vclzh __builtin_vec_vclzh -#define vec_vclzw __builtin_vec_vclzw -#define vec_vaddecuq __builtin_vec_vaddecuq -#define vec_vaddeuqm __builtin_vec_vaddeuqm -#define vec_vsubecuq __builtin_vec_vsubecuq -#define vec_vsubeuqm __builtin_vec_vsubeuqm -#define vec_vgbbd __builtin_vec_vgbbd -#define vec_gb __builtin_vec_vgbbd -#define vec_vmaxsd __builtin_vec_vmaxsd -#define vec_vmaxud __builtin_vec_vmaxud -#define vec_vminsd __builtin_vec_vminsd -#define vec_vminud __builtin_vec_vminud -#define vec_vmrgew __builtin_vec_vmrgew -#define vec_vmrgow __builtin_vec_vmrgow -#define vec_vpksdss __builtin_vec_vpksdss -#define vec_vpksdus __builtin_vec_vpksdus -#define vec_vpkudum __builtin_vec_vpkudum -#define vec_vpkudus __builtin_vec_vpkudus -#define vec_vpopcnt __builtin_vec_vpopcnt -#define vec_vpopcntb __builtin_vec_vpopcntb -#define vec_vpopcntd __builtin_vec_vpopcntd -#define vec_vpopcnth __builtin_vec_vpopcnth -#define vec_vpopcntw __builtin_vec_vpopcntw -#define vec_popcnt __builtin_vec_vpopcntu -#define vec_vrld __builtin_vec_vrld -#define vec_vsld __builtin_vec_vsld -#define vec_vsrad __builtin_vec_vsrad -#define vec_vsrd __builtin_vec_vsrd -#define vec_vsubcuq __builtin_vec_vsubcuq -#define vec_vsubudm __builtin_vec_vsubudm -#define vec_vsubuqm __builtin_vec_vsubuqm -#define vec_vupkhsw __builtin_vec_vupkhsw -#define vec_vupklsw __builtin_vec_vupklsw -#define vec_revb __builtin_vec_revb -#define vec_sbox_be __builtin_crypto_vsbox_be -#define vec_cipher_be __builtin_crypto_vcipher_be -#define vec_cipherlast_be __builtin_crypto_vcipherlast_be -#define vec_ncipher_be __builtin_crypto_vncipher_be -#define vec_ncipherlast_be __builtin_crypto_vncipherlast_be -#endif - -#ifdef __POWER9_VECTOR__ -/* Vector additions added in ISA 3.0. */ -#define vec_first_match_index __builtin_vec_first_match_index -#define vec_first_match_or_eos_index __builtin_vec_first_match_or_eos_index -#define vec_first_mismatch_index __builtin_vec_first_mismatch_index -#define vec_first_mismatch_or_eos_index __builtin_vec_first_mismatch_or_eos_index -#define vec_pack_to_short_fp32 __builtin_vec_convert_4f32_8f16 -#define vec_parity_lsbb __builtin_vec_vparity_lsbb -#define vec_vctz __builtin_vec_vctz -#define vec_cnttz __builtin_vec_vctz -#define vec_vctzb __builtin_vec_vctzb -#define vec_vctzd __builtin_vec_vctzd -#define vec_vctzh __builtin_vec_vctzh -#define vec_vctzw __builtin_vec_vctzw -#define vec_extract4b __builtin_vec_extract4b -#define vec_insert4b __builtin_vec_insert4b -#define vec_vprtyb __builtin_vec_vprtyb -#define vec_vprtybd __builtin_vec_vprtybd -#define vec_vprtybw __builtin_vec_vprtybw - -#ifdef _ARCH_PPC64 -#define vec_vprtybq __builtin_vec_vprtybq -#endif - -#define vec_absd __builtin_vec_vadu -#define vec_absdb __builtin_vec_vadub -#define vec_absdh __builtin_vec_vaduh -#define vec_absdw __builtin_vec_vaduw - -#define vec_slv __builtin_vec_vslv -#define vec_srv __builtin_vec_vsrv - -#define vec_extract_exp __builtin_vec_extract_exp -#define vec_extract_sig __builtin_vec_extract_sig -#define vec_insert_exp __builtin_vec_insert_exp -#define vec_test_data_class __builtin_vec_test_data_class - -#define vec_extract_fp_from_shorth __builtin_vec_vextract_fp_from_shorth -#define vec_extract_fp_from_shortl __builtin_vec_vextract_fp_from_shortl -#define vec_extract_fp32_from_shorth __builtin_vec_vextract_fp_from_shorth -#define vec_extract_fp32_from_shortl __builtin_vec_vextract_fp_from_shortl - -#define scalar_extract_exp __builtin_vec_scalar_extract_exp -#define scalar_extract_sig __builtin_vec_scalar_extract_sig -#define scalar_insert_exp __builtin_vec_scalar_insert_exp -#define scalar_test_data_class __builtin_vec_scalar_test_data_class -#define scalar_test_neg __builtin_vec_scalar_test_neg - -#define scalar_cmp_exp_gt __builtin_vec_scalar_cmp_exp_gt -#define scalar_cmp_exp_lt __builtin_vec_scalar_cmp_exp_lt -#define scalar_cmp_exp_eq __builtin_vec_scalar_cmp_exp_eq -#define scalar_cmp_exp_unordered __builtin_vec_scalar_cmp_exp_unordered - -#ifdef _ARCH_PPC64 -#define vec_xl_len __builtin_vec_lxvl -#define vec_xst_len __builtin_vec_stxvl -#define vec_xl_len_r __builtin_vec_xl_len_r -#define vec_xst_len_r __builtin_vec_xst_len_r -#endif - -#define vec_cmpnez __builtin_vec_vcmpnez - -#define vec_cntlz_lsbb __builtin_vec_vclzlsbb -#define vec_cnttz_lsbb __builtin_vec_vctzlsbb - -#define vec_test_lsbb_all_ones __builtin_vec_xvtlsbb_all_ones -#define vec_test_lsbb_all_zeros __builtin_vec_xvtlsbb_all_zeros - -#define vec_xlx __builtin_vec_vextulx -#define vec_xrx __builtin_vec_vexturx -#define vec_signexti __builtin_vec_vsignexti -#define vec_signextll __builtin_vec_vsignextll +#define __builtin_vec_xl __builtin_vec_vsx_ld +#define __builtin_vec_xst __builtin_vec_vsx_st -#endif - -/* BCD builtins, map ABI builtin name to existing builtin name. */ -#define __builtin_bcdadd __builtin_vec_bcdadd -#define __builtin_bcdadd_lt __builtin_vec_bcdadd_lt -#define __builtin_bcdadd_eq __builtin_vec_bcdadd_eq -#define __builtin_bcdadd_gt __builtin_vec_bcdadd_gt #define __builtin_bcdadd_ofl __builtin_vec_bcdadd_ov -#define __builtin_bcdadd_ov __builtin_vec_bcdadd_ov -#define __builtin_bcdsub __builtin_vec_bcdsub -#define __builtin_bcdsub_lt __builtin_vec_bcdsub_lt -#define __builtin_bcdsub_eq __builtin_vec_bcdsub_eq -#define __builtin_bcdsub_gt __builtin_vec_bcdsub_gt #define __builtin_bcdsub_ofl __builtin_vec_bcdsub_ov -#define __builtin_bcdsub_ov __builtin_vec_bcdsub_ov -#define __builtin_bcdinvalid __builtin_vec_bcdinvalid -#define __builtin_bcdmul10 __builtin_vec_bcdmul10 -#define __builtin_bcddiv10 __builtin_vec_bcddiv10 -#define __builtin_bcd2dfp __builtin_vec_denb2dfp #define __builtin_bcdcmpeq(a,b) __builtin_vec_bcdsub_eq(a,b,0) #define __builtin_bcdcmpgt(a,b) __builtin_vec_bcdsub_gt(a,b,0) #define __builtin_bcdcmplt(a,b) __builtin_vec_bcdsub_lt(a,b,0) #define __builtin_bcdcmpge(a,b) __builtin_vec_bcdsub_ge(a,b,0) #define __builtin_bcdcmple(a,b) __builtin_vec_bcdsub_le(a,b,0) +#endif +/* For _ARCH_PWR10. Always define to support #pragma GCC target. */ +#define __builtin_vec_se_lxvrx __builtin_vec_xl_sext +#define __builtin_vec_tr_stxvrx __builtin_vec_xst_trunc +#define __builtin_vec_ze_lxvrx __builtin_vec_xl_zext +#define __builtin_vsx_xxpermx __builtin_vec_xxpermx /* Predicates. For C++, we use templates in order to allow non-parenthesized arguments. @@ -700,14 +318,9 @@ __altivec_scalar_pred(vec_any_nle, #define vec_any_nle(a1, a2) __builtin_vec_vcmpge_p (__CR6_LT_REV, (a2), (a1)) #endif -/* These do not accept vectors, so they do not have a __builtin_vec_* - counterpart. */ +/* Miscellaneous definitions. */ #define vec_dss(x) __builtin_altivec_dss((x)) #define vec_dssall() __builtin_altivec_dssall () -#define vec_mfvscr() ((__vector unsigned short) __builtin_altivec_mfvscr ()) -#define vec_splat_s8(x) __builtin_altivec_vspltisb ((x)) -#define vec_splat_s16(x) __builtin_altivec_vspltish ((x)) -#define vec_splat_s32(x) __builtin_altivec_vspltisw ((x)) #define vec_splat_u8(x) ((__vector unsigned char) vec_splat_s8 ((x))) #define vec_splat_u16(x) ((__vector unsigned short) vec_splat_s16 ((x))) #define vec_splat_u32(x) ((__vector unsigned int) vec_splat_s32 ((x))) @@ -716,59 +329,4 @@ __altivec_scalar_pred(vec_any_nle, to #define vec_step to __builtin_vec_step. */ #define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0) -#ifdef _ARCH_PWR10 -#define vec_signextq __builtin_vec_vsignextq -#define vec_dive __builtin_vec_dive -#define vec_mod __builtin_vec_mod - -/* May modify these macro definitions if future capabilities overload - with support for different vector argument and result types. */ -#define vec_cntlzm(a, b) __builtin_altivec_vclzdm (a, b) -#define vec_cnttzm(a, b) __builtin_altivec_vctzdm (a, b) -#define vec_pdep(a, b) __builtin_altivec_vpdepd (a, b) -#define vec_pext(a, b) __builtin_altivec_vpextd (a, b) -#define vec_cfuge(a, b) __builtin_altivec_vcfuged (a, b) -#define vec_genpcvm(a, b) __builtin_vec_xxgenpcvm (a, b) - -/* Overloaded built-in functions for ISA 3.1. */ -#define vec_extractl(a, b, c) __builtin_vec_extractl (a, b, c) -#define vec_extracth(a, b, c) __builtin_vec_extracth (a, b, c) -#define vec_insertl(a, b, c) __builtin_vec_insertl (a, b, c) -#define vec_inserth(a, b, c) __builtin_vec_inserth (a, b, c) -#define vec_replace_elt(a, b, c) __builtin_vec_replace_elt (a, b, c) -#define vec_replace_unaligned(a, b, c) __builtin_vec_replace_un (a, b, c) -#define vec_sldb(a, b, c) __builtin_vec_sldb (a, b, c) -#define vec_srdb(a, b, c) __builtin_vec_srdb (a, b, c) -#define vec_splati(a) __builtin_vec_xxspltiw (a) -#define vec_splatid(a) __builtin_vec_xxspltid (a) -#define vec_splati_ins(a, b, c) __builtin_vec_xxsplti32dx (a, b, c) -#define vec_blendv(a, b, c) __builtin_vec_xxblend (a, b, c) -#define vec_permx(a, b, c, d) __builtin_vec_xxpermx (a, b, c, d) - -#define vec_gnb(a, b) __builtin_vec_gnb (a, b) -#define vec_clrl(a, b) __builtin_vec_clrl (a, b) -#define vec_clrr(a, b) __builtin_vec_clrr (a, b) -#define vec_ternarylogic(a, b, c, d) __builtin_vec_xxeval (a, b, c, d) - -#define vec_strir(a) __builtin_vec_strir (a) -#define vec_stril(a) __builtin_vec_stril (a) - -#define vec_strir_p(a) __builtin_vec_strir_p (a) -#define vec_stril_p(a) __builtin_vec_stril_p (a) - -#define vec_mulh(a, b) __builtin_vec_mulh ((a), (b)) -#define vec_dive(a, b) __builtin_vec_dive ((a), (b)) -#define vec_mod(a, b) __builtin_vec_mod ((a), (b)) - -/* VSX Mask Manipulation builtin. */ -#define vec_genbm __builtin_vec_mtvsrbm -#define vec_genhm __builtin_vec_mtvsrhm -#define vec_genwm __builtin_vec_mtvsrwm -#define vec_gendm __builtin_vec_mtvsrdm -#define vec_genqm __builtin_vec_mtvsrqm -#define vec_cntm __builtin_vec_cntm -#define vec_expandm __builtin_vec_vexpandm -#define vec_extractm __builtin_vec_vextractm -#endif - #endif /* _ALTIVEC_H */ diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def index 58dfce1..30556e5 100644 --- a/gcc/config/rs6000/rs6000-builtin-new.def +++ b/gcc/config/rs6000/rs6000-builtin-new.def @@ -273,7 +273,7 @@ ; Power6 builtins requiring 64-bit GPRs (even with 32-bit addressing). [power6-64] const signed long __builtin_p6_cmpb (signed long, signed long); - CMPB cmpbdi3 {} + CMPB cmpbdi3 {no32bit} ; AltiVec builtins. @@ -2018,7 +2018,7 @@ ADDG6S addg6s {} const signed long __builtin_bpermd (signed long, signed long); - BPERMD bpermd_di {} + BPERMD bpermd_di {32bit} const unsigned int __builtin_cbcdtd (unsigned int); CBCDTD cbcdtd {} @@ -2971,7 +2971,7 @@ void __builtin_set_fpscr_drn (const int[0,7]); SET_FPSCR_DRN rs6000_set_fpscr_drn {} - const unsigned long __builtin_unpack_dec128 (_Decimal128, const int<1>); + const unsigned long long __builtin_unpack_dec128 (_Decimal128, const int<1>); UNPACK_TD unpacktd {} @@ -3014,39 +3014,39 @@ [htm] - unsigned long long __builtin_get_texasr (); + unsigned long __builtin_get_texasr (); GET_TEXASR nothing {htm,htmspr} - unsigned long long __builtin_get_texasru (); + unsigned long __builtin_get_texasru (); GET_TEXASRU nothing {htm,htmspr} - unsigned long long __builtin_get_tfhar (); + unsigned long __builtin_get_tfhar (); GET_TFHAR nothing {htm,htmspr} - unsigned long long __builtin_get_tfiar (); + unsigned long __builtin_get_tfiar (); GET_TFIAR nothing {htm,htmspr} - void __builtin_set_texasr (unsigned long long); + void __builtin_set_texasr (unsigned long); SET_TEXASR nothing {htm,htmspr} - void __builtin_set_texasru (unsigned long long); + void __builtin_set_texasru (unsigned long); SET_TEXASRU nothing {htm,htmspr} - void __builtin_set_tfhar (unsigned long long); + void __builtin_set_tfhar (unsigned long); SET_TFHAR nothing {htm,htmspr} - void __builtin_set_tfiar (unsigned long long); + void __builtin_set_tfiar (unsigned long); SET_TFIAR nothing {htm,htmspr} unsigned int __builtin_tabort (unsigned int); TABORT tabort {htm,htmcr} - unsigned int __builtin_tabortdc (unsigned long long, unsigned long long, \ - unsigned long long); + unsigned int __builtin_tabortdc (unsigned long, unsigned long, \ + unsigned long); TABORTDC tabortdc {htm,htmcr} - unsigned int __builtin_tabortdci (unsigned long long, unsigned long long, \ - unsigned long long); + unsigned int __builtin_tabortdci (unsigned long, unsigned long, \ + unsigned long); TABORTDCI tabortdci {htm,htmcr} unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int); diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 01688c4..141d2fc 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -15736,9 +15736,10 @@ rs6000_expand_new_builtin (tree exp, rtx target, } if (bif_is_no32bit (*bifaddr) && TARGET_32BIT) - fatal_error (input_location, - "%<%s%> is not supported in 32-bit mode", - bifaddr->bifname); + { + error ("%<%s%> is not supported in 32-bit mode", bifaddr->bifname); + return const0_rtx; + } if (bif_is_cpu (*bifaddr)) return new_cpu_expand_builtin (fcode, exp, target); @@ -15762,6 +15763,8 @@ rs6000_expand_new_builtin (tree exp, rtx target, { if (fcode == RS6000_BIF_MFTB) icode = CODE_FOR_rs6000_mftb_si; + else if (fcode == RS6000_BIF_BPERMD) + icode = CODE_FOR_bpermd_si; else gcc_unreachable (); } diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c index 4ce83bd..d2e9c4c 100644 --- a/gcc/config/rs6000/rs6000-gen-builtins.c +++ b/gcc/config/rs6000/rs6000-gen-builtins.c @@ -2845,7 +2845,7 @@ write_init_file (void) fprintf (init_file, "#include \"rs6000-builtins.h\"\n"); fprintf (init_file, "\n"); - fprintf (init_file, "int new_builtins_are_live = 0;\n\n"); + fprintf (init_file, "int new_builtins_are_live = 1;\n\n"); fprintf (init_file, "tree rs6000_builtin_decls_x[RS6000_OVLD_MAX];\n\n"); diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c index 9221806..53b67c9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c @@ -14,7 +14,7 @@ get_exponent (double *p) { double source = *p; - return scalar_extract_exp (source); /* { dg-error "'__builtin_vec_scalar_extract_exp' is not supported in this compiler configuration" } */ + return scalar_extract_exp (source); /* { dg-error "'__builtin_vsx_scalar_extract_exp' requires the" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c index e24d4bd..39ee74c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c @@ -12,5 +12,5 @@ get_significand (double *p) { double source = *p; - return __builtin_vec_scalar_extract_sig (source); /* { dg-error "'__builtin_vec_scalar_extract_sig' is not supported in this compiler configuration" } */ + return __builtin_vec_scalar_extract_sig (source); /* { dg-error "'__builtin_vsx_scalar_extract_sig' requires the" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c index feb9431..efd6972 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c @@ -16,5 +16,5 @@ insert_exponent (unsigned long long int *significand_p, unsigned long long int significand = *significand_p; unsigned long long int exponent = *exponent_p; - return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vec_scalar_insert_exp' is not supported in this compiler configuration" } */ + return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vsx_scalar_insert_exp' requires the" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c index 0e5683d..f85966a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c @@ -16,5 +16,5 @@ insert_exponent (double *significand_p, double significand = *significand_p; unsigned long long int exponent = *exponent_p; - return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vec_scalar_insert_exp' is not supported in this compiler configuration" } */ + return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vsx_scalar_insert_exp_dp' requires the" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c index bd68f77..b1be828 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c @@ -16,5 +16,5 @@ insert_exponent (unsigned __int128 *significand_p, /* { dg-error "'__int128' is unsigned __int128 significand = *significand_p; /* { dg-error "'__int128' is not supported on this target" } */ unsigned long long int exponent = *exponent_p; - return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vec_scalar_insert_exp' is not supported in this compiler configuration" } */ + return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vsx_scalar_insert_exp' requires the" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c index 7d2b4de..46d743a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c @@ -10,5 +10,5 @@ test_neg (float *p) { float source = *p; - return __builtin_vec_scalar_test_neg_sp (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_sp' requires" } */ + return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_sp' requires" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c index b503dfa..bfc892b 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c @@ -10,5 +10,5 @@ test_neg (double *p) { double source = *p; - return __builtin_vec_scalar_test_neg_dp (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_dp' requires" } */ + return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_dp' requires" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c index bab8604..8c55c1c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c @@ -10,5 +10,5 @@ test_neg (__ieee128 *p) { __ieee128 source = *p; - return __builtin_vec_scalar_test_neg_qp (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_qp' requires" } */ + return __builtin_vec_scalar_test_neg (source); /* { dg-error "'__builtin_vsx_scalar_test_neg_qp' requires" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c b/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c index 44cc778..4c676ba 100644 --- a/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c +++ b/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c @@ -10,5 +10,5 @@ int test_byte_in_set (unsigned char b, unsigned long long set_members) { - return __builtin_byte_in_set (b, set_members); /* { dg-warning "implicit declaration of function" } */ + return __builtin_byte_in_set (b, set_members); /* { dg-error "'__builtin_scalar_byte_in_set' requires the" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c index 113ab6a..02b84d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/cmpb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/cmpb-2.c @@ -8,7 +8,7 @@ void abort (); unsigned long long int do_compare (unsigned long long int a, unsigned long long int b) { - return __builtin_cmpb (a, b); /* { dg-warning "implicit declaration of function '__builtin_cmpb'" } */ + return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb' requires the '-mcpu=power6' option" } */ } void diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb-3.c b/gcc/testsuite/gcc.target/powerpc/cmpb-3.c index de111a8..75641bd 100644 --- a/gcc/testsuite/gcc.target/powerpc/cmpb-3.c +++ b/gcc/testsuite/gcc.target/powerpc/cmpb-3.c @@ -8,7 +8,7 @@ void abort (); long long int do_compare (long long int a, long long int b) { - return __builtin_cmpb (a, b); /* { dg-error "'__builtin_cmpb' is not supported in this compiler configuration" } */ + return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb' requires the '-mcpu=power6' option and either the '-m64' or '-mpowerpc64' option" } */ } void expect (long long int pattern, long long int value) diff --git a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c index 37b5474..d4264ab 100644 --- a/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c +++ b/gcc/testsuite/gcc.target/powerpc/cmpb32-2.c @@ -7,7 +7,7 @@ void abort (); unsigned int do_compare (unsigned int a, unsigned int b) { - return __builtin_cmpb (a, b); /* { dg-warning "implicit declaration of function '__builtin_cmpb'" } */ + return __builtin_cmpb (a, b); /* { dg-error "'__builtin_p6_cmpb_32' requires the '-mcpu=power6' option" } */ } void diff --git a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c index 4066b12..b3a6c73 100644 --- a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c @@ -5,21 +5,21 @@ void use_builtins_d (__vector unsigned long long *p, __vector unsigned long long *q, __vector unsigned long long *r, __vector unsigned long long *s) { - p[0] = __builtin_crypto_vcipher (q[0], r[0]); /* { dg-error "'__builtin_crypto_vcipher' is not supported with the current options" } */ - p[1] = __builtin_crypto_vcipherlast (q[1], r[1]); /* { dg-error "'__builtin_crypto_vcipherlast' is not supported with the current options" } */ - p[2] = __builtin_crypto_vncipher (q[2], r[2]); /* { dg-error "'__builtin_crypto_vncipher' is not supported with the current options" } */ - p[3] = __builtin_crypto_vncipherlast (q[3], r[3]); /* { dg-error "'__builtin_crypto_vncipherlast' is not supported with the current options" } */ + p[0] = __builtin_crypto_vcipher (q[0], r[0]); /* { dg-error "'__builtin_crypto_vcipher' requires the '-mcrypto' option" } */ + p[1] = __builtin_crypto_vcipherlast (q[1], r[1]); /* { dg-error "'__builtin_crypto_vcipherlast' requires the '-mcrypto' option" } */ + p[2] = __builtin_crypto_vncipher (q[2], r[2]); /* { dg-error "'__builtin_crypto_vncipher' requires the '-mcrypto' option" } */ + p[3] = __builtin_crypto_vncipherlast (q[3], r[3]); /* { dg-error "'__builtin_crypto_vncipherlast' requires the '-mcrypto' option" } */ p[4] = __builtin_crypto_vpermxor (q[4], r[4], s[4]); p[5] = __builtin_crypto_vpmsumd (q[5], r[5]); - p[6] = __builtin_crypto_vshasigmad (q[6], 1, 15); /* { dg-error "'__builtin_crypto_vshasigmad' is not supported with the current options" } */ - p[7] = __builtin_crypto_vsbox (q[7]); /* { dg-error "'__builtin_crypto_vsbox' is not supported with the current options" } */ + p[6] = __builtin_crypto_vshasigmad (q[6], 1, 15); /* { dg-error "'__builtin_crypto_vshasigmad' requires the '-mcrypto' option" } */ + p[7] = __builtin_crypto_vsbox (q[7]); /* { dg-error "'__builtin_crypto_vsbox' requires the '-mcrypto' option" } */ } void use_builtins_w (__vector unsigned int *p, __vector unsigned int *q, __vector unsigned int *r, __vector unsigned int *s) { p[0] = __builtin_crypto_vpermxor (q[0], r[0], s[0]); p[1] = __builtin_crypto_vpmsumw (q[1], r[1]); - p[2] = __builtin_crypto_vshasigmaw (q[2], 1, 15); /* { dg-error "'__builtin_crypto_vshasigmaw' is not supported with the current options" } */ + p[2] = __builtin_crypto_vshasigmaw (q[2], 1, 15); /* { dg-error "'__builtin_crypto_vshasigmaw' requires the '-mcrypto' option" } */ } void use_builtins_h (__vector unsigned short *p, __vector unsigned short *q, __vector unsigned short *r, __vector unsigned short *s) diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c index 7661917..b95fa32 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c @@ -18,7 +18,7 @@ vector float test_fc () vector double testd_00 (vector double x) { return vec_splat (x, 0b00000); } vector double testd_01 (vector double x) { return vec_splat (x, 0b00001); } vector double test_dc () -{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00010); } +{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00001); } /* If the source vector is a known constant, we will generate a load or possibly XXSPLTIW. */ @@ -28,5 +28,5 @@ vector double test_dc () /* { dg-final { scan-assembler-times {\mvspltw\M|\mxxspltw\M} 3 } } */ /* For double types, we will generate xxpermdi instructions. */ -/* { dg-final { scan-assembler-times "xxpermdi" 3 } } */ +/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c index b95b987..3fa1f05 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c @@ -9,23 +9,19 @@ vector bool long long testb_00 (vector bool long long x) { return vec_splat (x, 0b00000); } vector bool long long testb_01 (vector bool long long x) { return vec_splat (x, 0b00001); } -vector bool long long testb_02 (vector bool long long x) { return vec_splat (x, 0b00010); } vector signed long long tests_00 (vector signed long long x) { return vec_splat (x, 0b00000); } vector signed long long tests_01 (vector signed long long x) { return vec_splat (x, 0b00001); } -vector signed long long tests_02 (vector signed long long x) { return vec_splat (x, 0b00010); } vector unsigned long long testu_00 (vector unsigned long long x) { return vec_splat (x, 0b00000); } vector unsigned long long testu_01 (vector unsigned long long x) { return vec_splat (x, 0b00001); } -vector unsigned long long testu_02 (vector unsigned long long x) { return vec_splat (x, 0b00010); } /* Similar test as above, but the source vector is a known constant. */ -vector bool long long test_bll () { const vector bool long long y = {12, 23}; return vec_splat (y, 0b00010); } -vector signed long long test_sll () { const vector signed long long y = {34, 45}; return vec_splat (y, 0b00010); } -vector unsigned long long test_ull () { const vector unsigned long long y = {56, 67}; return vec_splat (y, 0b00010); } +vector bool long long test_bll () { const vector bool long long y = {12, 23}; return vec_splat (y, 0b00001); } +vector signed long long test_sll () { const vector signed long long y = {34, 45}; return vec_splat (y, 0b00001); } /* Assorted load instructions for the initialization with known constants. */ -/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mplxv\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mplxv\M|\mxxspltib\M} 2 } } */ /* xxpermdi for vec_splat of long long vectors. At the time of this writing, the number of xxpermdi instructions diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c index 20f5b05..263a172 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-misc-invalid.c @@ -10,24 +10,24 @@ vector signed short testss_1 (unsigned int ui) { - return vec_splat_s16 (ui);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_s16 (ui);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector unsigned short testss_2 (signed int si) { - return vec_splat_u16 (si);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_u16 (si);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector signed char testsc_1 (unsigned int ui) { - return vec_splat_s8 (ui); /* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_s8 (ui); /* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector unsigned char testsc_2 (signed int si) { - return vec_splat_u8 (si);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_u8 (si);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c index 1255ee9..1356793 100644 --- a/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/int_128bit-runnable.c @@ -11,9 +11,9 @@ /* { dg-final { scan-assembler-times {\mvrlq\M} 2 } } */ /* { dg-final { scan-assembler-times {\mvrlqnm\M} 2 } } */ /* { dg-final { scan-assembler-times {\mvrlqmi\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mvcmpequq\M} 16 } } */ -/* { dg-final { scan-assembler-times {\mvcmpgtsq\M} 16 } } */ -/* { dg-final { scan-assembler-times {\mvcmpgtuq\M} 16 } } */ +/* { dg-final { scan-assembler-times {\mvcmpequq\M} 24 } } */ +/* { dg-final { scan-assembler-times {\mvcmpgtsq\M} 26 } } */ +/* { dg-final { scan-assembler-times {\mvcmpgtuq\M} 26 } } */ /* { dg-final { scan-assembler-times {\mvmuloud\M} 1 } } */ /* { dg-final { scan-assembler-times {\mvmulesd\M} 1 } } */ /* { dg-final { scan-assembler-times {\mvmulosd\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c index e2db0ff..f37f1f1 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c @@ -10,6 +10,6 @@ main() int mask; /* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */ - res = __builtin_crypto_vshasigmaw (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */ + res = __builtin_crypto_vshasigmaw (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */ return 0; } diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c index 144b705..0819a05 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c @@ -10,6 +10,6 @@ main () int mask; /* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */ - res = __builtin_crypto_vshasigmad (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */ + res = __builtin_crypto_vshasigmad (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */ return 0; } diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c index 99a3e24..cc2e46c 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c @@ -12,6 +12,6 @@ main () int mask; /* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */ - res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */ + res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */ return res; } diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c index 7f5f6f7..ac12910 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c @@ -12,6 +12,6 @@ main () int mask; /* Argument 2 must be 0 or 1. Argument 3 must be in range 0..15. */ - res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be in the range \[0, 15\]} } */ + res = vec_shasigma_be (test, 1, 0xff); /* { dg-error {argument 3 must be a 4-bit unsigned literal} } */ return res; } diff --git a/gcc/testsuite/gcc.target/powerpc/pr88100.c b/gcc/testsuite/gcc.target/powerpc/pr88100.c index 4452145..764c897 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr88100.c +++ b/gcc/testsuite/gcc.target/powerpc/pr88100.c @@ -10,35 +10,35 @@ vector unsigned char splatu1 (void) { - return vec_splat_u8(0x100);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_u8(0x100);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector unsigned short splatu2 (void) { - return vec_splat_u16(0x10000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_u16(0x10000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector unsigned int splatu3 (void) { - return vec_splat_u32(0x10000000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_u32(0x10000000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector signed char splats1 (void) { - return vec_splat_s8(0x100);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_s8(0x100);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector signed short splats2 (void) { - return vec_splat_s16(0x10000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_s16(0x10000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } vector signed int splats3 (void) { - return vec_splat_s32(0x10000000);/* { dg-error "argument 1 must be a 5-bit signed literal" } */ + return vec_splat_s32(0x10000000);/* { dg-error "argument 1 must be a literal between -16 and 15, inclusive" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c index e03099b..c1667d9 100644 --- a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c +++ b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c @@ -20,7 +20,7 @@ vector bool int test2 (vector signed int a, vector signed int b) { return vec_cmpnez (a, b); - /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */ + /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' and '-mvsx' options" "" { target *-*-* } .-1 } */ } #pragma GCC target ("cpu=power7") @@ -28,7 +28,7 @@ vector signed int test3 (vector signed int a, vector signed int b) { return vec_mergee (a, b); - /* { dg-error "'__builtin_altivec_vmrgew_v4si' requires the '-mpower8-vector' option" "" { target *-*-* } .-1 } */ + /* { dg-error "'__builtin_altivec_vmrgew_v4si' requires the '-mcpu=power8' and '-mvsx' options" "" { target *-*-* } .-1 } */ } #pragma GCC target ("cpu=power6") diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power8.c b/gcc/testsuite/gcc.target/powerpc/pragma_power8.c index c8d2cdd..cb0f308 100644 --- a/gcc/testsuite/gcc.target/powerpc/pragma_power8.c +++ b/gcc/testsuite/gcc.target/powerpc/pragma_power8.c @@ -19,6 +19,7 @@ test1 (vector int a, vector int b) #pragma GCC target ("cpu=power7") /* Force a re-read of altivec.h with new cpu target. */ #undef _ALTIVEC_H +#undef _RS6000_VECDEFINES_H #include <altivec.h> #ifdef _ARCH_PWR7 vector signed int @@ -33,6 +34,7 @@ test2 (vector signed int a, vector signed int b) #pragma GCC target ("cpu=power8") /* Force a re-read of altivec.h with new cpu target. */ #undef _ALTIVEC_H +#undef _RS6000_VECDEFINES_H #include <altivec.h> #ifdef _ARCH_PWR8 vector int diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power9.c b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c index e33aad1..e05f1f4 100644 --- a/gcc/testsuite/gcc.target/powerpc/pragma_power9.c +++ b/gcc/testsuite/gcc.target/powerpc/pragma_power9.c @@ -17,6 +17,7 @@ test1 (vector int a, vector int b) #pragma GCC target ("cpu=power7") #undef _ALTIVEC_H +#undef _RS6000_VECDEFINES_H #include <altivec.h> #ifdef _ARCH_PWR7 vector signed int @@ -30,6 +31,7 @@ test2 (vector signed int a, vector signed int b) #pragma GCC target ("cpu=power8") #undef _ALTIVEC_H +#undef _RS6000_VECDEFINES_H #include <altivec.h> #ifdef _ARCH_PWR8 vector int @@ -50,6 +52,7 @@ test3b (vec_t a, vec_t b) #pragma GCC target ("cpu=power9,power9-vector") #undef _ALTIVEC_H +#undef _RS6000_VECDEFINES_H #include <altivec.h> #ifdef _ARCH_PWR9 vector bool int diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c b/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c index 028ab0b..4f9d9e0 100644 --- a/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c +++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_drn_builtin_error.c @@ -9,8 +9,8 @@ int main () __builtin_set_fpscr_drn() also support a variable as an argument but can't test variable value at compile time. */ - __builtin_set_fpscr_drn(-1); /* { dg-error "Argument must be a value between 0 and 7" } */ - __builtin_set_fpscr_drn(8); /* { dg-error "Argument must be a value between 0 and 7" } */ + __builtin_set_fpscr_drn(-1); /* { dg-error "argument 1 must be a variable or a literal between 0 and 7, inclusive" } */ + __builtin_set_fpscr_drn(8); /* { dg-error "argument 1 must be a variable or a literal between 0 and 7, inclusive" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c index aea6509..10391b7 100644 --- a/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c +++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_error.c @@ -8,13 +8,13 @@ int main () int arguments. The builtins __builtin_set_fpscr_rn() also supports a variable as an argument but can't test variable value at compile time. */ - __builtin_mtfsb0(-1); /* { dg-error "Argument must be a constant between 0 and 31" } */ - __builtin_mtfsb0(32); /* { dg-error "Argument must be a constant between 0 and 31" } */ + __builtin_mtfsb0(-1); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */ + __builtin_mtfsb0(32); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */ - __builtin_mtfsb1(-1); /* { dg-error "Argument must be a constant between 0 and 31" } */ - __builtin_mtfsb1(32); /* { dg-error "Argument must be a constant between 0 and 31" } */ + __builtin_mtfsb1(-1); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */ + __builtin_mtfsb1(32); /* { dg-error "argument 1 must be a 5-bit unsigned literal" } */ - __builtin_set_fpscr_rn(-1); /* { dg-error "Argument must be a value between 0 and 3" } */ - __builtin_set_fpscr_rn(4); /* { dg-error "Argument must be a value between 0 and 3" } */ + __builtin_set_fpscr_rn(-1); /* { dg-error "argument 1 must be a variable or a literal between 0 and 3, inclusive" } */ + __builtin_set_fpscr_rn(4); /* { dg-error "argument 1 must be a variable or a literal between 0 and 3, inclusive" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c b/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c index 895bb95..4e59cbf 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-gnb-2.c @@ -20,7 +20,7 @@ do_vec_gnb (vector unsigned __int128 source, int stride) case 5: return vec_gnb (source, 1); /* { dg-error "between 2 and 7" } */ case 6: - return vec_gnb (source, stride); /* { dg-error "unsigned literal" } */ + return vec_gnb (source, stride); /* { dg-error "literal" } */ case 7: return vec_gnb (source, 7); diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c index f53c6dc..a41e82e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c @@ -12,5 +12,5 @@ test_all_not_equal_and_not_zero (vector unsigned short *arg1_p, vector unsigned short arg_2 = *arg2_p; return __builtin_vec_vcmpnez_p (__CR6_LT, arg_1, arg_2); - /* { dg-error "'__builtin_altivec_vcmpnezh_p' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */ + /* { dg-error "'__builtin_altivec_vcmpnezh_p' requires the '-mcpu=power9' and '-mvsx' options" "" { target *-*-* } .-1 } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c index 757acd9..3bf8a32 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c @@ -11,5 +11,5 @@ test_any_equal (vector unsigned int *arg1_p, vector unsigned int *arg2_p) vector unsigned int arg_2 = *arg2_p; return __builtin_vec_vcmpnez_p (__CR6_LT_REV, arg_1, arg_2); - /* { dg-error "'__builtin_altivec_vcmpnezw_p' requires the '-mcpu=power9' option" "" { target *-*-* } .-1 } */ + /* { dg-error "'__builtin_altivec_vcmpnezw_p' requires the '-mcpu=power9' and '-mvsx' options" "" { target *-*-* } .-1 } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c index 811b32f..52110af 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c @@ -10,5 +10,5 @@ fetch_data (vector unsigned int *arg1_p, vector unsigned int *arg2_p) vector unsigned int arg_1 = *arg1_p; vector unsigned int arg_2 = *arg2_p; - return __builtin_vec_vcmpnez (arg_1, arg_2); /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' option" } */ + return __builtin_vec_vcmpnez (arg_1, arg_2); /* { dg-error "'__builtin_altivec_vcmpnezw' requires the '-mcpu=power9' and '-mvsx' options" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c index 6ee066d..dd0d337 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c @@ -9,5 +9,5 @@ count_leading_zero_byte_bits (vector unsigned char *arg1_p) { vector unsigned char arg_1 = *arg1_p; - return __builtin_vec_vclzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vclzlsbb_v16qi' requires the '-mcpu=power9' option" } */ + return __builtin_vec_vclzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vclzlsbb_v16qi' requires the '-mcpu=power9' and '-mvsx' options" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c index ecd0add..22c55ef 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c @@ -9,5 +9,5 @@ count_trailing_zero_byte_bits (vector unsigned char *arg1_p) { vector unsigned char arg_1 = *arg1_p; - return __builtin_vec_vctzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vctzlsbb_v16qi' requires the '-mcpu=power9' option" } */ + return __builtin_vec_vctzlsbb (arg_1); /* { dg-error "'__builtin_altivec_vctzlsbb_v16qi' requires the '-mcpu=power9' and '-mvsx' options" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c index 1cfed57..0f601fb 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c @@ -13,5 +13,5 @@ int fetch_data (float *address, size_t length) { - return __builtin_vec_lxvl (address, length); /* { dg-warning "'__builtin_vec_lxvl'" } */ + return __builtin_vec_lxvl (address, length); /* { dg-error "'__builtin_vsx_lxvl' requires the" } */ } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c index 3a51132..f30d49c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c @@ -13,5 +13,5 @@ store_data (vector double *datap, double *address, size_t length) { vector double data = *datap; - __builtin_vec_stxvl (data, address, length); /* { dg-error "'__builtin_vec_stxvl' is not supported in this compiler configuration" } */ + __builtin_vec_stxvl (data, address, length); /* { dg-error "'__builtin_altivec_stxvl' requires the" } */ } |