diff options
Diffstat (limited to 'gcc')
29 files changed, 163 insertions, 159 deletions
diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c index 9f61dc4..1ea6de8 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-1.c @@ -8,5 +8,5 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c index 09048e5..389b114 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-10.c @@ -11,11 +11,11 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c index 8b058e3..07d8de7 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-13.c @@ -7,15 +7,15 @@ foo (void) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]*%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]*%xmm0, %xmm\[0-9\]+" 15 { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ +/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ +/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 15 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c index d4eaaf7..55a272c 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-14.c @@ -8,12 +8,12 @@ foo (void) /* { dg-final { scan-assembler-times "vzeroall" 1 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c index dd3bb90..d0e975c 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-15.c @@ -10,5 +10,5 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c index e2274f6..d41a255 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-16.c @@ -10,5 +10,5 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c index 7f5d153..c79fcd3 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-17.c @@ -9,5 +9,5 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" { target ia32 } } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" { target ia32 } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c index fe13d2b..6f90723 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-18.c @@ -8,6 +8,6 @@ foo (float z, float y, float x) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm1, %xmm2" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c index 205a532..491d2d5 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-19.c @@ -8,5 +8,5 @@ foo (float z, float y, float x) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm2, %xmm2" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm2, %xmm2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c index e046684..52406fc 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-2.c @@ -8,12 +8,12 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c index 4be8ff6..ccd4917 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-20.c @@ -8,16 +8,16 @@ foo (float z, float y, float x) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm0, %xmm0" { target { ia32 } } } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]*%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ -/* { dg-final { scan-assembler-times "movaps\[ \t\]*%xmm1, %xmm\[0-9\]+" 14 { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" { target { ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm0, %xmm\[0-9\]+" 7 { target { ia32 } } } } */ +/* { dg-final { scan-assembler-times "movaps\[ \t\]+%xmm1, %xmm\[0-9\]+" 14 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c index 0eb34e0..b3570f3 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-21.c @@ -9,6 +9,6 @@ foo (float z, float y, float x) } /* { dg-final { scan-assembler-not "vzeroall" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm1, %xmm1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm1, %xmm2" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm1, %xmm1" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm1, %xmm2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c index 0258c70..b253420 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-22.c @@ -8,14 +8,14 @@ foo (void) /* { dg-final { scan-assembler "vzeroall" } } */ /* { dg-final { scan-assembler-times "fldz" 8 } } */ -/* { dg-final { scan-assembler-times "fstp" 8 } } */ +/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c index 0625eb5..69d42d7 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c @@ -8,22 +8,22 @@ foo (void) /* { dg-final { scan-assembler "vzeroall" } } */ /* { dg-final { scan-assembler-times "fldz" 8 } } */ -/* { dg-final { scan-assembler-times "fstp" 8 } } */ +/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kxorw\[ \t\]*%k0, %k0, %k0" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k1" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k2" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k3" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k4" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k5" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k6" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "kmovw\[ \t\]*%k0, %k7" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kxorw\[ \t\]+%k0, %k0, %k0" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k1" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k2" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k3" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k4" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k5" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k6" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "kmovw\[ \t\]+%k0, %k7" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-24.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-24.c index 208633e..5c68287 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-24.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-24.c @@ -7,4 +7,4 @@ foo (int x) return x; } -/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-25.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-25.c index 21e82c6..902d3ac 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-25.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-25.c @@ -7,4 +7,4 @@ foo (int x) return x; } -/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c index 293d2fe..8fb5299 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-26.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all-arg" } */ +/* { dg-options "-O2 -msse2 -fzero-call-used-regs=all-arg" } */ int foo (int x) @@ -7,17 +7,17 @@ foo (int x) return x; } -/* { dg-final { scan-assembler "xorl\[ \t\]*%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %esi" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %edi" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r8d" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r9d" } } */ -/* { dg-final { scan-assembler "pxor\[ \t\]*%xmm0, %xmm0" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm1" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm2" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm3" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm4" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm5" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm6" } } */ -/* { dg-final { scan-assembler "movaps\[ \t\]*%xmm0, %xmm7" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%xmm0, %xmm0" } } */ +/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm1" } } */ +/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm2" } } */ +/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm3" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm4" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm5" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm6" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movaps\[ \t\]+%xmm0, %xmm7" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c index c34e6af..26ceacf 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-27.c @@ -7,9 +7,9 @@ foo (int x) return x; } -/* { dg-final { scan-assembler "xorl\[ \t\]*%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %esi" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %edi" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r8d" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r9d" } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c index 48b1f01..044e4af 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-28.c @@ -2,15 +2,17 @@ /* { dg-options "-O2 -mmmx -fzero-call-used-regs=all" } */ /* { dg-require-effective-target ia32 } */ +typedef int __v2si __attribute__ ((vector_size (8))); + __v2si ret_mmx (void) { return (__v2si) { 123, 345 }; } -/* { dg-final { scan-assembler "pxor\[ \t\]*%mm1, %mm1" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm2" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm3" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm4" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm5" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm6" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm7" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */ +/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */ +/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm3" } } */ +/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm4" } } */ +/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm5" } } */ +/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm6" } } */ +/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm7" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-29.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-29.c index 8b5e1cd..6270645 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-29.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-29.c @@ -7,4 +7,4 @@ long double ret_x87 (void) } /* { dg-final { scan-assembler-times "fldz" 7 } } */ -/* { dg-final { scan-assembler-times "fstp" 7 } } */ +/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 7 } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c index de71223..89e69b8 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-3.c @@ -8,5 +8,5 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-30.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-30.c index 2a6f38f..c4e9930 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-30.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-30.c @@ -1,5 +1,5 @@ /* { dg-do compile { target *-*-linux* } } */ -/* { dg-options "-O2 -fzero-call-used-regs=all" } */ +/* { dg-options "-O2 -fzero-call-used-regs=all" } */ _Complex long double ret_x87_cplx (void) { @@ -7,6 +7,6 @@ _Complex long double ret_x87_cplx (void) } /* { dg-final { scan-assembler-times "fldz" 8 { target ia32 } } } */ -/* { dg-final { scan-assembler-times "fstp" 8 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 8 { target ia32 } } } */ /* { dg-final { scan-assembler-times "fldz" 6 { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler-times "fstp" 6 { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "fstp\[ \t\]+%st\\(0\\)" 6 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c index df71286..afa8b33 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-31.c @@ -2,11 +2,13 @@ /* { dg-options "-O2 -mmmx -fzero-call-used-regs=all-arg" } */ /* { dg-require-effective-target ia32 } */ +typedef int __v2si __attribute__ ((vector_size (8))); + __v2si ret_mmx (void) { return (__v2si) { 123, 345 }; } -/* { dg-final { scan-assembler "pxor\[ \t\]*%mm1, %mm1" } } */ -/* { dg-final { scan-assembler "movq\[ \t\]*%mm1, %mm2" } } */ -/* { dg-final { scan-assembler-not "movq\[ \t\]*%mm1, %mm\[34567\]" } } */ +/* { dg-final { scan-assembler "pxor\[ \t\]+%mm1, %mm1" } } */ +/* { dg-final { scan-assembler "movq\[ \t\]+%mm1, %mm2" } } */ +/* { dg-final { scan-assembler-not "movq\[ \t\]+%mm1, %mm\[34567\]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c index ccfa441..1e98d17 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-4.c @@ -10,5 +10,5 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c index 6b46ca3..56aecda 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-5.c @@ -9,12 +9,12 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%eax, %eax" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%eax, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%eax, %eax" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%eax, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c index 0680f38..fa83185 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-6.c @@ -10,5 +10,5 @@ foo (void) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" } } */ -/* { dg-final { scan-assembler-not "movl\[ \t\]*%" } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" } } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]+%" } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c index 534defa..0444a21 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-7.c @@ -9,5 +9,5 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" { target ia32 } } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" { target ia32 } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c index 477bb19..75356db 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-8.c @@ -9,11 +9,11 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%edx, %edx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %ecx" } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %esi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %edi" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r8d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r9d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r10d" { target { ! ia32 } } } } */ -/* { dg-final { scan-assembler "movl\[ \t\]*%edx, %r11d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edx, %edx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %ecx" } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %esi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r8d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r9d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r10d" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "movl\[ \t\]+%edx, %r11d" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c index a305a60..64755b00 100644 --- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-9.c @@ -11,5 +11,5 @@ foo (int x) /* { dg-final { scan-assembler-not "vzeroall" } } */ /* { dg-final { scan-assembler-not "%xmm" } } */ -/* { dg-final { scan-assembler-not "xorl\[ \t\]*%" { target ia32 } } } */ -/* { dg-final { scan-assembler "xorl\[ \t\]*%edi, %edi" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-not "xorl\[ \t\]+%" { target ia32 } } } */ +/* { dg-final { scan-assembler "xorl\[ \t\]+%edi, %edi" { target { ! ia32 } } } } */ |