diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 39 |
2 files changed, 30 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b046a72..900ca82 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2000-07-03 Nick Clifton <nickc@cygnus.com> + + * config/arm/arm.md: Fix post increment and pre increment + peepholes so that they do not generate UNPREDICATBLE opcodes. + (ie ones where the increment clobbers the source/destination). + 2000-07-01 Marek Michalkiewicz <marekm@linux.org.pl> * config/avr/avr.c (out_adj_frame_ptr): Make "frame pointer diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 9cf0d24..0b75a0e 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -7701,15 +7701,20 @@ ; It doesn't seem worth adding peepholes for anything but the most common ; cases since, unlike combine, the increment must immediately follow the load ; for this pattern to match. -; When loading we must watch to see that the base register isn't trampled by -; the load. In such cases this isn't a post-inc expression. +; We must watch to see that the source/destination register isn't also the +; same as the base address register, and that if the index is a register, +; that it is not the same as the base address register. In such cases the +; instruction that we would generate would have UNPREDICTABLE behaviour so +; we cannot use it. (define_peephole [(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r")) (match_operand:QI 2 "s_register_operand" "r")) (set (match_dup 0) (plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))] - "TARGET_ARM" + "TARGET_ARM + && (REGNO (operands[2]) != REGNO (operands[0])) + && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))" "str%?b\\t%2, [%0], %1") (define_peephole @@ -7717,9 +7722,9 @@ (mem:QI (match_operand:SI 1 "s_register_operand" "+r"))) (set (match_dup 1) (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))] - "TARGET_ARM && REGNO(operands[0]) != REGNO(operands[1]) - && (GET_CODE (operands[2]) != REG - || REGNO(operands[0]) != REGNO (operands[2]))" + "TARGET_ARM + && REGNO (operands[0]) != REGNO(operands[1]) + && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))" "ldr%?b\\t%0, [%1], %2") (define_peephole @@ -7727,7 +7732,9 @@ (match_operand:SI 2 "s_register_operand" "r")) (set (match_dup 0) (plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))] - "TARGET_ARM" + "TARGET_ARM + && (REGNO (operands[2]) != REGNO (operands[0])) + && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))" "str%?\\t%2, [%0], %1") (define_peephole @@ -7738,9 +7745,8 @@ "TARGET_ARM && (! BYTES_BIG_ENDIAN) && ! TARGET_MMU_TRAPS - && REGNO(operands[0]) != REGNO(operands[1]) - && (GET_CODE (operands[2]) != REG - || REGNO(operands[0]) != REGNO (operands[2]))" + && REGNO (operands[0]) != REGNO(operands[1]) + && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))" "ldr%?\\t%0, [%1], %2\\t%@ loadhi") (define_peephole @@ -7749,9 +7755,8 @@ (set (match_dup 1) (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))] "TARGET_ARM - && REGNO(operands[0]) != REGNO(operands[1]) - && (GET_CODE (operands[2]) != REG - || REGNO(operands[0]) != REGNO (operands[2]))" + && REGNO (operands[0]) != REGNO(operands[1]) + && (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))" "ldr%?\\t%0, [%1], %2") (define_peephole @@ -7759,7 +7764,9 @@ (match_operand:SI 1 "index_operand" "rJ"))) (match_operand:QI 2 "s_register_operand" "r")) (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))] - "TARGET_ARM" + "TARGET_ARM + && (REGNO (operands[2]) != REGNO (operands[0])) + && (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))" "str%?b\\t%2, [%0, %1]!") (define_peephole @@ -7770,7 +7777,9 @@ (match_operand:QI 3 "s_register_operand" "r")) (set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)]) (match_dup 2)))] - "TARGET_ARM" + "TARGET_ARM + && (REGNO (operands[3]) != REGNO (operands[2])) + && (REGNO (operands[0]) != REGNO (operands[2]))" "str%?b\\t%3, [%2, %0%S4]!") ; This pattern is never tried by combine, so do it as a peephole |