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-rw-r--r--gcc/ChangeLog26
-rw-r--r--gcc/config/mips/24k.md16
-rw-r--r--gcc/config/mips/3000.md2
-rw-r--r--gcc/config/mips/4000.md2
-rw-r--r--gcc/config/mips/4100.md4
-rw-r--r--gcc/config/mips/4130.md6
-rw-r--r--gcc/config/mips/4300.md4
-rw-r--r--gcc/config/mips/4600.md4
-rw-r--r--gcc/config/mips/5000.md4
-rw-r--r--gcc/config/mips/5400.md6
-rw-r--r--gcc/config/mips/5500.md4
-rw-r--r--gcc/config/mips/7000.md6
-rw-r--r--gcc/config/mips/9000.md4
-rw-r--r--gcc/config/mips/generic.md2
-rw-r--r--gcc/config/mips/mips.md19
-rw-r--r--gcc/config/mips/sb1.md4
-rw-r--r--gcc/config/mips/sr71k.md4
17 files changed, 71 insertions, 46 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 145839c..d620fc4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,29 @@
+2005-05-11 David Ung <davidu@mips.com>
+
+ * config/mips/mips.md (type): Add imul3.
+ (length, hazard, may_clobber_hilo): Check for imul3.
+ (mulsi3_mult3, muldi3_mult3, *muls, <su>mulsi3_highpart_mulhi_internal)
+ (*<su>mulsi3_highpart_neg_mulhi_internal): Set attr to imul3.
+ * config/mips/24k.md (r24k_int_mul3): Enable this reservation
+ for a 3 operand mul and its bypasses.
+ * config/mips/3000.md (r3k_imul): Add imul3 to reservations.
+ * config/mips/4000.md (r4k_imul): Likewise.
+ * config/mips/4100.md (r4100_imul_si, r4100_imul_di): Likewise.
+ * config/mips/4130.md (vr4130_class, vr4130_mulsi)
+ (vr4130_muldi): Likewise.
+ * config/mips/4300.md (r4300_imul_si, r4300_imul_di): Likewise.
+ * config/mips/4600.md (r4600_imul, r4650_imul): Likewise.
+ * config/mips/5000.md (r5k_imul_si, r5k_imul_di): Likewise.
+ * config/mips/5400.md (ir_vr54_imul_si, ir_vr54_imul_di)
+ (ir_vr54_imadd_si): Likewise.
+ * config/mips/5500.md (ir_vr55_imul_si, ir_vr55_imul_di): Likewise.
+ * config/mips/7000.md (rm7_impy_si_mult, rm7_impy_si_mul)
+ (rm7_impy_di): Likewise.
+ * config/mips/9000.md (rm9k_mulsi, rm9k_muldi): Likewise.
+ * config/mips/generic.md (generic_imul): Likewise.
+ * config/mips/sb1.md (ir_sb1_mulsi, ir_sb1_muldi): Likewise.
+ * config/mips/sr71k.md (ir_sr70_imul_si, ir_sr70_imul_di): Likewise.
+
2005-05-11 J"orn Rennecke <joern.rennecke@st.com>
PR middle-end/20371:
diff --git a/gcc/config/mips/24k.md b/gcc/config/mips/24k.md
index 4f6d50f..feac2fe0 100644
--- a/gcc/config/mips/24k.md
+++ b/gcc/config/mips/24k.md
@@ -87,12 +87,10 @@
"r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
;; mul - delivers result to gpr in 5 cycles
-;; (disabled for now until we introduce the 3 operand mul into the general
-;; patterns).
-;;(define_insn_reservation "r24k_int_mul3" 5
-;; (and (eq_attr "cpu" "24k,24kx")
-;; (eq_attr "type" "imul3"))
-;; "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
+(define_insn_reservation "r24k_int_mul3" 5
+ (and (eq_attr "cpu" "24k,24kx")
+ (eq_attr "type" "imul3"))
+ "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
(define_insn_reservation "r24k_int_mfhilo" 5
@@ -186,9 +184,9 @@
;; mul3->next use : 5 cycles (default)
;; mul3->l/s base : 6 cycles
;; mul3->prefetch : 6 cycles
-;;(define_bypass 6 "r24k_int_mul3" "r24k_int_load")
-;;(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
-;;(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
+(define_bypass 6 "r24k_int_mul3" "r24k_int_load")
+(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
+(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
;; mfhilo->next use : 5 cycles (default)
;; mfhilo->l/s base : 6 cycles
diff --git a/gcc/config/mips/3000.md b/gcc/config/mips/3000.md
index f9a8291..bc748d8 100644
--- a/gcc/config/mips/3000.md
+++ b/gcc/config/mips/3000.md
@@ -29,7 +29,7 @@
(define_insn_reservation "r3k_imul" 12
(and (eq_attr "cpu" "r3000,r3900")
- (eq_attr "type" "imul,imadd"))
+ (eq_attr "type" "imul,imul3,imadd"))
"imuldiv*12")
(define_insn_reservation "r3k_idiv" 35
diff --git a/gcc/config/mips/4000.md b/gcc/config/mips/4000.md
index 97149a5..4fcd240 100644
--- a/gcc/config/mips/4000.md
+++ b/gcc/config/mips/4000.md
@@ -24,7 +24,7 @@
(define_insn_reservation "r4k_imul" 10
(and (eq_attr "cpu" "r4000")
- (eq_attr "type" "imul,imadd"))
+ (eq_attr "type" "imul,imul3,imadd"))
"imuldiv*10")
(define_insn_reservation "r4k_idiv" 69
diff --git a/gcc/config/mips/4100.md b/gcc/config/mips/4100.md
index 2a0dcdd..5601c97 100644
--- a/gcc/config/mips/4100.md
+++ b/gcc/config/mips/4100.md
@@ -29,13 +29,13 @@
(define_insn_reservation "r4100_imul_si" 1
(and (eq_attr "cpu" "r4100,r4120")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"imuldiv")
(define_insn_reservation "r4100_imul_di" 4
(and (eq_attr "cpu" "r4100,r4120")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"imuldiv*4")
diff --git a/gcc/config/mips/4130.md b/gcc/config/mips/4130.md
index eddc405..6feeab3 100644
--- a/gcc/config/mips/4130.md
+++ b/gcc/config/mips/4130.md
@@ -55,7 +55,7 @@
(cond [(eq_attr "type" "load,store")
(const_string "mem")
- (eq_attr "type" "mfhilo,mthilo,imul,imadd,idiv")
+ (eq_attr "type" "mfhilo,mthilo,imul,imul3,imadd,idiv")
(const_string "mul")]
(const_string "alu")))
@@ -95,7 +95,7 @@
;; use "mtlo; macc" instead of "mult; mflo".
(define_insn_reservation "vr4130_mulsi" 4
(and (eq_attr "cpu" "r4130")
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "SI")))
"vr4130_muldiv + (vr4130_mulpre * 2)")
@@ -103,7 +103,7 @@
;; after 3 cycles.
(define_insn_reservation "vr4130_muldi" 6
(and (eq_attr "cpu" "r4130")
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"(vr4130_muldiv * 3) + (vr4130_mulpre * 4)")
diff --git a/gcc/config/mips/4300.md b/gcc/config/mips/4300.md
index d663f16..0b319ea 100644
--- a/gcc/config/mips/4300.md
+++ b/gcc/config/mips/4300.md
@@ -29,13 +29,13 @@
(define_insn_reservation "r4300_imul_si" 5
(and (eq_attr "cpu" "r4300")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"imuldiv*5")
(define_insn_reservation "r4300_imul_di" 8
(and (eq_attr "cpu" "r4300")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"imuldiv*8")
diff --git a/gcc/config/mips/4600.md b/gcc/config/mips/4600.md
index 58b3099..7892200 100644
--- a/gcc/config/mips/4600.md
+++ b/gcc/config/mips/4600.md
@@ -27,7 +27,7 @@
(define_insn_reservation "r4600_imul" 10
(and (eq_attr "cpu" "r4600")
- (eq_attr "type" "imul,imadd"))
+ (eq_attr "type" "imul,imul3,imadd"))
"imuldiv*10")
(define_insn_reservation "r4600_idiv" 42
@@ -38,7 +38,7 @@
(define_insn_reservation "r4650_imul" 4
(and (eq_attr "cpu" "r4650")
- (eq_attr "type" "imul,imadd"))
+ (eq_attr "type" "imul,imul3,imadd"))
"imuldiv*4")
(define_insn_reservation "r4650_idiv" 36
diff --git a/gcc/config/mips/5000.md b/gcc/config/mips/5000.md
index 9b02ac3..b00e707 100644
--- a/gcc/config/mips/5000.md
+++ b/gcc/config/mips/5000.md
@@ -29,13 +29,13 @@
(define_insn_reservation "r5k_imul_si" 5
(and (eq_attr "cpu" "r5000")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"imuldiv*5")
(define_insn_reservation "r5k_imul_di" 9
(and (eq_attr "cpu" "r5000")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"imuldiv*9")
diff --git a/gcc/config/mips/5400.md b/gcc/config/mips/5400.md
index f39dc88..8571308 100644
--- a/gcc/config/mips/5400.md
+++ b/gcc/config/mips/5400.md
@@ -65,19 +65,19 @@
(define_insn_reservation "ir_vr54_imul_si" 3
(and (eq_attr "cpu" "r5400")
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "SI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imul_di" 4
(and (eq_attr "cpu" "r5400")
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imadd_si" 3
(and (eq_attr "cpu" "r5400")
- (eq_attr "type" "imul"))
+ (eq_attr "type" "imul,imul3"))
"vr54_mac")
(define_insn_reservation "ir_vr54_idiv_si" 42
diff --git a/gcc/config/mips/5500.md b/gcc/config/mips/5500.md
index fbcc6f6..881cbcb4 100644
--- a/gcc/config/mips/5500.md
+++ b/gcc/config/mips/5500.md
@@ -78,7 +78,7 @@
;; latency of {mul,mult}->{mfhi,mflo}.
(define_insn_reservation "ir_vr55_imul_si" 5
(and (eq_attr "cpu" "r5500")
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "SI")))
"vr55_mac")
@@ -91,7 +91,7 @@
;; between it and the dmult.
(define_insn_reservation "ir_vr55_imul_di" 9
(and (eq_attr "cpu" "r5500")
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"vr55_mac*4")
diff --git a/gcc/config/mips/7000.md b/gcc/config/mips/7000.md
index ec75ffc..0323472 100644
--- a/gcc/config/mips/7000.md
+++ b/gcc/config/mips/7000.md
@@ -111,7 +111,7 @@
(define_insn_reservation "rm7_impy_si_mult" 5
(and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(and (eq_attr "mode" "SI")
(match_operand 0 "hilo_operand"))))
"rm7_impydiv+(rm7_impydiv_iter*3)")
@@ -119,13 +119,13 @@
;; There are an additional 2 stall cycles.
(define_insn_reservation "rm7_impy_si_mul" 2
(and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(and (eq_attr "mode" "SI")
(not (match_operand 0 "hilo_operand")))))
"rm7_impydiv")
(define_insn_reservation "rm7_impy_di" 9 (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"rm7_impydiv+(rm7_impydiv_iter*8)")
diff --git a/gcc/config/mips/9000.md b/gcc/config/mips/9000.md
index b5501c3..4aa3ff6 100644
--- a/gcc/config/mips/9000.md
+++ b/gcc/config/mips/9000.md
@@ -64,13 +64,13 @@
;; This applies to both 'mul' and 'mult'.
(define_insn_reservation "rm9k_mulsi" 3
(and (eq_attr "cpu" "r9000")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "!DI")))
"rm9k_f_int")
(define_insn_reservation "rm9k_muldi" 7
(and (eq_attr "cpu" "r9000")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"rm9k_f_int + rm9k_imul * 7")
diff --git a/gcc/config/mips/generic.md b/gcc/config/mips/generic.md
index 237272e..7ddb0bd 100644
--- a/gcc/config/mips/generic.md
+++ b/gcc/config/mips/generic.md
@@ -48,7 +48,7 @@
"imuldiv*3")
(define_insn_reservation "generic_imul" 17
- (eq_attr "type" "imul,imadd")
+ (eq_attr "type" "imul,imul3,imadd")
"imuldiv*17")
(define_insn_reservation "generic_idiv" 38
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 90a7305..1473f55 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -126,7 +126,8 @@
;; slt set less than instructions
;; clz the clz and clo instructions
;; trap trap if instructions
-;; imul integer multiply
+;; imul integer multiply 2 operands
+;; imul3 integer multiply 3 operands
;; imadd integer multiply-add
;; idiv integer divide
;; fmove floating point register move
@@ -148,7 +149,7 @@
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
- "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
+ "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
@@ -253,7 +254,7 @@
;; VR4120 errata MD(4): if there are consecutive dmult instructions,
;; the result of the second one is missed. The assembler should work
;; around this by inserting a nop after the first dmult.
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(and (eq_attr "mode" "DI")
(ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
(const_int 8)
@@ -317,7 +318,7 @@
;; True if an instruction might assign to hi or lo when reloaded.
;; This is used by the TUNE_MACC_CHAINS code.
(define_attr "may_clobber_hilo" "no,yes"
- (if_then_else (eq_attr "type" "imul,imadd,idiv,mthilo")
+ (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
(const_string "yes")
(const_string "no")))
@@ -967,7 +968,7 @@
return "mul\t%0,%1,%2";
return "mult\t%0,%1,%2";
}
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul3,imul")
(set_attr "mode" "SI")])
(define_insn "muldi3_mult3"
@@ -978,7 +979,7 @@
(clobber (match_scratch:DI 4 "=l"))]
"TARGET_64BIT && GENERATE_MULT3_DI"
"dmult\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul3")
(set_attr "mode" "DI")])
;; If a register gets allocated to LO, and we spill to memory, the reload
@@ -1400,7 +1401,7 @@
"@
muls\t$0,%1,%2
muls\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
@@ -1586,7 +1587,7 @@
"@
mult<u>\t%1,%2
mulhi<u>\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
@@ -1604,7 +1605,7 @@
"@
mulshi<u>\t%.,%1,%2
mulshi<u>\t%0,%1,%2"
- [(set_attr "type" "imul")
+ [(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md
index 3ab0333..b1b085f 100644
--- a/gcc/config/mips/sb1.md
+++ b/gcc/config/mips/sb1.md
@@ -296,7 +296,7 @@
(define_insn_reservation "ir_sb1_mulsi" 3
(and (eq_attr "cpu" "sb1")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"sb1_ex1+sb1_mul")
@@ -305,7 +305,7 @@
(define_insn_reservation "ir_sb1_muldi" 4
(and (eq_attr "cpu" "sb1")
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "imul,imul3")
(eq_attr "mode" "DI")))
"sb1_ex1+sb1_mul, sb1_mul")
diff --git a/gcc/config/mips/sr71k.md b/gcc/config/mips/sr71k.md
index d40e27e..9ccfc59 100644
--- a/gcc/config/mips/sr71k.md
+++ b/gcc/config/mips/sr71k.md
@@ -209,14 +209,14 @@
(define_insn_reservation "ir_sr70_imul_si"
4
(and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "SI")))
"ri_alux,ipu_alux,ipu_macc_iter")
(define_insn_reservation "ir_sr70_imul_di"
6
(and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "imul,imadd")
+ (and (eq_attr "type" "imul,imul3,imadd")
(eq_attr "mode" "DI")))
"ri_alux,ipu_alux,(ipu_macc_iter*3)")
generated by cgit v1.1 at 2025-05-28 15:22:18 +0000