diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/darwin.md | 27 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 105 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 7 |
4 files changed, 114 insertions, 35 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 99a6b00..ebb7cbc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2019-10-17 Iain Sandoe <iain@sandoe.co.uk> + + PR target/65342 + * config/rs6000/darwin.md (movdi_low, movsi_low_st): Delete. + (movdi_low_st): Delete. + * config/rs6000/rs6000.c + (darwin_rs6000_legitimate_lo_sum_const_p): New. + (mem_operand_gpr): Validate Mach-O LO_SUM cases separately. + * config/rs6000/rs6000.md (movsi_low): Delete. + 2019-10-17 Jason Merrill <jason@redhat.com> * gimplify.h (get_initialized_tmp_var): Add default argument to diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index 3994447..16f710b 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -122,33 +122,6 @@ You should have received a copy of the GNU General Public License [(set_attr "type" "store")]) ;; 64-bit MachO load/store support -(define_insn "movdi_low" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,*!d") - (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") - (match_operand 2 "" ""))))] - "TARGET_MACHO && TARGET_64BIT" - "@ - ld %0,lo16(%2)(%1) - lfd %0,lo16(%2)(%1)" - [(set_attr "type" "load")]) - -(define_insn "movsi_low_st" - [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand 2 "" ""))) - (match_operand:SI 0 "gpc_reg_operand" "r"))] - "TARGET_MACHO && ! TARGET_64BIT" - "stw %0,lo16(%2)(%1)" - [(set_attr "type" "store")]) - -(define_insn "movdi_low_st" - [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") - (match_operand 2 "" ""))) - (match_operand:DI 0 "gpc_reg_operand" "r,*!d"))] - "TARGET_MACHO && TARGET_64BIT" - "@ - std %0,lo16(%2)(%1) - stfd %0,lo16(%2)(%1)" - [(set_attr "type" "store")]) ;; Mach-O PIC. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a129137d..5876714 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -7329,6 +7329,103 @@ address_offset (rtx op) return NULL_RTX; } +/* This tests that a lo_sum {constant, symbol, symbol+offset} is valid for + the mode. If we can't find (or don't know) the alignment of the symbol + we assume (optimistically) that it's sufficiently aligned [??? maybe we + should be pessimistic]. Offsets are validated in the same way as for + reg + offset. */ +static bool +darwin_rs6000_legitimate_lo_sum_const_p (rtx x, machine_mode mode) +{ + /* We should not get here with this. */ + gcc_checking_assert (! mode_supports_dq_form (mode)); + + if (GET_CODE (x) == CONST) + x = XEXP (x, 0); + + if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_MACHOPIC_OFFSET) + x = XVECEXP (x, 0, 0); + + rtx sym = NULL_RTX; + unsigned HOST_WIDE_INT offset = 0; + + if (GET_CODE (x) == PLUS) + { + sym = XEXP (x, 0); + if (! SYMBOL_REF_P (sym)) + return false; + if (!CONST_INT_P (XEXP (x, 1))) + return false; + offset = INTVAL (XEXP (x, 1)); + } + else if (SYMBOL_REF_P (x)) + sym = x; + else if (CONST_INT_P (x)) + offset = INTVAL (x); + else if (GET_CODE (x) == LABEL_REF) + offset = 0; // We assume code labels are Pmode aligned + else + return false; // not sure what we have here. + + /* If we don't know the alignment of the thing to which the symbol refers, + we assume optimistically it is "enough". + ??? maybe we should be pessimistic instead. */ + unsigned align = 0; + + if (sym) + { + tree decl = SYMBOL_REF_DECL (sym); +#if TARGET_MACHO + if (MACHO_SYMBOL_INDIRECTION_P (sym)) + /* The decl in an indirection symbol is the original one, which might + be less aligned than the indirection. Our indirections are always + pointer-aligned. */ + ; + else +#endif + if (decl && DECL_ALIGN (decl)) + align = DECL_ALIGN_UNIT (decl); + } + + unsigned int extra = 0; + switch (mode) + { + case E_DFmode: + case E_DDmode: + case E_DImode: + /* If we are using VSX scalar loads, restrict ourselves to reg+reg + addressing. */ + if (VECTOR_MEM_VSX_P (mode)) + return false; + + if (!TARGET_POWERPC64) + extra = 4; + else if ((offset & 3) || (align & 3)) + return false; + break; + + case E_TFmode: + case E_IFmode: + case E_KFmode: + case E_TDmode: + case E_TImode: + case E_PTImode: + extra = 8; + if (!TARGET_POWERPC64) + extra = 12; + else if ((offset & 3) || (align & 3)) + return false; + break; + + default: + break; + } + + /* We only care if the access(es) would cause a change to the high part. */ + offset = ((offset & 0xffff) ^ 0x8000) - 0x8000; + return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra); +} + /* Return true if the MEM operand is a memory operand suitable for use with a (full width, possibly multiple) gpr load/store. On powerpc64 this means the offset must be divisible by 4. @@ -7366,7 +7463,13 @@ mem_operand_gpr (rtx op, machine_mode mode) if (address_is_prefixed (addr, mode, NON_PREFIXED_DS)) return true; - /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */ + /* We need to look through Mach-O PIC unspecs to determine if a lo_sum is + really OK. Doing this early avoids teaching all the other machinery + about them. */ + if (TARGET_MACHO && GET_CODE (addr) == LO_SUM) + return darwin_rs6000_legitimate_lo_sum_const_p (XEXP (addr, 1), mode); + + /* Only allow offsettable addresses. See PRs 83969 and 84279. */ if (!rs6000_offsettable_memref_p (op, mode, false)) return false; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 2dca269..29dd616 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6894,13 +6894,6 @@ ;; do the load 16-bits at a time. We could do this by loading from memory, ;; and this is even supposed to be faster, but it is simpler not to get ;; integers in the TOC. -(define_insn "movsi_low" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand 2 "" ""))))] - "TARGET_MACHO && ! TARGET_64BIT" - "lwz %0,lo16(%2)(%1)" - [(set_attr "type" "load")]) ;; MR LA LWZ LFIWZX LXSIWZX ;; STW STFIWX STXSIWX LI LIS |