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-rw-r--r--gcc/ChangeLog14
-rw-r--r--gcc/config/i386/i386-builtin.def18
-rw-r--r--gcc/config/i386/i386.c19
-rw-r--r--gcc/testsuite/ChangeLog19
-rw-r--r--gcc/testsuite/gcc.target/i386/pr79568-1.c18
-rw-r--r--gcc/testsuite/gcc.target/i386/pr79568-2.c18
-rw-r--r--gcc/testsuite/gcc.target/i386/pr79568-3.c19
7 files changed, 105 insertions, 20 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 57857ee..a14d091 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2017-02-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/79568
+ * config/i386/i386.c (ix86_expand_builtin): Handle
+ OPTION_MASK_ISA_AVX512VL and OPTION_MASK_ISA_64BIT in
+ ix86_builtins_isa[fcode].isa as a requirement of those
+ flags and any other flag in the bitmask.
+ (ix86_init_mmx_sse_builtins): Use 0 instead of
+ ~OPTION_MASK_ISA_64BIT as mask.
+ * config/i386/i386-builtin.def (__builtin_ia32_rdtsc,
+ __builtin_ia32_rdtscp, __builtin_ia32_pause, __builtin_ia32_bsrsi,
+ __builtin_ia32_rdpmc, __builtin_ia32_rolqi, __builtin_ia32_rolhi,
+ __builtin_ia32_rorqi, __builtin_ia32_rorhi): Likewise.
+
2017-02-20 Matthew Fortune <matthew.fortune@imgtec.com>
PR target/78012
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 4b9442d..4ef4a01 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -88,9 +88,9 @@ BDESC_END (PCMPISTR, SPECIAL_ARGS)
/* Special builtins with variable number of arguments. */
BDESC_FIRST (special_args, SPECIAL_ARGS,
- ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID)
-BDESC (~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED)
-BDESC (~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID)
+ 0, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID)
+BDESC (0, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED)
+BDESC (0, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID)
/* 80387 (for use internally for atomic compound assignment). */
BDESC (0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID)
@@ -385,13 +385,13 @@ BDESC_END (SPECIAL_ARGS, ARGS)
/* Builtins with variable number of arguments. */
BDESC_FIRST (args, ARGS,
- ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT)
+ 0, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT)
BDESC (OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64)
-BDESC (~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT)
-BDESC (~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT)
-BDESC (~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT)
-BDESC (~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT)
-BDESC (~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT)
+BDESC (0, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT)
+BDESC (0, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT)
+BDESC (0, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT)
+BDESC (0, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT)
+BDESC (0, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT)
/* MMX */
BDESC (OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index fb0dca2..fe2dd6a 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -32078,11 +32078,11 @@ ix86_init_mmx_sse_builtins (void)
IX86_BUILTIN_SBB64);
/* Read/write FLAGS. */
- def_builtin (~OPTION_MASK_ISA_64BIT, "__builtin_ia32_readeflags_u32",
+ def_builtin (0, "__builtin_ia32_readeflags_u32",
UNSIGNED_FTYPE_VOID, IX86_BUILTIN_READ_FLAGS);
def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_ia32_readeflags_u64",
UINT64_FTYPE_VOID, IX86_BUILTIN_READ_FLAGS);
- def_builtin (~OPTION_MASK_ISA_64BIT, "__builtin_ia32_writeeflags_u32",
+ def_builtin (0, "__builtin_ia32_writeeflags_u32",
VOID_FTYPE_UNSIGNED, IX86_BUILTIN_WRITE_FLAGS);
def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_ia32_writeeflags_u64",
VOID_FTYPE_UINT64, IX86_BUILTIN_WRITE_FLAGS);
@@ -36726,9 +36726,18 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
Originally the builtin was not created if it wasn't applicable to the
current ISA based on the command line switches. With function specific
options, we need to check in the context of the function making the call
- whether it is supported. */
- if ((ix86_builtins_isa[fcode].isa
- && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
+ whether it is supported. Treat AVX512VL specially. For other flags,
+ if isa includes more than one ISA bit, treat those are requiring any
+ of them. For AVX512VL, require both AVX512VL and the non-AVX512VL
+ ISAs. Similarly for 64BIT, but we shouldn't be building such builtins
+ at all, -m64 is a whole TU option. */
+ if (((ix86_builtins_isa[fcode].isa
+ & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT))
+ && !(ix86_builtins_isa[fcode].isa
+ & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT)
+ & ix86_isa_flags))
+ || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512VL)
+ && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512VL))
|| (ix86_builtins_isa[fcode].isa2
&& !(ix86_builtins_isa[fcode].isa2 & ix86_isa_flags2)))
{
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ce53f01..c821a84 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,19 +1,26 @@
+2017-02-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/79568
+ * gcc.target/i386/pr79568-1.c: New test.
+ * gcc.target/i386/pr79568-2.c: New test.
+ * gcc.target/i386/pr79568-3.c: New test.
+
2017-02-16 Paul Thomas <pault@gcc.gnu.org>
PR fortran/79382
- * gfortran.dg/dtio_10.f90 : Change test of error message.
- * gfortran.dg/dtio_23.f90 : New test.
- * gfortran.dg/dtio_24.f90 : New test.
+ * gfortran.dg/dtio_10.f90: Change test of error message.
+ * gfortran.dg/dtio_23.f90: New test.
+ * gfortran.dg/dtio_24.f90: New test.
2017-02-20 Paul Thomas <pault@gcc.gnu.org>
PR fortran/79434
- * gfortran.dg/submodule_25.f08 : New test.
+ * gfortran.dg/submodule_25.f08: New test.
2017-02-19 Paul Thomas <pault@gcc.gnu.org>
PR fortran/79447
- * gfortran.dg/submodule_24.f08 : New test.
+ * gfortran.dg/submodule_24.f08: New test.
2017-02-19 Andre Vehreschild <vehre@gcc.gnu.org>
@@ -460,7 +467,7 @@
2017-02-07 Andrew Pinski <apinski@cavium.com>
- * gcc.target/aarch64/popcount.c : New Testcase.
+ * gcc.target/aarch64/popcount.c: New Testcase.
2017-02-07 Jakub Jelinek <jakub@redhat.com>
diff --git a/gcc/testsuite/gcc.target/i386/pr79568-1.c b/gcc/testsuite/gcc.target/i386/pr79568-1.c
new file mode 100644
index 0000000..92956d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr79568-1.c
@@ -0,0 +1,18 @@
+/* PR target/79568 */
+/* { dg-do compile } */
+/* { dg-options "-mno-avx512vl -mavx512bw -O2" } */
+
+#pragma GCC push_options
+#pragma GCC target ("avx512vl,avx512bw")
+void
+foo (char *x, char __attribute__ ((__vector_size__(32))) *y, int z)
+{
+ __builtin_ia32_storedquqi256_mask (x, *y, z);
+}
+#pragma GCC pop_options
+
+void
+bar (char *x, char __attribute__ ((__vector_size__(32))) *y, int z)
+{
+ __builtin_ia32_storedquqi256_mask (x, *y, z); /* { dg-error "needs isa option" } */
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr79568-2.c b/gcc/testsuite/gcc.target/i386/pr79568-2.c
new file mode 100644
index 0000000..a0ee8e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr79568-2.c
@@ -0,0 +1,18 @@
+/* PR target/79568 */
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-mno-lwp" } */
+
+#pragma GCC push_options
+#pragma GCC target ("lwp")
+void
+foo (unsigned long x, unsigned int y)
+{
+ __builtin_ia32_lwpval64 (x, y, 1);
+}
+#pragma GCC pop_options
+
+void
+bar (unsigned long x, unsigned int y)
+{
+ __builtin_ia32_lwpval64 (x, y, 1); /* { dg-error "needs isa option" } */
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr79568-3.c b/gcc/testsuite/gcc.target/i386/pr79568-3.c
new file mode 100644
index 0000000..c210162
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr79568-3.c
@@ -0,0 +1,19 @@
+/* PR target/79568 */
+/* { dg-do compile } */
+/* { dg-options "-mno-sahf -mno-mmx -mno-sse" } */
+/* { dg-additional-options "-march=i386" { target ia32 } } */
+
+#pragma GCC push_options
+#pragma GCC target ("sse")
+void
+foo (void)
+{
+ __builtin_ia32_pause ();
+}
+#pragma GCC pop_options
+
+void
+bar (void)
+{
+ __builtin_ia32_pause ();
+}
generated by cgit v1.1 at 2025-06-03 18:20:03 +0000