diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 21 | ||||
| -rw-r--r-- | gcc/config/rs6000/altivec.h | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-builtin.def | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-c.c | 72 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/altivec-35.c | 16 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c | 62 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c | 36 |
8 files changed, 222 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d279b39..1090656 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,24 @@ +2015-08-18 Bill Schmidt <wschmidt@vnet.linux.ibm.com> + + * config/rs6000/altivec.h (vec_adde): New define. + (vec_addec): Likewise. + (vec_double): Likewise. + (vec_bperm): Likewise. + (vec_gb): Likewise. + * config/rs6000/rs6000-builtin.def (ADDE): New + BU_ALTIVEC_OVERLOAD_3. + (ADDEC): Likewise. + (DOUBLE): New BU_VSX_OVERLOAD_1. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add new + entries for ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VEC_ADDE, + ALTIVEC_BUILTIN_VEC_ADDEC, ALTIVEC_BUILTIN_VEC_ANDC, + VSX_BUILTIN_VEC_DOUBLE, ALTIVEC_BUILTIN_VEC_MERGEH, + ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VEC_NOR, + ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VEC_XOR, + ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VEC_SEL, + P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_VEC_ORC, + and P8V_BUILTIN_VEC_VBPERMQ. + 2015-08-18 Jason Merrill <jason@redhat.com> * print-tree.c (print_node): Handle TREE_BINFO. diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 8efc119..3ef6bc8 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -100,6 +100,8 @@ typed builtins. */ #define vec_vaddfp __builtin_vec_vaddfp #define vec_addc __builtin_vec_addc +#define vec_adde __builtin_vec_adde +#define vec_addec __builtin_vec_addec #define vec_vaddsws __builtin_vec_vaddsws #define vec_vaddshs __builtin_vec_vaddshs #define vec_vaddsbs __builtin_vec_vaddsbs @@ -125,6 +127,7 @@ #define vec_cts __builtin_vec_cts #define vec_ctu __builtin_vec_ctu #define vec_cpsgn __builtin_vec_copysign +#define vec_double __builtin_vec_double #define vec_expte __builtin_vec_expte #define vec_floor __builtin_vec_floor #define vec_loge __builtin_vec_loge @@ -340,6 +343,7 @@ #define vec_vaddudm __builtin_vec_vaddudm #define vec_vadduqm __builtin_vec_vadduqm #define vec_vbpermq __builtin_vec_vbpermq +#define vec_bperm __builtin_vec_vbpermq #define vec_vclz __builtin_vec_vclz #define vec_cntlz __builtin_vec_vclz #define vec_vclzb __builtin_vec_vclzb @@ -351,6 +355,7 @@ #define vec_vsubecuq __builtin_vec_vsubecuq #define vec_vsubeuqm __builtin_vec_vsubeuqm #define vec_vgbbd __builtin_vec_vgbbd +#define vec_gb __builtin_vec_vgbbd #define vec_vmaxsd __builtin_vec_vmaxsd #define vec_vmaxud __builtin_vec_vmaxud #define vec_vminsd __builtin_vec_vminsd diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index fbc97ef..7beddf6 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -951,6 +951,8 @@ BU_ALTIVEC_X (VEC_EXT_V4SF, "vec_ext_v4sf", CONST) before we get to the point about classifying the builtin type. */ /* 3 argument Altivec overloaded builtins. */ +BU_ALTIVEC_OVERLOAD_3 (ADDE, "adde") +BU_ALTIVEC_OVERLOAD_3 (ADDEC, "addec") BU_ALTIVEC_OVERLOAD_3 (MADD, "madd") BU_ALTIVEC_OVERLOAD_3 (MADDS, "madds") BU_ALTIVEC_OVERLOAD_3 (MLADD, "mladd") @@ -1447,6 +1449,9 @@ BU_VSX_OVERLOAD_2 (XXMRGLW, "xxmrglw") BU_VSX_OVERLOAD_2 (XXSPLTD, "xxspltd") BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw") +/* 1 argument VSX overloaded builtin functions. */ +BU_VSX_OVERLOAD_1 (DOUBLE, "double") + /* VSX builtins that are handled as special cases. */ BU_VSX_OVERLOAD_X (LD, "ld") BU_VSX_OVERLOAD_X (ST, "st") diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index e2891cf..d45bc93 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -810,7 +810,25 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, + RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + { ALTIVEC_BUILTIN_VEC_ADDE, P8V_BUILTIN_VADDEUQM, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, + { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, + { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, + RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, @@ -980,6 +998,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, @@ -1237,6 +1257,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP, + RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 }, + { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP, + RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, @@ -1712,6 +1736,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, @@ -1770,6 +1796,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, @@ -1955,6 +1983,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, @@ -1997,6 +2027,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -2696,6 +2728,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -2957,6 +2991,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI }, + { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, @@ -3003,6 +3040,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, + RS6000_BTI_unsigned_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, @@ -3766,6 +3809,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, @@ -3781,6 +3826,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, + RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, @@ -3796,6 +3843,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, @@ -3811,6 +3860,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, @@ -3839,6 +3890,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, @@ -3854,6 +3907,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, + RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, @@ -3869,6 +3924,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, @@ -3884,6 +3941,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF, @@ -3904,6 +3963,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, @@ -3919,6 +3980,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, + RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, @@ -3934,6 +3997,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, @@ -3949,6 +4014,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF, @@ -3984,6 +4051,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI, + RS6000_BTI_unsigned_V16QI, 0 }, { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9ca2ce5..5ed17b9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2015-08-18 Bill Schmidt <wschmidt@vnet.linux.ibm.com> + + * gcc.target/powerpc/altivec-35.c: New test. + * gcc.target/powerpc/p8vector-builtin-8.c: New test. + * gcc.target/powerpc/vsx-vector-7.c: New test. + 2015-08-18 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> PR middle-end/36757 diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-35.c b/gcc/testsuite/gcc.target/powerpc/altivec-35.c new file mode 100644 index 0000000..6217c9f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-35.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mno-vsx -mno-power8-vector -O0" } */ + +#include <altivec.h> + +/* Test Altivec built-ins added for version 1.1 of ELFv2 ABI. */ + +vector signed int vsia, vsib; + +void foo (vector signed int *vsir) +{ + *vsir++ = vec_addc (vsia, vsib); +} + +/* { dg-final { scan-assembler-times "vaddcuw" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c new file mode 100644 index 0000000..4554099 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include <altivec.h> + +/* Test POWER8 vector built-ins added for version 1.1 of ELFv2 ABI. */ + +vector unsigned char vuca, vucb, vucc; +vector bool char vbca, vbcb; +vector bool short vbsa, vbsb; +vector bool int vbia, vbib; +vector signed long long vsla, vslb; +vector unsigned long long vula, vulb, vulc; +vector bool long long vbla, vblb, vblc; +vector signed __int128 vsxa, vsxb, vsxc; +vector unsigned __int128 vuxa, vuxb, vuxc; +vector double vda, vdb; + +void foo (vector unsigned char *vucr, + vector bool char *vbcr, + vector bool short *vbsr, + vector bool int *vbir, + vector unsigned long long *vulr, + vector bool long long *vblr, + vector signed __int128 *vsxr, + vector unsigned __int128 *vuxr, + vector double *vdr) +{ + *vsxr++ = vec_addc (vsxa, vsxb); + *vuxr++ = vec_addc (vuxa, vuxb); + *vsxr++ = vec_adde (vsxa, vsxb, vsxc); + *vuxr++ = vec_adde (vuxa, vuxb, vuxc); + *vsxr++ = vec_addec (vsxa, vsxb, vsxc); + *vuxr++ = vec_addec (vuxa, vuxb, vuxc); + *vulr++ = vec_bperm (vuxa, vucb); + *vbcr++ = vec_eqv (vbca, vbcb); + *vbir++ = vec_eqv (vbia, vbib); + *vblr++ = vec_eqv (vbla, vblb); + *vbsr++ = vec_eqv (vbsa, vbsb); + *vucr++ = vec_gb (vuca); + *vbcr++ = vec_nand (vbca, vbcb); + *vbir++ = vec_nand (vbia, vbib); + *vblr++ = vec_nand (vbla, vblb); + *vbsr++ = vec_nand (vbsa, vbsb); + *vbcr++ = vec_orc (vbca, vbcb); + *vbir++ = vec_orc (vbia, vbib); + *vblr++ = vec_orc (vbla, vblb); + *vbsr++ = vec_orc (vbsa, vbsb); + *vblr++ = vec_perm (vbla, vblb, vucc); +} + +/* { dg-final { scan-assembler-times "vaddcuq" 2 } } */ +/* { dg-final { scan-assembler-times "vaddeuqm" 2 } } */ +/* { dg-final { scan-assembler-times "vaddecuq" 2 } } */ +/* { dg-final { scan-assembler-times "vbpermq" 1 } } */ +/* { dg-final { scan-assembler-times "xxleqv" 4 } } */ +/* { dg-final { scan-assembler-times "vgbbd" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnand" 4 } } */ +/* { dg-final { scan-assembler-times "xxlorc" 4 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c new file mode 100644 index 0000000..66880fd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -mno-power8-vector -O2" } */ + +#include <altivec.h> + +/* Test VSX built-ins added for version 1.1 of ELFv2 ABI. */ + +vector bool long long vbla, vblb, vblc; +vector signed long long vsla; +vector unsigned long long vula, vulc; + +void foo (vector bool long long *vblr, + vector double *vdr) +{ + *vblr++ = vec_andc (vbla, vblb); + *vdr++ = vec_double (vsla); + *vdr++ = vec_double (vula); + *vblr++ = vec_mergeh (vbla, vblb); + *vblr++ = vec_mergel (vbla, vblb); + *vblr++ = vec_nor (vbla, vblb); + *vblr++ = vec_or (vbla, vblb); + *vblr++ = vec_sel (vbla, vblb, vblc); + *vblr++ = vec_sel (vbla, vblb, vulc); + *vblr++ = vec_xor (vbla, vblb); +} + +/* { dg-final { scan-assembler-times "xxlandc" 1 } } */ +/* { dg-final { scan-assembler-times "xvcvsxddp" 1 } } */ +/* { dg-final { scan-assembler-times "xvcvuxddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxpermdi .*,.*,.*,3" 1 } } */ +/* { dg-final { scan-assembler-times "xxpermdi .*,.*,.*,0" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 1 } } */ +/* { dg-final { scan-assembler-times "xxlor" 1 } } */ +/* { dg-final { scan-assembler-times "xxsel" 2 } } */ +/* { dg-final { scan-assembler-times "xxlxor" 1 } } */ |