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-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/doc/extend.texi2
2 files changed, 6 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9e75138..e0d251d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-02-05 Gerald Pfeifer <gerald@pfeifer.com>
+
+ * doc/extend.texi (x86 specific memory model extensions for
+ transactional memory): Simplify a phrase.
+
2017-02-05 Eric Botcazou <ebotcazou@adacore.com>
PR target/79353
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 20eba82..24e5053 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -10103,7 +10103,7 @@ after addition, conditional jump on carry etc.
@section x86-Specific Memory Model Extensions for Transactional Memory
The x86 architecture supports additional memory ordering flags
-to mark lock critical sections for hardware lock elision.
+to mark critical sections for hardware lock elision.
These must be specified in addition to an existing memory order to
atomic intrinsics.