diff options
Diffstat (limited to 'gcc')
22 files changed, 105 insertions, 53 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 55c0a04..f0f1abc 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1496,7 +1496,7 @@ (match_operand:<VM> 1 "vector_mask_operand") (any_int_unop:VI (match_operand:VI 2 "register_operand")) - (match_operand:VI 3 "register_operand")] + (match_operand:VI 3 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1512,7 +1512,7 @@ (match_operand:<VM> 1 "vector_mask_operand") (any_int_unop:VI (match_operand:VI 2 "register_operand")) - (match_operand:VI 3 "register_operand") + (match_operand:VI 3 "autovec_else_operand") (match_operand 4 "autovec_length_operand") (match_operand 5 "const_0_operand")] "TARGET_VECTOR" @@ -1534,7 +1534,7 @@ (match_operand:<VM> 1 "vector_mask_operand") (any_float_unop_nofrm:VF (match_operand:VF 2 "register_operand")) - (match_operand:VF 3 "register_operand")] + (match_operand:VF 3 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1550,7 +1550,7 @@ (match_operand:<VM> 1 "vector_mask_operand") (any_float_unop_nofrm:VF (match_operand:VF 2 "register_operand")) - (match_operand:VF 3 "register_operand") + (match_operand:VF 3 "autovec_else_operand") (match_operand 4 "autovec_length_operand") (match_operand 5 "const_0_operand")] "TARGET_VECTOR" @@ -1573,7 +1573,7 @@ (any_shift:VI (match_operand:VI 2 "register_operand") (match_operand:VI 3 "vector_shift_operand")) - (match_operand:VI 4 "register_operand")] + (match_operand:VI 4 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1590,7 +1590,7 @@ (any_shift:VI (match_operand:VI 2 "register_operand") (match_operand:VI 3 "vector_shift_operand")) - (match_operand:VI 4 "register_operand") + (match_operand:VI 4 "autovec_else_operand") (match_operand 5 "autovec_length_operand") (match_operand 6 "const_0_operand")] "TARGET_VECTOR" @@ -1614,7 +1614,7 @@ (any_int_binop_no_shift:VI (match_operand:VI 2 "<binop_rhs1_predicate>") (match_operand:VI 3 "<binop_rhs2_predicate>")) - (match_operand:VI 4 "register_operand")] + (match_operand:VI 4 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1631,7 +1631,7 @@ (any_int_binop_no_shift:VI (match_operand:VI 2 "<binop_rhs1_predicate>") (match_operand:VI 3 "<binop_rhs2_predicate>")) - (match_operand:VI 4 "register_operand") + (match_operand:VI 4 "autovec_else_operand") (match_operand 5 "autovec_length_operand") (match_operand 6 "const_0_operand")] "TARGET_VECTOR" @@ -1655,7 +1655,7 @@ (any_float_binop:VF (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "register_operand")] + (match_operand:VF 4 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1672,7 +1672,7 @@ (any_float_binop:VF (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "register_operand") + (match_operand:VF 4 "autovec_else_operand") (match_operand 5 "autovec_length_operand") (match_operand 6 "const_0_operand")] "TARGET_VECTOR" @@ -1694,7 +1694,7 @@ (any_float_binop_nofrm:VF (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "register_operand")] + (match_operand:VF 4 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1711,7 +1711,7 @@ (any_float_binop_nofrm:VF (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "register_operand") + (match_operand:VF 4 "autovec_else_operand") (match_operand 5 "autovec_length_operand") (match_operand 6 "const_0_operand")] "TARGET_VECTOR" @@ -1734,7 +1734,7 @@ (match_operand:VI 2 "register_operand") (match_operand:VI 3 "register_operand") (match_operand:VI 4 "register_operand") - (match_operand:VI 5 "register_operand")] + (match_operand:VI 5 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1751,7 +1751,7 @@ (match_operand:VI 2 "register_operand") (match_operand:VI 3 "register_operand") (match_operand:VI 4 "register_operand") - (match_operand:VI 5 "register_operand") + (match_operand:VI 5 "autovec_else_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] "TARGET_VECTOR" @@ -1767,7 +1767,7 @@ (match_operand:VI 2 "register_operand") (match_operand:VI 3 "register_operand") (match_operand:VI 4 "register_operand") - (match_operand:VI 5 "register_operand")] + (match_operand:VI 5 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1784,7 +1784,7 @@ (match_operand:VI 2 "register_operand") (match_operand:VI 3 "register_operand") (match_operand:VI 4 "register_operand") - (match_operand:VI 5 "register_operand") + (match_operand:VI 5 "autovec_else_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] "TARGET_VECTOR" @@ -1807,7 +1807,7 @@ (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand") (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "register_operand")] + (match_operand:VF 5 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1824,7 +1824,7 @@ (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand") (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "register_operand") + (match_operand:VF 5 "autovec_else_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] "TARGET_VECTOR" @@ -1840,7 +1840,7 @@ (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand") (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "register_operand")] + (match_operand:VF 5 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1857,7 +1857,7 @@ (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand") (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "register_operand") + (match_operand:VF 5 "autovec_else_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] "TARGET_VECTOR" @@ -1873,7 +1873,7 @@ (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand") (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "register_operand")] + (match_operand:VF 5 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1890,7 +1890,7 @@ (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand") (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "register_operand") + (match_operand:VF 5 "autovec_else_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] "TARGET_VECTOR" @@ -1906,7 +1906,7 @@ (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand") (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "register_operand")] + (match_operand:VF 5 "autovec_else_operand")] "TARGET_VECTOR" { /* Normalize into cond_len_* operations. */ @@ -1923,7 +1923,7 @@ (match_operand:VF 2 "register_operand") (match_operand:VF 3 "register_operand") (match_operand:VF 4 "register_operand") - (match_operand:VF 5 "register_operand") + (match_operand:VF 5 "autovec_else_operand") (match_operand 6 "autovec_length_operand") (match_operand 7 "const_0_operand")] "TARGET_VECTOR" diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index bf24189..6b72a5f 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -452,6 +452,10 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "vector_undef_operand"))) +(define_predicate "autovec_else_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "scratch_operand"))) + (define_predicate "vector_arith_operand" (ior (match_operand 0 "register_operand") (and (match_code "const_vector") diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 64a71a1..366f065 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3024,6 +3024,13 @@ expand_cond_len_op (unsigned icode, insn_flags op_type, rtx *ops, rtx len) emit_nonvlmax_insn (icode, insn_flags, ops, len); } +/* Return RVV_VUNDEF if the ELSE value is scratch rtx. */ +static rtx +get_else_operand (rtx op) +{ + return GET_CODE (op) == SCRATCH ? RVV_VUNDEF (GET_MODE (op)) : op; +} + /* Expand unary ops COND_LEN_*. */ void expand_cond_len_unop (unsigned icode, rtx *ops) @@ -3031,7 +3038,7 @@ expand_cond_len_unop (unsigned icode, rtx *ops) rtx dest = ops[0]; rtx mask = ops[1]; rtx src = ops[2]; - rtx merge = ops[3]; + rtx merge = get_else_operand (ops[3]); rtx len = ops[4]; rtx cond_ops[] = {dest, mask, merge, src}; @@ -3046,7 +3053,7 @@ expand_cond_len_binop (unsigned icode, rtx *ops) rtx mask = ops[1]; rtx src1 = ops[2]; rtx src2 = ops[3]; - rtx merge = ops[4]; + rtx merge = get_else_operand (ops[4]); rtx len = ops[5]; rtx cond_ops[] = {dest, mask, merge, src1, src2}; @@ -3218,7 +3225,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops) rtx src1 = ops[2]; rtx src2 = ops[3]; rtx src3 = ops[4]; - rtx merge = ops[5]; + rtx merge = get_else_operand (ops[5]); rtx len = ops[6]; rtx cond_ops[] = {dest, mask, src1, src2, src3, merge}; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6158953..6e7a719 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -72,6 +72,7 @@ along with GCC; see the file COPYING3. If not see #include "gimple-expr.h" #include "tree-vectorizer.h" #include "gcse.h" +#include "tree-dfa.h" /* This file should be included last. */ #include "target-def.h" @@ -9585,6 +9586,18 @@ riscv_vectorize_create_costs (vec_info *vinfo, bool costing_for_scalar) return new vector_costs (vinfo, costing_for_scalar); } +/* Implement TARGET_PREFERRED_ELSE_VALUE. */ + +static tree +riscv_preferred_else_value (unsigned ifn, tree vectype, unsigned int nops, + tree *ops) +{ + if (riscv_v_ext_mode_p (TYPE_MODE (vectype))) + return get_or_create_ssa_default_def (cfun, create_tmp_var (vectype)); + + return default_preferred_else_value (ifn, vectype, nops, ops); +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -9901,6 +9914,9 @@ riscv_vectorize_create_costs (vec_info *vinfo, bool costing_for_scalar) #undef TARGET_VECTORIZE_CREATE_COSTS #define TARGET_VECTORIZE_CREATE_COSTS riscv_vectorize_create_costs +#undef TARGET_PREFERRED_ELSE_VALUE +#define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c index 5ce2e57..f7d7704 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c @@ -10,3 +10,9 @@ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv4r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv8r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.i} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c index 9b984dd..bb421fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c @@ -12,3 +12,9 @@ /* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv4r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv8r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.i} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c index 7b1aa28..0dd4df6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c @@ -10,3 +10,9 @@ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv4r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv8r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.i} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c index ca4d23bb..9764cc3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c @@ -12,3 +12,9 @@ /* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv4r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv8r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.i} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c index 6d0493b..7628f4a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c @@ -5,3 +5,9 @@ /* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */ /* { dg-final { scan-assembler-times {\tvremu\.vv} 8 } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv4r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv8r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.i} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c index 24b2bc8..8af9a8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c @@ -6,3 +6,9 @@ /* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */ /* { dg-final { scan-assembler-times {\tvremu\.vv} 8 } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv4r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv8r\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.v} } } */ +/* { dg-final { scan-assembler-not {\tvmv\.v\.i} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c index 52861ee..c5fab3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c @@ -3,7 +3,5 @@ #include "ternop-1.c" -/* TODO: we don't have undefine IR for COND_LEN_* operations, - which will produce redundant move instructions here. - Will add assembler-not check of 'vmv' instructions in the future. */ /* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 3 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c index 01a5e99..a65c398 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c @@ -3,7 +3,5 @@ #include "ternop-10.c" -/* TODO: we don't have undefine IR for COND_LEN_* operations, - which will produce redundant move instructions here. - Will add assembler-not check of 'vmv' instructions in the future. */ /* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c index 1967142..9725cfa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c @@ -3,7 +3,5 @@ #include "ternop-11.c" -/* TODO: we don't have undefine IR for COND_LEN_* operations, - which will produce redundant move instructions here. - Will add assembler-not check of 'vmv' instructions in the future. */ /* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c index f2c2c73..97be71c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c @@ -4,3 +4,5 @@ #include "ternop-12.c" /* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */ +/* { dg-final { scan-assembler-times {\tvmv} 3 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c index ba07596..965365d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c @@ -4,8 +4,6 @@ #include "ternop-2.c" /* { dg-final { scan-assembler-times {\tvmacc\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {\tvfmacc\.vv} 9 } } */ -/* TODO: we don't have undefine IR for COND_LEN_* operations, - which will produce redundant move instructions here. - Will add assembler-not check of 'vmv' instructions in the future. */ +/* { dg-final { scan-assembler-times {\tvfma[c-d][c-d]\.vv} 9 } } */ /* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 9 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c index bc44644..de6d404 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c @@ -4,5 +4,6 @@ #include "ternop-3.c" /* { dg-final { scan-assembler-times {\tvmacc\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {\tvfmacc\.vv} 9 } } */ +/* { dg-final { scan-assembler-times {\tvfma[c-d][c-d]\.vv} 9 } } */ /* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 9 "optimized" } } */ +/* { dg-final { scan-assembler-times {\tvmv} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c index 96dd8a0..4d73a54 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c @@ -3,7 +3,5 @@ #include "ternop-4.c" -/* TODO: we don't have undefine IR for COND_LEN_* operations, - which will produce redundant move instructions here. - Will add assembler-not check of 'vmv' instructions in the future. */ /* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c index 2664efae..6fa28a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c @@ -3,7 +3,5 @@ #include "ternop-5.c" -/* TODO: we don't have undefine IR for COND_LEN_* operations, - which will produce redundant move instructions here. - Will add assembler-not check of 'vmv' instructions in the future. */ /* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c index 9f3d120..33faf05 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c @@ -4,3 +4,4 @@ #include "ternop-6.c" /* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */ +/* { dg-final { scan-assembler-times {\tvmv} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c index 8c07f19..4480799 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c @@ -3,7 +3,5 @@ #include "ternop-7.c" -/* TODO: we don't have undefine IR for COND_LEN_* operations, - which will produce redundant move instructions here. - Will add assembler-not check of 'vmv' instructions in the future. */ /* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 3 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c index e0cbc53..c89f583 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c @@ -3,7 +3,5 @@ #include "ternop-8.c" -/* TODO: we don't have undefine IR for COND_LEN_* operations, - which will produce redundant move instructions here. - Will add assembler-not check of 'vmv' instructions in the future. */ /* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 9 "optimized" } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c index f080d3a..2de649b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c @@ -4,3 +4,4 @@ #include "ternop-9.c" /* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 9 "optimized" } } */ +/* { dg-final { scan-assembler-times {\tvmv} 3 } } */ |