diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-protos.h | 2 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 26 |
3 files changed, 33 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9869d0a..223eb8b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2015-05-01 Wilco Dijkstra <wdijkstr@arm.com> + * gcc/config/aarch64/aarch64-protos.h (tune_params): + Add min_div_recip_mul_sf and min_div_recip_mul_df fields. + * gcc/config/aarch64/aarch64.c (aarch64_min_divisions_for_recip_mul): + Return value depending on target. + (generic_tunings): Initialize new target settings. + (cortexa53_tunings): Likewise. + (cortexa57_tunings): Likewise. + (thunderx_tunings): Likewise. + (xgene1_tunings): Likewise. + +2015-05-01 Wilco Dijkstra <wdijkstr@arm.com> + * gcc/config/arm/aarch-cost-tables.h (cortexa53_extra_costs): Make Cortex-A53 shift costs more accurate. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 8676c5c..08ce5f1 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -177,6 +177,8 @@ struct tune_params const int int_reassoc_width; const int fp_reassoc_width; const int vec_reassoc_width; + const int min_div_recip_mul_sf; + const int min_div_recip_mul_df; }; HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 94bdac7..374b0a9 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -354,7 +354,9 @@ static const struct tune_params generic_tunings = 4, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; static const struct tune_params cortexa53_tunings = @@ -372,7 +374,9 @@ static const struct tune_params cortexa53_tunings = 4, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; static const struct tune_params cortexa57_tunings = @@ -390,7 +394,9 @@ static const struct tune_params cortexa57_tunings = 4, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; static const struct tune_params thunderx_tunings = @@ -407,7 +413,9 @@ static const struct tune_params thunderx_tunings = 8, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; static const struct tune_params xgene1_tunings = @@ -424,7 +432,9 @@ static const struct tune_params xgene1_tunings = 16, /* loop_align. */ 2, /* int_reassoc_width. */ 4, /* fp_reassoc_width. */ - 1 /* vec_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2 /* min_div_recip_mul_df. */ }; /* A processor implementing AArch64. */ @@ -513,9 +523,11 @@ static const char * const aarch64_condition_codes[] = }; static unsigned int -aarch64_min_divisions_for_recip_mul (enum machine_mode mode ATTRIBUTE_UNUSED) +aarch64_min_divisions_for_recip_mul (enum machine_mode mode) { - return 2; + if (GET_MODE_UNIT_SIZE (mode) == 4) + return aarch64_tune_params->min_div_recip_mul_sf; + return aarch64_tune_params->min_div_recip_mul_df; } static int |