diff options
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/config/rs6000/altivec.h | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-builtin.def | 1 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-c.c | 38 | ||||
| -rw-r--r-- | gcc/doc/extend.texi | 50 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/altivec-13.c | 69 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/altivec-7-be.c | 35 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/altivec-7-le.c | 36 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/altivec-7.h (renamed from gcc/testsuite/gcc.target/powerpc/altivec-7.c) | 10 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 77 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/builtins-3.c | 179 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c | 83 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c | 31 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c | 32 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h (renamed from gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c) | 88 |
16 files changed, 737 insertions, 18 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 04fbd66..8073082 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2017-12-11 Carl Love <cel@us.ibm.com> + + * config/rs6000/altivec.h (vec_extract_fp32_from_shorth, + vec_extract_fp32_from_shortl]): Add #defines. + * config/rs6000/rs6000-builtin.def (VSLDOI_2DI): Add macro expansion. + * config/rs6000/rs6000-c.c (ALTIVEC_BUILTIN_VEC_UNPACKH, + ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VEC_AND, + ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VEC_SRL, + ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VEC_SLD, + ALTIVEC_BUILTIN_VEC_SLL): Add expansions. + * doc/extend.texi: Add documentation for the added builtins. + 2017-12-11 Alexandre Oliva <aoliva@redhat.com> PR rtl-optimization/80693 diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 068dfef..b58afd8 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -458,6 +458,8 @@ #define vec_extract_fp_from_shorth __builtin_vec_vextract_fp_from_shorth #define vec_extract_fp_from_shortl __builtin_vec_vextract_fp_from_shortl +#define vec_extract_fp32_from_shorth __builtin_vec_vextract_fp_from_shorth +#define vec_extract_fp32_from_shortl __builtin_vec_vextract_fp_from_shortl #define scalar_extract_exp __builtin_vec_scalar_extract_exp #define scalar_extract_sig __builtin_vec_scalar_extract_sig diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index cfb6e55..a563a5d 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -999,6 +999,7 @@ BU_ALTIVEC_3 (VSEL_1TI_UNS, "vsel_1ti_uns", CONST, vector_select_v1ti_uns) BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi) BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi) BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si) +BU_ALTIVEC_3 (VSLDOI_2DI, "vsldoi_2di", CONST, altivec_vsldoi_v2di) BU_ALTIVEC_3 (VSLDOI_4SF, "vsldoi_4sf", CONST, altivec_vsldoi_v4sf) BU_ALTIVEC_3 (VSLDOI_2DF, "vsldoi_2df", CONST, altivec_vsldoi_v2df) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 645260a..1bcdaa9 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -884,6 +884,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, + RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, @@ -914,6 +916,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX, + RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, @@ -1159,6 +1163,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -2653,6 +2659,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 }, + { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, @@ -2861,6 +2879,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, @@ -2893,6 +2915,15 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, @@ -3618,6 +3649,13 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, + { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_NOT_OPAQUE }, + { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, + { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE }, + { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index ad4d9d3..57c436b 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -16388,6 +16388,8 @@ vector unsigned char vec_vaddubs (vector unsigned char, vector float vec_and (vector float, vector float); vector float vec_and (vector float, vector bool int); vector float vec_and (vector bool int, vector float); +vector bool long long vec_and (vector bool long long int, + vector bool long long); vector bool int vec_and (vector bool int, vector bool int); vector signed int vec_and (vector bool int, vector signed int); vector signed int vec_and (vector signed int, vector bool int); @@ -17382,6 +17384,13 @@ vector unsigned char vec_sld (vector unsigned char, vector bool char vec_sld (vector bool char, vector bool char, const int); +vector bool long long int vec_sld (vector bool long long int, + vector bool long long int, const int); +vector long long int vec_sld (vector long long int, + vector long long int, const int); +vector unsigned long long int vec_sld (vector unsigned long long int, + vector unsigned long long int, + const int); vector signed char vec_sldw (vector signed char, vector signed char, @@ -17438,6 +17447,10 @@ vector unsigned short vec_sll (vector unsigned short, vector unsigned short); vector unsigned short vec_sll (vector unsigned short, vector unsigned char); +vector long long int vec_sll (vector long long int, + vector unsigned char); +vector unsigned long long int vec_sll (vector unsigned long long int, + vector unsigned char); vector bool short vec_sll (vector bool short, vector unsigned int); vector bool short vec_sll (vector bool short, vector unsigned short); vector bool short vec_sll (vector bool short, vector unsigned char); @@ -17594,6 +17607,10 @@ vector unsigned short vec_srl (vector unsigned short, vector unsigned short); vector unsigned short vec_srl (vector unsigned short, vector unsigned char); +vector long long int vec_srl (vector long long int, + vector unsigned char); +vector unsigned long long int vec_srl (vector unsigned long long int, + vector unsigned char); vector bool short vec_srl (vector bool short, vector unsigned int); vector bool short vec_srl (vector bool short, vector unsigned short); vector bool short vec_srl (vector bool short, vector unsigned char); @@ -17625,6 +17642,14 @@ vector unsigned short vec_sro (vector unsigned short, vector signed char); vector unsigned short vec_sro (vector unsigned short, vector unsigned char); +vector long long int vec_sro (vector long long int, + vector char); +vector long long int vec_sro (vector long long int, + vector unsigned char); +vector unsigned long long int vec_sro (vector unsigned long long int, + vector char); +vector unsigned long long int vec_sro (vector unsigned long long int, + vector unsigned char); vector pixel vec_sro (vector pixel, vector signed char); vector pixel vec_sro (vector pixel, vector unsigned char); vector signed char vec_sro (vector signed char, vector signed char); @@ -17894,6 +17919,7 @@ vector bool short vec_unpackh (vector bool char); vector signed int vec_unpackh (vector signed short); vector bool int vec_unpackh (vector bool short); vector unsigned int vec_unpackh (vector pixel); +vector double vec_unpackh (vector float); vector bool int vec_vupkhsh (vector bool short); vector signed int vec_vupkhsh (vector signed short); @@ -17908,6 +17934,7 @@ vector bool short vec_unpackl (vector bool char); vector unsigned int vec_unpackl (vector pixel); vector signed int vec_unpackl (vector signed short); vector bool int vec_unpackl (vector bool short); +vector double vec_unpackl (vector float); vector unsigned int vec_vupklpx (vector pixel); @@ -18656,9 +18683,18 @@ vector int vec_packs (vector long long, vector long long); vector unsigned int vec_packs (vector unsigned long long, vector unsigned long long); +test_vsi_packsu_vssi_vssi (vector signed short x, + +vector unsigned char vec_packsu (vector signed short, vector signed short ) +vector unsigned char vec_packsu (vector unsigned short, vector unsigned short ) +vector unsigned short int vec_packsu (vector signed int, vector signed int); +vector unsigned short int vec_packsu (vector unsigned int, + vector unsigned int); vector unsigned int vec_packsu (vector long long, vector long long); vector unsigned int vec_packsu (vector unsigned long long, vector unsigned long long); +vector unsigned int vec_packsu (vector signed long long, + vector signed long long); vector unsigned char vec_popcnt (vector signed char); vector unsigned char vec_popcnt (vector unsigned char); @@ -18887,9 +18923,21 @@ vector unsigned long long vec_bperm (vector unsigned long long, vector unsigned char); vector bool char vec_cmpne (vector bool char, vector bool char); -vector bool short vec_cmpne (vector bool short, vector bool short); +vector bool char vec_cmpne (vector signed char, vector signed char); +vector bool char vec_cmpne (vector unsigned char, vector unsigned char); vector bool int vec_cmpne (vector bool int, vector bool int); +vector bool int vec_cmpne (vector signed int, vector signed int); +vector bool int vec_cmpne (vector unsigned int, vector unsigned int); vector bool long long vec_cmpne (vector bool long long, vector bool long long); +vector bool long long vec_cmpne (vector signed long long, + vector signed long long); +vector bool long long vec_cmpne (vector unsigned long long, + vector unsigned long long); +vector bool short vec_cmpne (vector bool short, vector bool short); +vector bool short vec_cmpne (vector signed short, vector signed short); +vector bool short vec_cmpne (vector unsigned short, vector unsigned short); +vector bool long long vec_cmpne (vector double, vector double); +vector bool int vec_cmpne (vector float, vector float); vector float vec_extract_fp32_from_shorth (vector unsigned short); vector float vec_extract_fp32_from_shortl (vector unsigned short); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5cdd493..140df68 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2017-12-11 Carl Love <cel@us.ibm.com> + + * config/rs6000/altivec.h (vec_extract_fp32_from_shorth, + vec_extract_fp32_from_shortl]): Add #defines. + * config/rs6000/rs6000-builtin.def (VSLDOI_2DI): Add macro expansion. + * config/rs6000/rs6000-c.c (ALTIVEC_BUILTIN_VEC_UNPACKH, + ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VEC_AND, + ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VEC_SRL, + ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VEC_SLD, + ALTIVEC_BUILTIN_VEC_SLL): Add expansions. + * doc/extend.texi: Add documentation for the added builtins. + 2017-12-11 Alexandre Oliva <aoliva@redhat.com> PR rtl-optimization/80693 diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-13.c b/gcc/testsuite/gcc.target/powerpc/altivec-13.c index 22ff951..2315f6e 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-13.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-13.c @@ -1,6 +1,7 @@ /* { dg-do compile { target powerpc*-*-* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-options "-maltivec" } */ + /* Author: Ziemowit Laski <zlaski@apple.com> */ /* This test case exercises intrinsic/argument combinations that, @@ -14,8 +15,74 @@ void foo (void) vector bool int boolVec1 = (vector bool int) vec_splat_u32(3); vector bool short boolVec2 = (vector bool short) vec_splat_u16(3); vector bool char boolVec3 = (vector bool char) vec_splat_u8(3); - + vector signed char vsc1, vsc2, vscz; + vector unsigned char vuc1, vuc2, vucz; + vector signed short int vssi1, vssi2, vssiz; + vector signed int vsi1, vsi2, vsiz; + vector unsigned int vui1, vui2, vuiz; + vector unsigned short int vusi1, vusi2, vusiz; + vector bool long long vubll1, vubll2, vubllz; + vector signed int long long vsill1, vsill2, vsillz; + vector unsigned int long long vuill1, vuill2, vuillz; + vector pixel vp1, vp2, vpz; + vector float vf1, vf2, vfz; + vector double vd1, vd2, vdz; + boolVec1 = vec_sld( boolVec1, boolVec1, 4 ); boolVec2 = vec_sld( boolVec2, boolVec2, 2 ); boolVec3 = vec_sld( boolVec3, boolVec3, 1 ); + + vscz = vec_sld( vsc1, vsc2, 1 ); + vucz = vec_sld( vuc1, vuc2, 1 ); + vsiz = vec_sld( vsi1, vsi2, 1 ); + vuiz = vec_sld( vui1, vui2, 1 ); + vubllz = vec_sld( vubll1, vubll2, 1 ); + vsillz = vec_sld( vsill1, vsill2, 1 ); + vuillz = vec_sld( vuill1, vuill2, 1 ); + vssiz = vec_sld( vssi1, vssi2, 1 ); + vusiz = vec_sld( vusi1, vusi2, 1 ); + + vfz = vec_sld( vf1, vf2, 1 ); + vdz = vec_sld( vd1, vd2, 1 ); + + vpz = vec_sld( vp1, vp2, 1 ); + + vucz = vec_srl(vuc1, vuc2); + vsiz = vec_srl(vsi1, vuc2); + vuiz = vec_srl(vui1, vuc2); + vsillz = vec_srl(vsill1, vuc2); + vuillz = vec_srl(vuill1, vuc2); + vpz = vec_srl(vp1, vuc2); + vssiz = vec_srl(vssi1, vuc2); + vusiz = vec_srl(vusi1, vuc2); + + vscz = vec_sro(vsc1, vsc2); + vscz = vec_sro(vsc1, vuc2); + vucz = vec_sro(vuc1, vsc2); + vucz = vec_sro(vuc1, vuc2); + vsiz = vec_sro(vsi1, vsc2); + vsiz = vec_sro(vsi1, vuc2); + vuiz = vec_sro(vui1, vsc2); + vuiz = vec_sro(vui1, vuc2); + vsillz = vec_sro(vsill1, vsc2); + vsillz = vec_sro(vsill1, vuc2); + vuillz = vec_sro(vuill1, vsc2); + vuillz = vec_sro(vuill1, vuc2); + vpz = vec_sro(vp1, vsc2); + vpz = vec_sro(vp1, vuc2); + vssiz = vec_sro(vssi1, vsc2); + vssiz = vec_sro(vssi1, vuc2); + vusiz = vec_sro(vusi1, vsc2); + vusiz = vec_sro(vusi1, vuc2); + vfz = vec_sro(vf1, vsc2); + vfz = vec_sro(vf1, vuc2); } + +/* Expected results: + vec_sld vsldoi + vec_srl vsr + vec_sro vsro */ + +/* { dg-final { scan-assembler-times "vsldoi" 15 } } */ +/* { dg-final { scan-assembler-times "vsr " 8 } } */ +/* { dg-final { scan-assembler-times "vsro" 20 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c b/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c new file mode 100644 index 0000000..cbc31e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target powerpc64-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Expected results for Big Endian: + vec_packpx vpkpx + vec_ld lxv2x + vec_lde lvewx + vec_ldl lxvl + vec_lvewx lvewx + vec_unpackh vupklsh + vec_unpackl vupkhsh + vec_andc xxnor + xxland + vec_vxor xxlxor + vec_vmsumubm vmsumubm + vec_vmulesb vmulesb + vec_vmulosb vmulosb +*/ + +/* { dg-final { scan-assembler-times "vpkpx" 2 } } */ +/* { dg-final { scan-assembler-times "vmulesb" 1 } } */ +/* { dg-final { scan-assembler-times "vmulosb" 1 } } */ +/* { dg-final { scan-assembler-times "lxvd2x" 6 } } */ +/* { dg-final { scan-assembler-times "lvewx" 2 } } */ +/* { dg-final { scan-assembler-times "lvxl" 1 } } */ +/* { dg-final { scan-assembler-times "vupklsh" 1 } } */ +/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 4 } } */ +/* { dg-final { scan-assembler-times "xxland" 4 } } */ +/* { dg-final { scan-assembler-times "xxlxor" 5 } } */ +/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */ + +/* Source code for the test in altivec-7.h */ +#include "altivec-7.h" diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c b/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c new file mode 100644 index 0000000..a154911 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target powerpc64le-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Expected results for Little Endian: + vec_packpx vpkpx + vec_vmulosb vmulesb + vec_ld lxv2x + vec_lde lvewx + vec_ldl lxvl + vec_lvewx lvewx + vec_unpackh vupklsh + vec_unpackl vupkhsh + vec_andc xxnor + xxland + vec_vxor xxlxor + vec_vmsumubm vmsumubm + vec_vmulesb vmulosb + vec_vmulosb vmulesb +*/ + +/* { dg-final { scan-assembler-times "vpkpx" 2 } } */ +/* { dg-final { scan-assembler-times "vmulesb" 1 } } */ +/* { dg-final { scan-assembler-times "vmulosb" 1 } } */ +/* { dg-final { scan-assembler-times "lxvd2x" 36 } } */ +/* { dg-final { scan-assembler-times "lvewx" 2 } } */ +/* { dg-final { scan-assembler-times "lvxl" 1 } } */ +/* { dg-final { scan-assembler-times "vupklsh" 1 } } */ +/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 4 } } */ +/* { dg-final { scan-assembler-times "xxland" 4 } } */ +/* { dg-final { scan-assembler-times "xxlxor" 5 } } */ +/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */ + +/* Source code for the test in altivec-7.h */ +#include "altivec-7.h" diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.h index 30a1ee5..ff87deb 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.h @@ -1,8 +1,8 @@ /* Origin: Aldy Hernandez <aldyh@redhat.com> */ -/* { dg-do compile { target powerpc*-*-* } } */ -/* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-options "-maltivec" } */ +/* This test code is included into altivec-7-be.c and altivec-7-le.c. + The two files have the tests for the number of instructions generated for + LE versus BE. */ #include <altivec.h> @@ -17,6 +17,7 @@ vector unsigned char *vecuchar; vector unsigned int *vecuint; vector unsigned short *vecushort; vector float *vecfloat; +vector double *vecdouble; int main () { @@ -26,6 +27,7 @@ int main () *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]); *varpixel++ = vec_packpx(vecuint[0], vecuint[1]); *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]); + *vecshort++ = vec_vmulesb(vecchar[0], vecchar[1]); *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]); *vecint++ = vec_ld(var_int[0], intp[1]); *vecint++ = vec_lde(var_int[0], intp[1]); @@ -41,6 +43,8 @@ int main () *vecuint++ = vec_lvx(var_int[0], uintp[1]); *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]); *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]); + *vecdouble++ = vec_unpackl(vecfloat[0]); + *vecdouble++ = vec_unpackh(vecfloat[0]); return 0; } diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c index bc1c850..83d538b 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c @@ -16,6 +16,34 @@ test_pack_float (vector double x, vector double y) return vec_pack (x, y); } +vector unsigned char +test_vsi_packs_vusi_vusi (vector unsigned short x, + vector unsigned short y) +{ + return vec_packs (x, y); +} + +vector signed char +test_vsi_packs_vssi_vssi (vector signed short x, + vector signed short y) +{ + return vec_packs (x, y); +} + +vector signed short int +test_vsi_packs_vsi_vsi (vector signed int x, + vector signed int y) +{ + return vec_packs (x, y); +} + +vector unsigned short int +test_vsi_packs_vui_vui (vector unsigned int x, + vector unsigned int y) +{ + return vec_packs (x, y); +} + vector signed int test_vsi_packs_vsll_vsll (vector signed long long x, vector signed long long y) @@ -31,6 +59,48 @@ test_vui_packs_vull_vull (vector unsigned long long x, } vector unsigned char +test_vsi_packsu_vssi_vssi (vector signed short x, + vector signed short y) +{ + return vec_packsu (x, y); +} + +vector unsigned char +test_vsi_packsu_vusi_vusi (vector unsigned short x, + vector unsigned short y) +{ + return vec_packsu (x, y); +} + +vector unsigned int +test_vsi_packsu_vsll_vsll (vector signed long long x, + vector signed long long y) +{ + return vec_packsu (x, y); +} + +vector unsigned int +test_vsi_packsu_vull_vull (vector unsigned long long x, + vector unsigned long long y) +{ + return vec_packsu (x, y); +} + +vector unsigned short int +test_vsi_packsu_vsi_vsi (vector signed int x, + vector signed int y) +{ + return vec_packsu (x, y); +} + +vector unsigned short int +test_vsi_packsu_vui_vui (vector unsigned int x, + vector unsigned int y) +{ + return vec_packsu (x, y); +} + +vector unsigned char test_unsigned_char_popcnt_signed_char (vector signed char x) { return vec_popcnt (x); @@ -115,6 +185,8 @@ test_vull_mulo_vui_vui (vector unsigned int x, vector unsigned int y) test_pack_float 1 vpkudum inst test_vsi_packs_vsll_vsll 1 vpksdss test_vui_packs_vull_vull 1 vpkudus + test_vui_packs_vssi_vssi 1 vpkshss + test_vsi_packsu_vssi_vssi 1 vpkshus test_unsigned_char_popcnt_signed_char 1 vpopcntb test_unsigned_char_popcnt_unsigned_char 1 vpopcntb test_unsigned_short_popcnt_signed_short 1 vpopcnth @@ -133,6 +205,11 @@ test_vull_mulo_vui_vui (vector unsigned int x, vector unsigned int y) /* { dg-final { scan-assembler-times "vpkudum" 1 } } */ /* { dg-final { scan-assembler-times "vpksdss" 1 } } */ /* { dg-final { scan-assembler-times "vpkudus" 1 } } */ +/* { dg-final { scan-assembler-times "vpkuhus" 2 } } */ +/* { dg-final { scan-assembler-times "vpkshss" 1 } } */ +/* { dg-final { scan-assembler-times "vpkshus" 1 } } */ +/* { dg-final { scan-assembler-times "vpksdus" 2 } } */ +/* { dg-final { scan-assembler-times "vpkuwus" 2 } } */ /* { dg-final { scan-assembler-times "vpopcntb" 2 } } */ /* { dg-final { scan-assembler-times "vpopcnth" 2 } } */ /* { dg-final { scan-assembler-times "vpopcntw" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c index 42153da..833116e 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c @@ -88,26 +88,185 @@ test_neg_double (vector double x) return vec_neg (x); } +vector signed char +test_sll_vsc_vsc_vsuc (vector signed char x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector unsigned char +test_sll_vuc_vuc_vuc (vector unsigned char x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector signed int +test_sll_vsi_vsi_vuc (vector signed int x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector unsigned int +test_sll_vui_vui_vuc (vector unsigned int x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector bool long long +test_sll_vbll_vbll_vuc (vector bool long long x, + vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector bool long long +test_sll_vbll_vbll_vull (vector bool long long x, + vector unsigned long long y) +{ + return vec_sll (x, y); +} + +vector bool long long +test_sll_vbll_vbll_vus (vector bool long long x, + vector unsigned short y) +{ + return vec_sll (x, y); +} +vector pixel +test_sll_vp_vp_vuc (vector pixel x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector signed short int +test_sll_vssi_vssi_vuc (vector signed short x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector unsigned short int +test_sll_vusi_vusi_vuc (vector unsigned short x, vector unsigned char y) +{ + return vec_sll (x, y); +} + +vector signed char +test_slo_vsc_vsc_vsc (vector signed char x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector signed char +test_slo_vsc_vsc_vuc (vector signed char x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector unsigned char +test_slo_vuc_vuc_vsc (vector unsigned char x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector unsigned char +test_slo_vuc_vuc_vuc (vector unsigned char x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector signed int +test_slo_vsi_vsi_vsc (vector signed int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector signed int +test_slo_vsi_vsi_vuc (vector signed int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector unsigned int +test_slo_vui_vui_vsc (vector unsigned int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector unsigned int +test_slo_vui_vui_vuc (vector unsigned int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + vector signed long long -test_vsll_slo_vsll_vsc (vector signed long long x, vector signed char y) +test_slo_vsll_slo_vsll_vsc (vector signed long long x, vector signed char y) { return vec_slo (x, y); } vector signed long long -test_vsll_slo_vsll_vuc (vector signed long long x, vector unsigned char y) +test_slo_vsll_slo_vsll_vuc (vector signed long long x, vector unsigned char y) { return vec_slo (x, y); } vector unsigned long long -test_vull_slo_vull_vsc (vector unsigned long long x, vector signed char y) +test_slo_vull_slo_vull_vsc (vector unsigned long long x, vector signed char y) { return vec_slo (x, y); } vector unsigned long long -test_vull_slo_vull_vuc (vector unsigned long long x, vector unsigned char y) +test_slo_vull_slo_vull_vuc (vector unsigned long long x, + vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector pixel +test_slo_vp_vp_vsc (vector pixel int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector pixel +test_slo_vp_vp_vuc (vector pixel int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector signed short int +test_slo_vssi_vssi_vsc (vector signed short int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector signed short int +test_slo_vssi_vssi_vuc (vector signed short int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector unsigned short int +test_slo_vusi_vusi_vsc (vector unsigned short int x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector unsigned short int +test_slo_vusi_vusi_vuc (vector unsigned short int x, vector unsigned char y) +{ + return vec_slo (x, y); +} + +vector float +test_slo_vf_vf_vsc (vector float x, vector signed char y) +{ + return vec_slo (x, y); +} + +vector float +test_slo_vf_vf_vuc (vector float x, vector unsigned char y) { return vec_slo (x, y); } @@ -163,6 +322,12 @@ test_vul_sldw_vul_vul (vector unsigned long long x, return vec_sldw (x, y, 3); } +vector int +test_cmpb_float (vector float x, vector float y) +{ + return vec_cmpb (x, y); +} + /* Expected test results: test_eq_char 1 vcmpequb inst @@ -190,7 +355,8 @@ test_vul_sldw_vul_vul (vector unsigned long long x, test_vsi_mulo_vsi_vsi 1 xxsldwi test_vui_mulo_vui_vui 1 xxsldwi test_vsl_mulo_vsl_vsl 1 xxsldwi - test_vul_mulo_vul_vul 1 xxsldwi */ + test_vul_mulo_vul_vul 1 xxsldwi + test_cmpb_float 1 vcmpbfp */ /* { dg-final { scan-assembler-times "vcmpequb" 1 } } */ /* { dg-final { scan-assembler-times "vcmpequh" 1 } } */ @@ -207,5 +373,6 @@ test_vul_sldw_vul_vul (vector unsigned long long x, /* { dg-final { scan-assembler-times "xvnabsdp" 1 } } */ /* { dg-final { scan-assembler-times "xvnegsp" 1 } } */ /* { dg-final { scan-assembler-times "xvnegdp" 1 } } */ -/* { dg-final { scan-assembler-times "vslo" 4 } } */ +/* { dg-final { scan-assembler-times "vslo" 20 } } */ /* { dg-final { scan-assembler-times "xxsldwi" 8 } } */ +/* { dg-final { scan-assembler-times "vcmpbfp" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c index 7e1a251..0026097 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c @@ -9,6 +9,14 @@ typedef vector long long v_sign; typedef vector unsigned long long v_uns; typedef vector bool long long v_bool; +typedef vector bool char v_bchar; +typedef vector bool int v_bint; +typedef vector bool short v_bshort; +typedef vector signed int v_sint; +typedef vector unsigned int v_uint; +typedef vector signed char v_schar; +typedef vector unsigned char v_uchar; +typedef vector float v_float; v_sign sign_add_1 (v_sign a, v_sign b) { @@ -191,15 +199,88 @@ v_sign sign_sra_3 (v_sign a, v_uns b) return vec_vsrad (a, b); } +v_bchar vbchar_eq (v_bchar a, v_bchar b) +{ + return vec_cmpeq (a, b); +} + +v_bchar vbschar_eq (v_schar a, v_schar b) +{ + return vec_cmpeq (a, b); +} + +v_bchar vuchar_eq (v_uchar a, v_uchar b) +{ + return vec_cmpeq (a, b); +} + +v_bint vbint_eq (v_bint a, v_bint b) +{ + return vec_cmpeq (a, b); +} + +v_bint vsint_eq (v_sint a, v_sint b) +{ + return vec_cmpeq (a, b); +} + +v_bint vuint_eq (v_uint a, v_uint b) +{ + return vec_cmpeq (a, b); +} + +v_bool vbool_eq (v_bool a, v_bool b) +{ + return vec_cmpeq (a, b); +} + +v_bint vbint_ne (v_bint a, v_bint b) +{ + return vec_cmpne (a, b); +} + +v_bint vsint_ne (v_sint a, v_sint b) +{ + return vec_cmpne (a, b); +} + +v_bint vuint_ne (v_uint a, v_uint b) +{ + return vec_cmpne (a, b); +} + +v_bool vbool_ne (v_bool a, v_bool b) +{ + return vec_cmpne (a, b); +} + +v_bool vsign_ne (v_sign a, v_sign b) +{ + return vec_cmpne (a, b); +} + +v_bool vuns_ne (v_uns a, v_uns b) +{ + return vec_cmpne (a, b); +} + +v_bshort vbshort_ne (v_bshort a, v_bshort b) +{ + return vec_cmpne (a, b); +} + + /* { dg-final { scan-assembler-times "vaddudm" 5 } } */ /* { dg-final { scan-assembler-times "vsubudm" 6 } } */ /* { dg-final { scan-assembler-times "vmaxsd" 4 } } */ /* { dg-final { scan-assembler-times "vminsd" 3 } } */ /* { dg-final { scan-assembler-times "vmaxud" 2 } } */ /* { dg-final { scan-assembler-times "vminud" 2 } } */ -/* { dg-final { scan-assembler-times "vcmpequd" 2 } } */ +/* { dg-final { scan-assembler-times "vcmpequd" 6 } } */ /* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */ /* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */ /* { dg-final { scan-assembler-times "vrld" 3 } } */ /* { dg-final { scan-assembler-times "vsld" 5 } } */ /* { dg-final { scan-assembler-times "vsrad" 3 } } */ +/* { dg-final { scan-assembler-times "vcmpequb" 3 } } */ +/* { dg-final { scan-assembler-times "vcmpequw" 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c new file mode 100644 index 0000000..a33f6d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +/* Expected instruction counts for Big Endian */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 13 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c new file mode 100644 index 0000000..ad424b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +/* Expected instruction counts for Little Endian */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 6 } } */ +/* { dg-final { scan-assembler-times "xxlor" 16 } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 9 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h index fe1590a..422f8a1 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h @@ -1,19 +1,36 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-mvsx -O2" } */ +/* This test code is included into vsx-vector-6-be.c and vsx-vector-6-le.c. + The two files have the tests for the number of instructions generated for + LE versus BE. */ #include <altivec.h> -void foo (vector double *out, vector double *in, vector long *p_l, vector bool long *p_b, vector unsigned char *p_uc, int *i) +void foo (vector double *out, vector double *in, vector long *p_l, vector bool long *p_b, + vector unsigned char *p_uc, int *i, vector float *p_f, + vector bool char *outbc, vector bool int *outbi, + vector bool short *outbsi, vector int *outsi, vector unsigned int *outui) { vector double in0 = in[0]; vector double in1 = in[1]; vector double in2 = in[2]; vector long inl = *p_l; vector bool long inb = *p_b; + vector bool long long inbl0; + vector bool long long inbl1; vector unsigned char uc = *p_uc; - + vector float inf0; + vector float inf1; + vector float inf2; + vector bool char inbc0; + vector bool char inbc1; + vector bool short inbs0; + vector bool short inbs1; + vector bool int inbi0; + vector bool int inbi1; + vector signed short int inssi0, inssi1; + vector unsigned short int inusi0, inusi1; + vector signed int insi0, insi1; + vector unsigned int inui0, inui1; + *out++ = vec_abs (in0); *out++ = vec_add (in0, in1); *out++ = vec_and (in0, in1); @@ -22,6 +39,9 @@ void foo (vector double *out, vector double *in, vector long *p_l, vector bool l *out++ = vec_andc (in0, in1); *out++ = vec_andc (in0, inb); *out++ = vec_andc (inb, in0); + *out++ = vec_andc (inbl0, in0); + *out++ = vec_andc (in0, inbl0); + *out++ = vec_ceil (in0); *p_b++ = vec_cmpeq (in0, in1); *p_b++ = vec_cmpgt (in0, in1); @@ -78,4 +98,60 @@ void foo (vector double *out, vector double *in, vector long *p_l, vector bool l *i++ = vec_any_nle (in0, in1); *i++ = vec_any_nlt (in0, in1); *i++ = vec_any_numeric (in0); + + *p_f++ = vec_msub (inf0, inf1, inf2); + *p_f++ = vec_nmsub (inf0, inf1, inf2); + *p_f++ = vec_nmadd (inf0, inf1, inf2); + *p_f++ = vec_or (inf0, inf1); + + *out++ = vec_or (inbl0, in0); + *out++ = vec_or (in0, inbl0); + + *out++ = vec_nor (in0, in1); + + *outbc++ = vec_nor (inbc0, inbc1); + *outbc++ = vec_andc (inbc0, inbc1); + *outbc++ = vec_or (inbc0, inbc1); + + *outbi++ = vec_andc (inbi0, inbi1); + *outbsi++ = vec_andc (inbs0, inbs1); + + *outbsi++ = vec_andc (inbs0, inbs1); + + *outbi++ = vec_nor (inbi0, inbi1); + *outbi++ = vec_or (inbi0, inbi1); + + *outbsi++ = vec_nor (inbs0, inbs1); + *outbsi++ = vec_or (inbs0, inbs1); + + *outsi++ = vec_msums(inssi0, inssi1, insi0); + *outui++ = vec_msums(inusi0, inusi1, inui0); + + *p_f++ = vec_nor (inf0, inf1); + + *p_f++ = vec_andc (inf0, inf1); + *p_f++ = vec_andc (inbi0, inf0); + *p_f++ = vec_andc (inf0, inbi0); + + *in++ = vec_andc (inbl0, in1); + *in++ = vec_andc (in0, inbl1); +} + +int main() +{ + vector double *out; + vector double *in; + vector long *p_l; + vector bool long *p_b; + vector unsigned char *p_uc; + int *i; + vector float *p_f; + vector bool char *outbc; + vector bool int *outbi; + vector bool short *outbsi; + vector int *outsi; + vector unsigned int *outui; + + foo (out, in, p_l, p_b, p_uc, i, p_f, outbc, + outbi, outbsi, outsi, outui); } |